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Cleaned up the I-Cache memory.

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This commit is contained in:
Ross Thompson 2021-06-04 13:36:06 -05:00
parent fdef8df76b
commit e0d0fdd708
1 changed files with 57 additions and 70 deletions
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127
wally-pipelined/src/cache/ICacheMem.sv vendored
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@ -1,61 +1,54 @@
`include "wally-config.vh" `include "wally-config.vh"
module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) ( module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
// Pipeline stuff (
input logic clk, // Pipeline stuff
input logic reset, input logic clk,
// If flush is high, invalidate the entire cache input logic reset,
input logic flush, // If flush is high, invalidate the entire cache
input logic flush,
// Select which address to read (broken for efficiency's sake) // Select which address to read (broken for efficiency's sake)
input logic [`XLEN-1:0] PCTagF, // physical tag address input logic [`XLEN-1:0] PCTagF, // physical tag address
input logic [`XLEN-1:0] PCNextIndexF, input logic [`XLEN-1:0] PCNextIndexF,
// Write new data to the cache // Write new data to the cache
input logic WriteEnable, input logic WriteEnable,
input logic [BLOCKLEN-1:0] WriteLine, input logic [BLOCKLEN-1:0] WriteLine,
// Output the word, as well as if it is valid // Output the word, as well as if it is valid
output logic [31:0] DataWord, // *** was `XLEN-1 output logic [31:0] DataWord, // *** was `XLEN-1
output logic DataValid output logic DataValid
); );
// Various compile-time constants // divide the address bus into sections, tag, index, offset
localparam integer WORDWIDTH = $clog2(`XLEN/8); localparam BLOCKBYTELEN = BLOCKLEN/8;
localparam integer OFFSETWIDTH = $clog2(BLOCKLEN/`XLEN); localparam OFFSETLEN = $clog2(BLOCKBYTELEN);
localparam integer SETWIDTH = $clog2(NUMLINES); localparam INDEXLEN = $clog2(NUMLINES);
localparam integer TAGWIDTH = `XLEN - OFFSETWIDTH - SETWIDTH - WORDWIDTH; localparam TAGLEN = `XLEN - OFFSETLEN - INDEXLEN;
localparam integer OFFSETBEGIN = WORDWIDTH; // Machinery to read from and write to the correct addresses in memory
localparam integer OFFSETEND = OFFSETBEGIN+OFFSETWIDTH-1; logic [BLOCKLEN-1:0] ReadLine;
localparam integer SETBEGIN = OFFSETEND+1;
localparam integer SETEND = SETBEGIN + SETWIDTH - 1;
localparam integer TAGBEGIN = SETEND + 1;
localparam integer TAGEND = TAGBEGIN + TAGWIDTH - 1;
// Machinery to read from and write to the correct addresses in memory // Machinery to check if a given read is valid and is the desired value
logic [BLOCKLEN-1:0] ReadLine; logic [TAGLEN-1:0] DataTag;
logic [BLOCKLEN/`XLEN-1:0][`XLEN-1:0] ReadLineTransformed; logic [NUMLINES-1:0] ValidOut;
logic DataValidBit;
// Machinery to check if a given read is valid and is the desired value // Depth is number of bits in one "word" of the memory, width is number of such words
logic [TAGWIDTH-1:0] DataTag; sram1rw #(.DEPTH(BLOCKLEN), .WIDTH(NUMLINES))
logic [NUMLINES-1:0] ValidOut; cachemem (.*,
logic DataValidBit; .Addr(PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.ReadData(ReadLine),
.WriteData(WriteLine)
);
sram1rw #(.DEPTH(TAGLEN), .WIDTH(NUMLINES))
cachetags (.*,
.Addr(PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.ReadData(DataTag),
.WriteData(PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN])
);
// Depth is number of bits in one "word" of the memory, width is number of such words // Pick the right bits coming out the read line
sram1rw #(.DEPTH(BLOCKLEN), .WIDTH(NUMLINES)) cachemem ( //assign DataWord = ReadLineTransformed[ReadOffset];
.*,
.Addr(PCNextIndexF[SETEND:SETBEGIN]),
.ReadData(ReadLine),
.WriteData(WriteLine)
);
sram1rw #(.DEPTH(TAGWIDTH), .WIDTH(NUMLINES)) cachetags (
.*,
.Addr(PCNextIndexF[SETEND:SETBEGIN]),
.ReadData(DataTag),
.WriteData(PCTagF[TAGEND:TAGBEGIN])
);
// Pick the right bits coming out the read line
//assign DataWord = ReadLineTransformed[ReadOffset];
//logic [31:0] tempRD; //logic [31:0] tempRD;
always_comb begin always_comb begin
case (PCTagF[4:1]) case (PCTagF[4:1])
@ -80,25 +73,19 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) (
15: DataWord = {16'b0, ReadLine[255:240]}; 15: DataWord = {16'b0, ReadLine[255:240]};
endcase endcase
end end
genvar i;
generate
for (i=0; i < BLOCKLEN/`XLEN; i++) begin
assign ReadLineTransformed[i] = ReadLine[(i+1)*`XLEN-1:i*`XLEN];
end
endgenerate
// Correctly handle the valid bits // Correctly handle the valid bits
always_ff @(posedge clk, posedge reset) begin always_ff @(posedge clk, posedge reset) begin
if (reset) begin if (reset) begin
ValidOut <= {NUMLINES{1'b0}}; ValidOut <= {NUMLINES{1'b0}};
end else if (flush) begin end else if (flush) begin
ValidOut <= {NUMLINES{1'b0}}; ValidOut <= {NUMLINES{1'b0}};
end else begin end else begin
if (WriteEnable) begin if (WriteEnable) begin
ValidOut[PCNextIndexF[SETEND:SETBEGIN]] <= 1; ValidOut[PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= 1;
end end
end end
DataValidBit <= ValidOut[PCNextIndexF[SETEND:SETBEGIN]]; DataValidBit <= ValidOut[PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]];
end end
assign DataValid = DataValidBit && (DataTag == PCTagF[TAGEND:TAGBEGIN]); assign DataValid = DataValidBit && (DataTag == PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]);
endmodule endmodule