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Update riscv-arch-test and enable remaining Zcf and Zcd tests

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This commit is contained in:
Jordan Carlin 2025-01-17 10:32:28 -08:00
parent d8b6d65f15
commit e0c4eee86c
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4 changed files with 8 additions and 11 deletions
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2
addins/riscv-arch-test

@ -1 +1 @@
Subproject commit 832ab11c093f332ef83ca9c0ef55845071a7cb3d Subproject commit eeffdf802c117f592b30e380b59caf48da384e76

11
testbench/tests.vh
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@ -537,7 +537,6 @@ string arch64cpriv[] = '{
"rv64i_m/C/src/cebreak-01.S" "rv64i_m/C/src/cebreak-01.S"
}; };
// Tests commented out pending riscv-arch-test issue #590
string arch64zcd[] = '{ string arch64zcd[] = '{
// `RISCVARCHTEST, // `RISCVARCHTEST,
"rv64i_m/D_Zcd/src/c.fld-01.S", "rv64i_m/D_Zcd/src/c.fld-01.S",
@ -3431,20 +3430,18 @@ string arch32cpriv[] = '{
"rv32i_m/C/src/cebreak-01.S" "rv32i_m/C/src/cebreak-01.S"
}; };
// Tests commented out pending riscv-arch-test issue #590
string arch32zcf[] = '{ string arch32zcf[] = '{
// `RISCVARCHTEST, // `RISCVARCHTEST,
// "rv32i_m/F_Zcf/src/c.flw-01.S", "rv32i_m/F_Zcf/src/c.flw-01.S",
// "rv32i_m/F_Zcf/src/c.flwsp-01.S", "rv32i_m/F_Zcf/src/c.flwsp-01.S",
// "rv32i_m/F_Zcf/src/c.fsw-01.S", "rv32i_m/F_Zcf/src/c.fsw-01.S",
"rv32i_m/F_Zcf/src/c.fswsp-01.S" "rv32i_m/F_Zcf/src/c.fswsp-01.S"
}; };
// Tests commented out pending riscv-arch-test issue #590
string arch32zcd[] = '{ string arch32zcd[] = '{
// `RISCVARCHTEST, // `RISCVARCHTEST,
"rv32i_m/D_Zcd/src/c.fld-01.S", "rv32i_m/D_Zcd/src/c.fld-01.S",
// "rv32i_m/D_Zcd/src/c.fldsp-01.S", "rv32i_m/D_Zcd/src/c.fldsp-01.S",
"rv32i_m/D_Zcd/src/c.fsd-01.S", "rv32i_m/D_Zcd/src/c.fsd-01.S",
"rv32i_m/D_Zcd/src/c.fsdsp-01.S" "rv32i_m/D_Zcd/src/c.fsdsp-01.S"
}; };

4
tests/riscof/spike/spike_rv32gc_isa.yaml
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@ -1,7 +1,7 @@
hart_ids: [0] hart_ids: [0]
hart0: hart0:
# ISA: RV32IMAFDCZicboz_Zicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh # ISA: RV32IMAFDCZicboz_Zicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
ISA: RV32IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh ISA: RV32IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zcf_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
physical_addr_sz: 32 physical_addr_sz: 32
User_Spec_Version: '2.3' User_Spec_Version: '2.3'
supported_xlen: [32] supported_xlen: [32]
@ -26,4 +26,4 @@ hart0:
legal: legal:
- extensions[25:0] bitmask [0x014112D, 0x0000000] - extensions[25:0] bitmask [0x014112D, 0x0000000]
wr_illegal: wr_illegal:
- Unchanged - Unchanged

2
tests/riscof/spike/spike_rv64gc_isa.yaml
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@ -1,7 +1,7 @@
hart_ids: [0] hart_ids: [0]
hart0: hart0:
# ISA: RV64IMAFDQCSUZicboz_Zicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh # ISA: RV64IMAFDQCSUZicboz_Zicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
# ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh # ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
physical_addr_sz: 56 physical_addr_sz: 56
User_Spec_Version: '2.3' User_Spec_Version: '2.3'