Fixed UART merge conflict

src/cvw.sv

@@ -148,7 +148,6 @@ typedef struct packed {
   int                  BPRED_SIZE;
   int                  BTB_SIZE;
 
-
 // FPU division architecture
   int           RADIX;
   int           DIVCOPIES;

src/uncore/gpio_apb.sv

@@ -151,4 +151,3 @@ module gpio_apb import cvw::*;  #(parameter cvw_t P) (
 
   assign GPIOIntr  = |{(rise_ip & rise_ie),(fall_ip & fall_ie),(high_ip & high_ie),(low_ip & low_ie)};
 endmodule
-

src/uncore/plic_apb.sv

@@ -97,6 +97,7 @@ module plic_apb import cvw::*;  #(parameter cvw_t P) (
   // ==================
   // Register Interface
   // ==================
+    
   always @(posedge PCLK) begin
     // resetting
     if (~PRESETn) begin
@@ -245,4 +246,3 @@ module plic_apb import cvw::*;  #(parameter cvw_t P) (
   assign MExtInt = |(threshMask[0] & priorities_with_irqs[0]);
   assign SExtInt = |(threshMask[1] & priorities_with_irqs[1]);
 endmodule
-

src/uncore/ram_ahb.sv

@@ -74,7 +74,6 @@ module ram_ahb import cvw::*;  #(parameter cvw_t P,
   ram1p1rwbe #(.DEPTH(RANGE/8), .WIDTH(P.XLEN)) memory(.clk(HCLK), .ce(1'b1), 
     .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam));
   
-
   // use this to add arbitrary latency to ram. Helps test AHB controller correctness
   if(`RAM_LATENCY > 0) begin
     logic [7:0]       NextCycle, Cycle;
@@ -110,4 +109,3 @@ module ram_ahb import cvw::*;  #(parameter cvw_t P,
   end
 
 endmodule
-  

src/uncore/rom_ahb.sv

@@ -48,4 +48,3 @@ module rom_ahb import cvw::*;  #(parameter cvw_t P,
   rom1p1r #(ADDR_WIDTH, P.XLEN, P.FPGA)
     memory(.clk(HCLK), .ce(1'b1), .addr(HADDR[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRom));  
 endmodule
-  

src/uncore/uartPC16550D.sv

@@ -122,6 +122,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   ///////////////////////////////////////////
   // Input synchronization: 2-stage synchronizer
   ///////////////////////////////////////////
+  
   always_ff @(posedge PCLK) begin
     {SINd, DSRbd, DCDbd, CTSbd, RIbd} <= #1 {SIN, DSRb, DCDb, CTSb, RIb};
     {SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync} <= #1 loop ? {SOUTbit, ~MCR[0], ~MCR[3], ~MCR[1], ~MCR[2]} : 
@@ -132,6 +133,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   ///////////////////////////////////////////
   // Register interface (Table 1, note some are read only and some write only)
   ///////////////////////////////////////////
+  
   always_ff @(posedge PCLK, negedge PRESETn) 
     if (~PRESETn) begin // Table 3 Reset Configuration
       IER <= #1 4'b0;
@@ -234,6 +236,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   ///////////////////////////////////////////
   // receive timing and control
   ///////////////////////////////////////////
+  
   always_ff @(posedge PCLK, negedge PRESETn)
     if (~PRESETn) begin
       rxoversampledcnt   <= #1 0;
@@ -266,6 +269,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   ///////////////////////////////////////////
   // receive shift register, buffer register, FIFO
   ///////////////////////////////////////////
+  
   always_ff @(posedge PCLK, negedge PRESETn)
     if (~PRESETn) rxshiftreg <= #1 10'b0000000001; // initialize so that there is a valid stop bit
     else if (rxcentered) rxshiftreg <= #1 {rxshiftreg[8:0], SINsync}; // capture bit
@@ -282,7 +286,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
 
   // ERROR CONDITIONS
   assign rxparity     = ^rxdata;
-  assign rxparityerr = (rxparity ^ rxparitybit ^ ~evenparitysel) & LCR[3]; // Check even/odd parity
+  assign rxparityerr  = (rxparity ^ rxparitybit ^ ~evenparitysel) & LCR[3]; // Check even/odd parity (*** check if LCR needs to be inverted)
   assign rxoverrunerr = fifoenabled ? (rxfifoentries == 15) : rxdataready; // overrun if FIFO or receive buffer register full 
   assign rxframingerr = ~rxstopbit; // framing error if no stop bit
   assign rxbreak      = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time
@@ -367,6 +371,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   ///////////////////////////////////////////
   // transmit timing and control
   ///////////////////////////////////////////
+  
   always_ff @(posedge PCLK, negedge PRESETn)
     if (~PRESETn) begin
       txoversampledcnt <= #1 0;
@@ -392,6 +397,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   ///////////////////////////////////////////
   // transmit holding register, shift register, FIFO
   ///////////////////////////////////////////
+  
   always_comb begin // compute value for parity and tx holding register
     nexttxdata = fifoenabled ? txfifo[txfifotail] : TXHR; // pick from FIFO or holding register
     case (LCR[1:0]) // compute parity from appropriate number of bits
@@ -491,6 +497,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   ///////////////////////////////////////////
   // interrupts
   ///////////////////////////////////////////
+  
   assign RXerr = |LSR[4:1]; // LS interrupt if any of the flags are true
   assign RXerrIP = RXerr & ~squashRXerrIP; // intr squashed upon reading LSR
   assign rxdataavailintr = fifoenabled ? rxfifotriggered : rxdataready; 

src/uncore/uart_apb.sv

@@ -96,4 +96,3 @@ module uart_apb import cvw::*; #(parameter cvw_t P) (
 );
 
 endmodule
-

src/uncore/uncore.sv

@@ -189,4 +189,3 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
     HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD});
   flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED);
 endmodule
-