diff --git a/Makefile b/Makefile
index 518bcd2dd..8336fe017 100644
--- a/Makefile
+++ b/Makefile
@@ -4,7 +4,11 @@
 
 all:
 	make install
-	make regression
+	make testfloat	
+	make riscof
+	make verify
+	make coverage
+	make benchmarks
 
 # install copies over the Makefile.include from riscv-isa-sim
 # And corrects the TARGETDIR path and the RISCV_PREFIX
@@ -18,9 +22,37 @@ install:
 	##rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
 	##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
 
-regression:
+riscof:
 	make -C sim
 
+testfloat:
+	cd ${WALLY}/addins/SoftFloat-3e/build/Linux-x86_64-GCC; make
+	cd ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC; make
+	cd ${WALLY}/tests/fp; ./create_all_vectors.sh
+
+verify:
+	cd ${WALLY}/sim; ./regression-wally
+	cd ${WALLY}/sim; ./sim-testfloat-batch all
+	make imperasdv
+
+imperasdv:
+	iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m
+	iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m
+
+coverage:
+	cd ${WALLY}/sim; ./regresssion-wally -coverage -fp
+
+benchmarks:
+	make coremark
+	make embench
+
+coremark:
+	cd ${WALLY}/benchmarks/coremark; make; make run
+
+embench:
+	cd ${WALLY}/benchmarks/embench; make; make run
+
+
 clean:
 	make clean -C sim
 
diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile
index 309ed11c5..81c2b0959 100644
--- a/benchmarks/coremark/Makefile
+++ b/benchmarks/coremark/Makefile
@@ -11,7 +11,11 @@ sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h  \
 	$(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \
 	$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
 ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32)
-ARCH := rv$(XLEN)gc
+#ARCH := rv$(XLEN)gc_zba_zbb_zbc_zbs
+#ARCH := rv$(XLEN)gc
+ARCH := rv$(XLEN)imc_zicsr
+#ARCH := rv$(XLEN)im_zicsr
+#ARCH := rv$(XLEN)i_zicsr
 PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
 	-mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-3-series -O3 -finline-functions -falign-jumps=4 \
 	-fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 \
diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh
index 8970b824b..cc6254079 100755
--- a/bin/wally-tool-chain-install.sh
+++ b/bin/wally-tool-chain-install.sh
@@ -45,7 +45,7 @@ sudo mkdir -p $RISCV
 # Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/)
 sudo apt update -y
 sudo apt upgrade -y
-sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev verilator automake autotools-dev libmpc-dev libmpfr-dev  gperf libtool patchutils bc 
+sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev  gperf libtool patchutils bc 
 # Other python libraries used through the book.
 sudo pip3 install matplotlib scipy scikit-learn adjustText lief
 
@@ -113,6 +113,23 @@ cd ../arch_test_target/spike/device
 sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include
 sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
 
+# Wally needs Verilator 5.0 or later.
+# Verilator needs to be built from scratch to get the latest version
+# apt-get install verilator installs version 4.028 as of 6/8/23
+sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlibc zlib1g 
+sudo apt-get install -y libfl2  libfl-dev  # Ubuntu only (ignore if gives error)
+cd $RISCV
+git clone https://github.com/verilator/verilator   # Only first time
+unsetenv VERILATOR_ROOT  # For csh; ignore error if on bash
+unset VERILATOR_ROOT  # For bash
+cd verilator
+git pull         # Make sure git repository is up-to-date
+git checkout master      # Use development branch (e.g. recent bug fixes)
+autoconf         # Create ./configure script
+./configure      # Configure and create Makefile
+make -j NUM_THREADS  # Build Verilator itself (if error, try just 'make')
+sudo make install
+
 # Sail (https://github.com/riscv/sail-riscv)
 # Sail is the new golden reference model for RISC-V.  Sail is written in OCaml, which 
 # is an object-oriented extension of ML, which in turn is a functional programming 
diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh
index db356f07d..14f329907 100644
--- a/config/buildroot/config.vh
+++ b/config/buildroot/config.vh
@@ -40,10 +40,16 @@ localparam IEEE754 = 0;
 localparam MISA = (32'h0014112D);
 localparam ZICSR_SUPPORTED = 1;
 localparam ZIFENCEI_SUPPORTED = 1;
-localparam ZICOUNTERS_SUPPORTED = 1;
+localparam ZICNTR_SUPPORTED = 1;
+localparam ZIHPM_SUPPORTED = 1;
 localparam COUNTERS = 12'd32;
 localparam ZFH_SUPPORTED = 0;
 localparam SSTC_SUPPORTED = 0;
+localparam ZICBOM_SUPPORTED = 0;
+localparam ZICBOZ_SUPPORTED = 0;
+localparam ZICBOP_SUPPORTED = 0;
+localparam SVPBMT_SUPPORTED = 0;
+
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;
diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh
index e5a09aea6..e19e5e892 100644
--- a/config/rv32e/config.vh
+++ b/config/rv32e/config.vh
@@ -41,9 +41,14 @@ localparam MISA = (32'h00000010);
 localparam ZICSR_SUPPORTED = 0;
 localparam ZIFENCEI_SUPPORTED = 0;
 localparam COUNTERS = 12'd0;
-localparam ZICOUNTERS_SUPPORTED = 0;
+localparam ZICNTR_SUPPORTED = 0;
+localparam ZIHPM_SUPPORTED = 0;
 localparam ZFH_SUPPORTED = 0;
 localparam SSTC_SUPPORTED = 0;
+localparam ZICBOM_SUPPORTED = 0;
+localparam ZICBOZ_SUPPORTED = 0;
+localparam ZICBOP_SUPPORTED = 0;
+localparam SVPBMT_SUPPORTED = 0;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;
diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh
index b966b6484..031cd523f 100644
--- a/config/rv32gc/config.vh
+++ b/config/rv32gc/config.vh
@@ -42,9 +42,14 @@ localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 |
 localparam ZICSR_SUPPORTED = 1;
 localparam ZIFENCEI_SUPPORTED = 1;
 localparam COUNTERS = 12'd32;
-localparam ZICOUNTERS_SUPPORTED = 1;
+localparam ZICNTR_SUPPORTED = 1;
+localparam ZIHPM_SUPPORTED = 1;
 localparam ZFH_SUPPORTED = 0;
 localparam SSTC_SUPPORTED = 1;
+localparam ZICBOM_SUPPORTED = 0;
+localparam ZICBOZ_SUPPORTED = 0;
+localparam ZICBOP_SUPPORTED = 0;
+localparam SVPBMT_SUPPORTED = 0;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;
diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh
index c70679912..892ee356b 100644
--- a/config/rv32i/config.vh
+++ b/config/rv32i/config.vh
@@ -40,10 +40,15 @@ localparam IEEE754 = 0;
 localparam MISA = (32'h00000104);
 localparam ZICSR_SUPPORTED = 0;
 localparam ZIFENCEI_SUPPORTED = 0;
-localparam COUNTERS = 12'd32;
-localparam ZICOUNTERS_SUPPORTED = 0;
+localparam COUNTERS = 0;
+localparam ZICNTR_SUPPORTED = 0;
+localparam ZIHPM_SUPPORTED = 0;
 localparam ZFH_SUPPORTED = 0;
 localparam SSTC_SUPPORTED = 0;
+localparam ZICBOM_SUPPORTED = 0;
+localparam ZICBOZ_SUPPORTED = 0;
+localparam ZICBOP_SUPPORTED = 0;
+localparam SVPBMT_SUPPORTED = 0;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 0;
diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh
index 17a9e193b..1359cae49 100644
--- a/config/rv32imc/config.vh
+++ b/config/rv32imc/config.vh
@@ -40,9 +40,14 @@ localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12);
 localparam ZICSR_SUPPORTED = 1;
 localparam ZIFENCEI_SUPPORTED = 1;
 localparam COUNTERS = 12'd32;
-localparam ZICOUNTERS_SUPPORTED = 1;
+localparam ZICNTR_SUPPORTED = 1;
+localparam ZIHPM_SUPPORTED = 1;
 localparam ZFH_SUPPORTED = 0;
 localparam SSTC_SUPPORTED = 0;
+localparam ZICBOM_SUPPORTED = 0;
+localparam ZICBOZ_SUPPORTED = 0;
+localparam ZICBOP_SUPPORTED = 0;
+localparam SVPBMT_SUPPORTED = 0;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;
diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh
index 949fc3092..48a341b93 100644
--- a/config/rv64fpquad/config.vh
+++ b/config/rv64fpquad/config.vh
@@ -41,9 +41,14 @@ localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20
 localparam ZICSR_SUPPORTED = 1;
 localparam ZIFENCEI_SUPPORTED = 1;
 localparam COUNTERS = 12'd32;
-localparam ZICOUNTERS_SUPPORTED = 1;
+localparam ZICNTR_SUPPORTED = 1;
+localparam ZIHPM_SUPPORTED = 1;
 localparam ZFH_SUPPORTED = 1;
 localparam SSTC_SUPPORTED = 0;
+localparam ZICBOM_SUPPORTED = 0;
+localparam ZICBOZ_SUPPORTED = 0;
+localparam ZICBOP_SUPPORTED = 0;
+localparam SVPBMT_SUPPORTED = 0;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;
diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh
index 709d3d248..243b6ed47 100644
--- a/config/rv64gc/config.vh
+++ b/config/rv64gc/config.vh
@@ -44,9 +44,14 @@ localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12
 localparam ZICSR_SUPPORTED = 1;
 localparam ZIFENCEI_SUPPORTED = 1;
 localparam COUNTERS = 12'd32;
-localparam ZICOUNTERS_SUPPORTED = 1;
+localparam ZICNTR_SUPPORTED = 1;
+localparam ZIHPM_SUPPORTED = 1;
 localparam ZFH_SUPPORTED = 0;
 localparam SSTC_SUPPORTED = 1;
+localparam ZICBOM_SUPPORTED = 0;
+localparam ZICBOZ_SUPPORTED = 0;
+localparam ZICBOP_SUPPORTED = 0;
+localparam SVPBMT_SUPPORTED = 0;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;
diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh
index cc0fea1fb..426a012ca 100644
--- a/config/rv64i/config.vh
+++ b/config/rv64i/config.vh
@@ -40,10 +40,15 @@ localparam IEEE754 = 0;
 localparam MISA = (32'h00000104);
 localparam ZICSR_SUPPORTED = 0;
 localparam ZIFENCEI_SUPPORTED = 0;
-localparam COUNTERS = 12'd32;
-localparam ZICOUNTERS_SUPPORTED = 0;
+localparam COUNTERS = 0;
+localparam ZICNTR_SUPPORTED = 0;
+localparam ZIHPM_SUPPORTED = 0;
 localparam ZFH_SUPPORTED = 0;
 localparam SSTC_SUPPORTED = 0;
+localparam ZICBOM_SUPPORTED = 0;
+localparam ZICBOZ_SUPPORTED = 0;
+localparam ZICBOP_SUPPORTED = 0;
+localparam SVPBMT_SUPPORTED = 0;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 0;
diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh
index 271fc7fe8..e897f3dd0 100644
--- a/config/shared/parameter-defs.vh
+++ b/config/shared/parameter-defs.vh
@@ -11,20 +11,25 @@ parameter cvw_t P = '{
   ZICSR_SUPPORTED :      ZICSR_SUPPORTED,
   ZIFENCEI_SUPPORTED :   ZIFENCEI_SUPPORTED,
   COUNTERS :             COUNTERS,
-  ZICOUNTERS_SUPPORTED : ZICOUNTERS_SUPPORTED,
+  ZICNTR_SUPPORTED :     ZICNTR_SUPPORTED,
+  ZIHPM_SUPPORTED :      ZIHPM_SUPPORTED,
   ZFH_SUPPORTED :        ZFH_SUPPORTED,
   SSTC_SUPPORTED :       SSTC_SUPPORTED,
-  VIRTMEM_SUPPORTED :        VIRTMEM_SUPPORTED,
-  VECTORED_INTERRUPTS_SUPPORTED :        VECTORED_INTERRUPTS_SUPPORTED,
-  BIGENDIAN_SUPPORTED :        BIGENDIAN_SUPPORTED,
-  SVADU_SUPPORTED :        SVADU_SUPPORTED,
-  ZMMUL_SUPPORTED :        ZMMUL_SUPPORTED,
+  VIRTMEM_SUPPORTED :    VIRTMEM_SUPPORTED,
+  VECTORED_INTERRUPTS_SUPPORTED : VECTORED_INTERRUPTS_SUPPORTED,
+  BIGENDIAN_SUPPORTED :  BIGENDIAN_SUPPORTED,
+  SVADU_SUPPORTED :      SVADU_SUPPORTED,
+  ZMMUL_SUPPORTED :      ZMMUL_SUPPORTED,
+  ZICBOM_SUPPORTED :     ZICBOM_SUPPORTED,
+  ZICBOZ_SUPPORTED :     ZICBOZ_SUPPORTED,
+  ZICBOP_SUPPORTED :     ZICBOP_SUPPORTED,
+  SVPBMT_SUPPORTED :     SVPBMT_SUPPORTED,
   BUS_SUPPORTED :        BUS_SUPPORTED,
-  DCACHE_SUPPORTED :        DCACHE_SUPPORTED,
-  ICACHE_SUPPORTED :        ICACHE_SUPPORTED,
-  ITLB_ENTRIES :        ITLB_ENTRIES,
-  DTLB_ENTRIES :        DTLB_ENTRIES,
-  DCACHE_NUMWAYS :        DCACHE_NUMWAYS,
+  DCACHE_SUPPORTED :     DCACHE_SUPPORTED,
+  ICACHE_SUPPORTED :     ICACHE_SUPPORTED,
+  ITLB_ENTRIES :         ITLB_ENTRIES,
+  DTLB_ENTRIES :         DTLB_ENTRIES,
+  DCACHE_NUMWAYS :       DCACHE_NUMWAYS,
   DCACHE_WAYSIZEINBYTES :        DCACHE_WAYSIZEINBYTES,
   DCACHE_LINELENINBITS :        DCACHE_LINELENINBITS,
   ICACHE_NUMWAYS :        ICACHE_NUMWAYS,
diff --git a/sim/FPbuild.txt b/sim/FPbuild.txt
new file mode 100644
index 000000000..edb4a645c
--- /dev/null
+++ b/sim/FPbuild.txt
@@ -0,0 +1,60 @@
+Procedure for Runnning SoftFloat/TestFloat with Wally
+
+1.) First, compile SoftFloat and TestFloat by going to the addins
+directory and finding the specific build directory (e.g.,
+Linux_x86_64-GCC.  Currently, we are using v3e of
+SoftFloat/TestFloat.  I am not sure of the order, but I always compile
+SoftFloat first as I believe TestFloat uses the static library
+SoftFloat creates.
+
+2.) Once compiled both, go to the tests/fp directory and run the
+create_vectors.sh Linux script.  In the past, we have automated this,
+but I believe this has fallen into more of a manual state lately.
+
+3.) Then, run remove_spaces.sh which will remove spaces from the
+output and put underscores between vectors (this helps differentiate
+the vectors that are generated).  Again, this can be combined with
+Step 2.
+
+4.) TestFloat is run from wally/cvw/sim and sim-testfloat-batch with
+its respective test.  The format is ./sim-testfloat-add add.  All of
+the tests are listed below.  This can be augmented or added to for
+other FP tests given by the great SoftFloat/TestFloat output.
+
+ cvtint - test integer conversion unit (fcvtint)
+ cvtfp  - test floating-point conversion unit (fcvtfp)
+ cmp    - test comparison unit's LT, LE, EQ opperations (fcmp)
+ add    - test addition
+ fma    - test fma
+ mul    - test mult with fma
+ sub    - test subtraction
+ div    - test division
+ sqrt   - test square root
+ all    - test everything
+
+4a.) Each test will test all its vectors - if you want to test a
+subset of the vectors (e.g., only binary16), you should modify the
+cvw/testbench/tests-fp.h and comment out the tests  you do not want to
+test.  The best way to do this is to comment out each item out with
+the // comment option in SV.  For example,
+
+string f128div[] = '{
+//	"f128_div_rne.tv",
+//	"f128_div_rz.tv",
+//	"f128_div_ru.tv",
+//	"f128_div_rd.tv",
+//	"f128_div_rnm.tv"
+};
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/src/fpu/fdivsqrt/fdivsqrtcycles.sv b/src/fpu/fdivsqrt/fdivsqrtcycles.sv
index ea89ce7c6..c7aea4588 100644
--- a/src/fpu/fdivsqrt/fdivsqrtcycles.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtcycles.sv
@@ -50,9 +50,10 @@ module fdivsqrtcycles import cvw::*;  #(parameter cvw_t P) (
   else if (P.FPSIZES == 3)
     always_comb
       case (FmtE)
-        P.FMT:  Nf = P.NF;
-        P.FMT1: Nf = P.NF1;
-        P.FMT2: Nf = P.NF2; 
+        P.FMT:   Nf = P.NF;
+        P.FMT1:  Nf = P.NF1;
+        P.FMT2:  Nf = P.NF2; 
+        default: Nf = 'x; // shouldn't happen
       endcase
   else if (P.FPSIZES == 4)  
     always_comb
diff --git a/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv
index 105778d0c..2cc42e54d 100644
--- a/src/fpu/postproc/cvtshiftcalc.sv
+++ b/src/fpu/postproc/cvtshiftcalc.sv
@@ -82,7 +82,7 @@ module cvtshiftcalc import cvw::*;  #(parameter cvw_t P) (
               P.FMT:  ResNegNF = -($clog2(P.NF)+1)'(P.NF);
               P.FMT1: ResNegNF = -($clog2(P.NF)+1)'(P.NF1);
               P.FMT2: ResNegNF = -($clog2(P.NF)+1)'(P.NF2);
-              default: ResNegNF = 1'bx;
+              default: ResNegNF = 'x;
           endcase
 
   end else if (P.FPSIZES == 4) begin        
diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 2bc65caa6..7493c5ccc 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -191,7 +191,7 @@ module bpred import cvw::*;  #(parameter cvw_t P) (
   if(`INSTR_CLASS_PRED) mux2 #(P.XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPWrongM, NextValidPCE);
   else  assign NextValidPCE = PCE;
 
-  if(P.ZICOUNTERS_SUPPORTED) begin
+  if(P.ZIHPM_SUPPORTED) begin
     logic [P.XLEN-1:0]       RASPCD, RASPCE;
     logic                   BTAWrongE, RASPredPCWrongE;  
     // performance counters
diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv
index ce20cf20d..0ee13d865 100644
--- a/src/privileged/csrc.sv
+++ b/src/privileged/csrc.sv
@@ -187,4 +187,4 @@ module csrc  import cvw::*;  #(parameter cvw_t P) (
     end
 endmodule
 
-//  mounteren should only exist if u-mode exists
+//  mounteren should only exist if u-mode exists
\ No newline at end of file
diff --git a/src/privileged/csri.sv b/src/privileged/csri.sv
index 46723a209..ca89617d9 100644
--- a/src/privileged/csri.sv
+++ b/src/privileged/csri.sv
@@ -34,6 +34,7 @@ module csri import cvw::*;  #(parameter cvw_t P) (
   input  logic [11:0]       CSRAdrM,
   input  logic              MExtInt, SExtInt, MTimerInt, STimerInt, MSwInt,
   input  logic [11:0]       MIDELEG_REGW,
+  input  logic              MENVCFG_STCE,
   output logic [11:0]       MIP_REGW, MIE_REGW,
   output logic [11:0]       MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
 );
@@ -60,7 +61,7 @@ module csri import cvw::*;  #(parameter cvw_t P) (
   if (P.S_SUPPORTED) begin:mask
     if (P.SSTC_SUPPORTED) begin
       assign MIP_WRITE_MASK = 12'h202; // SEIP and SSIP are writable, but STIP is not writable when STIMECMP is implemented (see SSTC spec)
-      assign STIP = STimerInt;
+      assign STIP = MENVCFG_STCE ? STimerInt : MIP_REGW_writeable[5];
     end else begin
       assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writeable in MIP (20210108-draft 3.1.9)
       assign STIP = MIP_REGW_writeable[5];
diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv
index 4d17f0cfd..61226f790 100644
--- a/src/privileged/csrm.sv
+++ b/src/privileged/csrm.sv
@@ -252,4 +252,4 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
     endcase
   end
   // verilator lint_on WIDTH
-endmodule
+endmodule
\ No newline at end of file
diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv
index 31a5019c2..97c8b3f22 100644
--- a/src/privileged/csrs.sv
+++ b/src/privileged/csrs.sv
@@ -175,4 +175,4 @@ module csrs import cvw::*;  #(parameter cvw_t P) (
                end       
     endcase
   end
-endmodule
+endmodule
\ No newline at end of file
diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv
index 65f7af42f..55db35f63 100644
--- a/src/privileged/csrsr.sv
+++ b/src/privileged/csrsr.sv
@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: Status register
+// Purpose: Status register (and environment configuration register and others shared across modes)
 //          See RISC-V Privileged Mode Specification 20190608 
 // 
 // Documentation: RISC-V System on Chip Design Chapter 5
diff --git a/src/wally/cvw.sv b/src/wally/cvw.sv
index dfcebcdea..239b93e45 100644
--- a/src/wally/cvw.sv
+++ b/src/wally/cvw.sv
@@ -47,8 +47,9 @@ typedef struct packed {
   // RISC-V Features
   logic         ZICSR_SUPPORTED;
   logic         ZIFENCEI_SUPPORTED;
-  logic [11:0]           COUNTERS;
-  logic         ZICOUNTERS_SUPPORTED;
+  logic [11:0]  COUNTERS;
+  logic         ZICNTR_SUPPORTED;
+  logic         ZIHPM_SUPPORTED;
   logic         ZFH_SUPPORTED;
   logic         SSTC_SUPPORTED;
   logic         VIRTMEM_SUPPORTED;
@@ -56,6 +57,10 @@ typedef struct packed {
   logic         BIGENDIAN_SUPPORTED;
   logic         SVADU_SUPPORTED;
   logic         ZMMUL_SUPPORTED;
+  logic         ZICBOM_SUPPORTED;
+  logic         ZICBOZ_SUPPORTED;
+  logic         ZICBOP_SUPPORTED;
+  logic         SVPBMT_SUPPORTED;
 
   // Microarchitectural Features
   logic         BUS_SUPPORTED;
diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 221c8d7f8..8801f5119 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -139,6 +139,7 @@ module wallyTracer(rvviTrace rvvi);
 	  CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW;
 	  CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW;
 	  CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW;
+	  CSRArray[12'h30A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW;
 	  CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW;
 	  CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW;
 	  CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW;
@@ -157,6 +158,7 @@ module wallyTracer(rvviTrace rvvi);
 	  CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW;
 	  CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW;
 	  CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW;
+	  CSRArray[12'h10A] = testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW;
 	  CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW;
 	  CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW;
 	  CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
@@ -189,6 +191,7 @@ module wallyTracer(rvviTrace rvvi);
 	  CSRArray[12'h344] = CSRArrayOld[12'h344];
 	  CSRArray[12'h304] = CSRArrayOld[12'h304];
 	  CSRArray[12'h301] = CSRArrayOld[12'h301];
+	  CSRArray[12'h30A] = CSRArrayOld[12'h30A];
 	  CSRArray[12'hF14] = CSRArrayOld[12'hF14];
 	  CSRArray[12'h340] = CSRArrayOld[12'h340];
 	  CSRArray[12'h342] = CSRArrayOld[12'h342];
@@ -207,6 +210,7 @@ module wallyTracer(rvviTrace rvvi);
 	  CSRArray[12'h105] = CSRArrayOld[12'h105];
 	  CSRArray[12'h141] = CSRArrayOld[12'h141];
 	  CSRArray[12'h106] = CSRArrayOld[12'h106];
+	  CSRArray[12'h10A] = CSRArrayOld[12'h10A];
 	  CSRArray[12'h180] = CSRArrayOld[12'h180];
 	  CSRArray[12'h140] = CSRArrayOld[12'h140];
 	  CSRArray[12'h143] = CSRArrayOld[12'h143];
@@ -308,6 +312,7 @@ module wallyTracer(rvviTrace rvvi);
     CSRArrayOld[12'h344] = CSRArray[12'h344];
     CSRArrayOld[12'h304] = CSRArray[12'h304];
     CSRArrayOld[12'h301] = CSRArray[12'h301];
+    CSRArrayOld[12'h30A] = CSRArray[12'h30A];
     CSRArrayOld[12'hF14] = CSRArray[12'hF14];
     CSRArrayOld[12'h340] = CSRArray[12'h340];
     CSRArrayOld[12'h342] = CSRArray[12'h342];
@@ -326,6 +331,7 @@ module wallyTracer(rvviTrace rvvi);
     CSRArrayOld[12'h105] = CSRArray[12'h105];
     CSRArrayOld[12'h141] = CSRArray[12'h141];
     CSRArrayOld[12'h106] = CSRArray[12'h106];
+    CSRArrayOld[12'h10A] = CSRArray[12'h10A];
     CSRArrayOld[12'h180] = CSRArray[12'h180];
     CSRArrayOld[12'h140] = CSRArray[12'h140];
     CSRArrayOld[12'h143] = CSRArray[12'h143];
@@ -352,6 +358,7 @@ module wallyTracer(rvviTrace rvvi);
   assign #2 CSR_W[12'h305] = (CSRArrayOld[12'h305] != CSRArray[12'h305]) ? 1 : 0;
   assign #2 CSR_W[12'h341] = (CSRArrayOld[12'h341] != CSRArray[12'h341]) ? 1 : 0;
   assign #2 CSR_W[12'h306] = (CSRArrayOld[12'h306] != CSRArray[12'h306]) ? 1 : 0;
+  assign #2 CSR_W[12'h30A] = (CSRArrayOld[12'h30A] != CSRArray[12'h30A]) ? 1 : 0;
   assign #2 CSR_W[12'h320] = (CSRArrayOld[12'h320] != CSRArray[12'h320]) ? 1 : 0;
   assign #2 CSR_W[12'h302] = (CSRArrayOld[12'h302] != CSRArray[12'h302]) ? 1 : 0;
   assign #2 CSR_W[12'h303] = (CSRArrayOld[12'h303] != CSRArray[12'h303]) ? 1 : 0;
@@ -374,6 +381,7 @@ module wallyTracer(rvviTrace rvvi);
   assign #2 CSR_W[12'h105] = (CSRArrayOld[12'h105] != CSRArray[12'h105]) ? 1 : 0;
   assign #2 CSR_W[12'h141] = (CSRArrayOld[12'h141] != CSRArray[12'h141]) ? 1 : 0;
   assign #2 CSR_W[12'h106] = (CSRArrayOld[12'h106] != CSRArray[12'h106]) ? 1 : 0;
+  assign #2 CSR_W[12'h10A] = (CSRArrayOld[12'h10A] != CSRArray[12'h10A]) ? 1 : 0;
   assign #2 CSR_W[12'h180] = (CSRArrayOld[12'h180] != CSRArray[12'h180]) ? 1 : 0;
   assign #2 CSR_W[12'h140] = (CSRArrayOld[12'h140] != CSRArray[12'h140]) ? 1 : 0;
   assign #2 CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0;
@@ -394,6 +402,7 @@ module wallyTracer(rvviTrace rvvi);
   assign rvvi.csr_wb[0][0][12'h303] = CSR_W[12'h303];
   assign rvvi.csr_wb[0][0][12'h344] = CSR_W[12'h344];
   assign rvvi.csr_wb[0][0][12'h304] = CSR_W[12'h304];
+  assign rvvi.csr_wb[0][0][12'h30A] = CSR_W[12'h30A];
   assign rvvi.csr_wb[0][0][12'h301] = CSR_W[12'h301];
   assign rvvi.csr_wb[0][0][12'hF14] = CSR_W[12'hF14];
   assign rvvi.csr_wb[0][0][12'h340] = CSR_W[12'h340];
@@ -411,6 +420,7 @@ module wallyTracer(rvviTrace rvvi);
   assign rvvi.csr_wb[0][0][12'h105] = CSR_W[12'h105];
   assign rvvi.csr_wb[0][0][12'h141] = CSR_W[12'h141];
   assign rvvi.csr_wb[0][0][12'h106] = CSR_W[12'h106];
+  assign rvvi.csr_wb[0][0][12'h10A] = CSR_W[12'h10A];
   assign rvvi.csr_wb[0][0][12'h180] = CSR_W[12'h180];
   assign rvvi.csr_wb[0][0][12'h140] = CSR_W[12'h140];
   assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143];
@@ -431,6 +441,7 @@ module wallyTracer(rvviTrace rvvi);
   assign rvvi.csr[0][0][12'h303]    = CSRArray[12'h303];
   assign rvvi.csr[0][0][12'h344]    = CSRArray[12'h344];
   assign rvvi.csr[0][0][12'h304]    = CSRArray[12'h304];
+  assign rvvi.csr[0][0][12'h30A]    = CSRArray[12'h30A];
   assign rvvi.csr[0][0][12'h301]    = CSRArray[12'h301];
   assign rvvi.csr[0][0][12'hF14]    = CSRArray[12'hF14];
   assign rvvi.csr[0][0][12'h340]    = CSRArray[12'h340];
@@ -448,6 +459,7 @@ module wallyTracer(rvviTrace rvvi);
   assign rvvi.csr[0][0][12'h105]    = CSRArray[12'h105];
   assign rvvi.csr[0][0][12'h141]    = CSRArray[12'h141];
   assign rvvi.csr[0][0][12'h106]    = CSRArray[12'h106];
+  assign rvvi.csr[0][0][12'h10A]    = CSRArray[12'h10A];
   assign rvvi.csr[0][0][12'h180]    = CSRArray[12'h180];
   assign rvvi.csr[0][0][12'h140]    = CSRArray[12'h140];
   assign rvvi.csr[0][0][12'h143]    = CSRArray[12'h143];
diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv
index aaf280626..63660b025 100644
--- a/testbench/testbench-fp.sv
+++ b/testbench/testbench-fp.sv
@@ -113,8 +113,6 @@ module testbenchfp;
 
   `include "parameter-defs.vh"
   
-
-
   ///////////////////////////////////////////////////////////////////////////////////////////////
 
   //     ||||||||| |||||||| ||||||| |||||||||   ||||||| |||||||| |||
@@ -680,11 +678,11 @@ module testbenchfp;
   // instantiate devices under test
   if (TEST === "fma"| TEST === "mul" | TEST === "add" | TEST === "sub" | TEST === "all") begin : fma
     fma #(P) fma(.Xs(Xs), .Ys(Ys), .Zs(Zs), 
-            .Xe(Xe), .Ye(Ye), .Ze(Ze), 
-            .Xm(Xm), .Ym(Ym), .Zm(Zm),
-            .XZero, .YZero, .ZZero, .Ss, .Se,
-            .OpCtrl(OpCtrlVal), .Sm, .InvA, .SCnt, .As, .Ps,
-            .ASticky); 
+                 .Xe(Xe), .Ye(Ye), .Ze(Ze), 
+                 .Xm(Xm), .Ym(Ym), .Zm(Zm),
+                 .XZero, .YZero, .ZZero, .Ss, .Se,
+                 .OpCtrl(OpCtrlVal), .Sm, .InvA, .SCnt, .As, .Ps,
+                 .ASticky); 
   end
               
   postprocess #(P) postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]),
@@ -699,13 +697,13 @@ module testbenchfp;
               .PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes));
   
   if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt
-    fcvt #(P) fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), 
+    fcvt fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), 
               .XZero(XZero), .OpCtrl(OpCtrlVal), .IntZero,
               .Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE), .ResSubnormUf(CvtResSubnormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE));
   end
 
   if (TEST === "cmp" | TEST === "all") begin: fcmp
-    fcmp #(P) fcmp   (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye, 
+    fcmp fcmp   (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye, 
                 .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes),
                 .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
   end
@@ -892,13 +890,13 @@ always @(negedge clk) begin
     // check if result is correct
     //  - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
    // if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&~((FDivBusyE===1'b1)|DivStart)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
-    ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx);
-    FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx);
-    divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL;
+    assign ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx);
+    assign FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx);
+    assign divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL;
     assign DivDone = OldFDivBusyE & ~FDivBusyE;
 
     //assign divsqrtop = OpCtrl[TestNum] == `SQRT_OPCTRL | OpCtrl[TestNum] == `DIV_OPCTRL;
-    CheckNow = (DivDone | ~divsqrtop) & (UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT);
+    assign CheckNow = (DivDone | ~divsqrtop) & (UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT);
     if(~(ResMatch & FlagMatch) & CheckNow) begin
 //    if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(DivDone | (TEST != "sqrt" & TEST != "div"))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
       errors += 1;
@@ -974,10 +972,10 @@ module readvectors (
   output logic [`FLEN-1:0]   Ans,
   output logic [`XLEN-1:0]   SrcA,
   output logic [4:0]         AnsFlg,
-  output logic               Xs, Ys, Zs, // sign bits of XYZ
-  output logic [`NE-1:0]     Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision)
-  output logic [`NF:0]       Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision)
-  output logic               XNaN, YNaN, ZNaN, // is XYZ a NaN
+  output logic               Xs, Ys, Zs,          // sign bits of XYZ
+  output logic [`NE-1:0]     Xe, Ye, Ze,          // exponents of XYZ (converted to largest supported precision)
+  output logic [`NF:0]       Xm, Ym, Zm,          // mantissas of XYZ (converted to largest supported precision)
+  output logic               XNaN, YNaN, ZNaN,    // is XYZ a NaN
   output logic               XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN
   output logic               XSubnorm, ZSubnorm,  // is XYZ denormalized
   output logic               XZero, YZero, ZZero, // is XYZ zero
@@ -986,6 +984,7 @@ module readvectors (
   output logic               DivStart,
   output logic [`FLEN-1:0]   X, Y, Z, XPostBox
 );
+   
   logic XEn, YEn, ZEn;
 
   `include "parameter-defs.vh"
@@ -1346,7 +1345,6 @@ module readvectors (
   assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0]));
   assign ZEn = (Unit == `FMAUNIT);
   
-
   unpack #(P) unpack(.X, .Y, .Z, .Fmt(ModFmt), .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,
                 .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
                 .XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
diff --git a/testbench/testbench-linux-imperas.sv b/testbench/testbench-linux-imperas.sv
index d3d71626f..223e3529b 100644
--- a/testbench/testbench-linux-imperas.sv
+++ b/testbench/testbench-linux-imperas.sv
@@ -866,10 +866,12 @@ module testbench;
             "medeleg": `checkCSR(`CSR_BASE.csrm.MEDELEG_REGW)
             "mepc":    `checkCSR(`CSR_BASE.csrm.MEPC_REGW)
             "mtval":   `checkCSR(`CSR_BASE.csrm.MTVAL_REGW)
+            "menvcfg": `checkCSR(`CSR_BASE.csrm.MENVCFG_REGW)
             "sepc":    `checkCSR(`CSR_BASE.csrs.csrs.SEPC_REGW)
             "scause":  `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW)
             "stvec":   `checkCSR(`CSR_BASE.csrs.csrs.STVEC_REGW)
             "stval":   `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW)
+            "senvcfg": `checkCSR(`CSR_BASE.csrs.SENVCFG_REGW)
             "mip": begin
                        `checkCSR(`CSR_BASE.csrm.MIP_REGW)
                        if(!NO_SPOOFING) begin
diff --git a/tests/coverage/csrwrites.S b/tests/coverage/csrwrites.S
index 41d211467..63ee00c38 100644
--- a/tests/coverage/csrwrites.S
+++ b/tests/coverage/csrwrites.S
@@ -33,5 +33,8 @@ main:
     csrrw t0, satp, zero
     csrrw t0, stvec, zero
     csrrw t0, sscratch, zero
+    li t0, -2
+    csrrw t1, menvcfg, t0
+    csrrw t2, senvcfg, t0
 
     j done
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
index d885ab6c0..d5a114ab3 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
@@ -1,3 +1,5 @@
+FFFFFFFF # stimecmp readback
+80000000 # menvcfg readback
 00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts # skipping instruction address fault since they're impossible with compressed instrs enabled
 00000001 # mcause from an instruction access fault
 00000000 # mtval of faulting instruction address (0x0)
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
index 277f67274..c51eec965 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
@@ -280,7 +280,7 @@ end_trap_triggers:
     la t4, 0x02004000    // MTIMECMP register in CLINT
     li t5, 0xFFFFFFFF
     sw t5, 0(t4) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
-
+ 
     j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
 
 	// ---------------------------------------------------------------------------------------------
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S
index d90dff9eb..2b5daf264 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I_Sstc_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap)
 
 INIT_TESTS
@@ -34,8 +34,9 @@ TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on tr
 
 li x28, 0x8
 csrs mstatus, x28 // set mstatus.MIE bit to 1
-WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
-
+WRITE_READ_CSR stimecmp, 0xFFFFFFFF // set timer to high value so it doesn't go off immediately
+WRITE_READ_CSR menvcfgh, 0x80000000 // Enable menvcfg.STCE
+WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources 
 // test 5.3.1.4 Basic trap tests 
 
 // instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled.
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
index cb872b5b8..5c9b816fb 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
@@ -1,3 +1,7 @@
+FFFFFFFF # stimecmp low bits
+00000000 # stimecmp high bits
+00000000 # menvcfg low bits
+80000000 # menvcfg high bits
 00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
 00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
 00000001 # mcause from an instruction access fault
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
index 44a4ea66f..1e887b9fb 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
@@ -274,7 +274,7 @@ end_trap_triggers:
     la t4, 0x02004000    // MTIMECMP register in CLINT
     li t5, 0xFFFFFFFF
     sd t5, 0(t4) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
-
+ 
     j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
 
 	// ---------------------------------------------------------------------------------------------
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
index 26c06e053..24caa603a 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I_Sstc_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap)
 
 INIT_TESTS
@@ -33,7 +33,9 @@ TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on tr
 
 li x28, 0x8
 csrs mstatus, x28 // set mstatus.MIE bit to 1
-WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources
+WRITE_READ_CSR stimecmp, 0xFFFFFFFF // set timer to high value so it doesn't go off immediately
+WRITE_READ_CSR menvcfg, 0x8000000000000000 // Enable menvcfg.STCE
+WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources 
 
 // test 5.3.1.4 Basic trap tests