From e0740034f0281430860fa10df5c213a82de33203 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 6 Jan 2022 16:32:49 -0600
Subject: [PATCH] Clean up of cachefsm.

---
 pipelined/src/cache/cache.sv    |  9 +--------
 pipelined/src/cache/cachefsm.sv | 13 ++++++-------
 2 files changed, 7 insertions(+), 15 deletions(-)

diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv
index a7c5e623c..f2d0b19ed 100644
--- a/pipelined/src/cache/cache.sv
+++ b/pipelined/src/cache/cache.sv
@@ -243,15 +243,8 @@ module cache #(parameter integer LINELEN,
   assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0];
   assign FlushWayFlag = FlushWay[NUMWAYS-1];
 
-  // controller
-  // *** fixme
-  logic CacheableM;
-  
-  assign CacheableM = 1;
-
-
   cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck, 
-					.RW, .Atomic, .CPUBusy, .CacheableM, .IgnoreRequest,
+					.RW, .Atomic, .CPUBusy, .IgnoreRequest,
  					.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, 
 					.CacheMiss, .CacheAccess, .SelAdr, .SetValid, 
 					.ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnable,
diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv
index b09f86a05..6201b82c5 100644
--- a/pipelined/src/cache/cachefsm.sv
+++ b/pipelined/src/cache/cachefsm.sv
@@ -34,7 +34,6 @@ module cachefsm
    input logic 		  FlushCache,
    // hazard inputs
    input logic 		  CPUBusy,
-   input logic 		  CacheableM,
    // interlock fsm
    input logic 		  IgnoreRequest,
    // Bus inputs
@@ -100,8 +99,8 @@ module cachefsm
   assign AnyCPUReqM = |RW | (|Atomic);
 
   // outputs for the performance counters.
-  assign CacheAccess = AnyCPUReqM & CacheableM & CurrState == STATE_READY;
-  assign CacheMiss = CacheAccess & CacheableM & ~CacheHit;
+  assign CacheAccess = AnyCPUReqM & CurrState == STATE_READY;
+  assign CacheMiss = CacheAccess &  ~CacheHit;
 
   always_ff @(posedge clk)
     if (reset)    CurrState <= #1 STATE_READY;
@@ -159,7 +158,7 @@ module cachefsm
 		end
 		
 		// amo hit
-		else if(Atomic[1] & (&RW) & CacheableM & CacheHit) begin
+		else if(Atomic[1] & (&RW) & CacheHit) begin
 		  SelAdr = 2'b01;
 		  CacheStall = 1'b0;
 		  
@@ -175,7 +174,7 @@ module cachefsm
 		  end
 		end
 		// read hit valid cached
-		else if(RW[1] & CacheableM & CacheHit) begin
+		else if(RW[1] & CacheHit) begin
 		  CacheStall = 1'b0;
 		  LRUWriteEn = 1'b1;
 		  
@@ -188,7 +187,7 @@ module cachefsm
 	      end
 		end
 		// write hit valid cached
-		else if (RW[0] & CacheableM & CacheHit) begin
+		else if (RW[0] & CacheHit) begin
 		  SelAdr = 2'b01;
 		  CacheStall = 1'b0;
 		  SRAMWordWriteEnable = 1'b1;
@@ -204,7 +203,7 @@ module cachefsm
 		  end
 		end
 		// read or write miss valid cached
-		else if((|RW) & CacheableM & ~CacheHit) begin
+		else if((|RW) & ~CacheHit) begin
 		  NextState = STATE_MISS_FETCH_WDV;
 		  CacheStall = 1'b1;
 		  CacheFetchLine = 1'b1;