Add alu + controller

src/ieu/aes_common/aes_inv_mixcols.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// aes_inv_mixcols.sv
+// aes_Inv_mixcols.sv
 //
 // Written: ryan.swann@okstate.edu, james.stine@okstate.edu
 // Created: 20 February 2024
@@ -25,17 +25,17 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aes_inv_mixcols (input  logic [127:0] data, output logic [127:0] mixed_col);
+module aes_Inv_mixcols (input  logic [127:0] Data, output logic [127:0] Mixed_Col);
 
    // Declare Internal logic
    logic [31:0] 	w0, w1, w2, w3;
    logic [31:0] 	ws0, ws1, ws2, ws3;
    
-   // Break up input data into word components
+   // Break up input Data into word components
-   assign w0 = data[127:96];
+   assign w0 = Data[127:96];
-   assign w1 = data[95:64];
+   assign w1 = Data[95:64];
-   assign w2 = data[63:32];
+   assign w2 = Data[63:32];
-   assign w3 = data[31:0];
+   assign w3 = Data[31:0];
 
    // Declare mixword components
    inv_mixword mw_0(.word(w0), .mixed_word(ws0));
@@ -44,7 +44,7 @@ module aes_inv_mixcols (input  logic [127:0] data, output logic [127:0] mixed_co
    inv_mixword mw_3(.word(w3), .mixed_word(ws3));
 
    // Assign output to mixed word
-   assign mixed_col = {ws0, ws1, ws2, ws3};
+   assign Mixed_Col = {ws0, ws1, ws2, ws3};
 
 endmodule // inv_mixcols
 

src/ieu/aes_common/aes_inv_mixcolumns.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// aes_inv_mixcolumns.sv
+// aes_Inv_mixcolumns.sv
 //
 // Written: ryan.swann@okstate.edu, james.stine@okstate.edu
 // Created: 20 February 2024
@@ -43,28 +43,28 @@ module inv_mixword (input logic [31:0] word, output logic [31:0] mixed_word);
    assign b3 = word[7:0];
    
    // mb0 Galois components
-   gm9 gm9_0(.gm9_in(b1), .gm9_out(gm9_mb0));
+   gm9 gm9_0(.gm9_In(b1), .gm9_Out(gm9_mb0));
-   gm11 gm11_0(.gm11_in(b3), .gm11_out(gm11_mb0));
+   gm11 gm11_0(.gm11_In(b3), .gm11_Out(gm11_mb0));
-   gm13 gm13_0(.gm13_in(b2), .gm13_out(gm13_mb0));
+   gm13 gm13_0(.gm13_In(b2), .gm13_Out(gm13_mb0));
-   gm14 gm14_0(.gm14_in(b0), .gm14_out(gm14_mb0));
+   gm14 gm14_0(.gm14_In(b0), .gm14_Out(gm14_mb0));
 
    // mb1 Galois components                	
-   gm9 gm9_1(.gm9_in(b2), .gm9_out(gm9_mb1));  
+   gm9 gm9_1(.gm9_In(b2), .gm9_Out(gm9_mb1));  
-   gm11 gm11_1(.gm11_in(b0), .gm11_out(gm11_mb1));
+   gm11 gm11_1(.gm11_In(b0), .gm11_Out(gm11_mb1));
-   gm13 gm13_1(.gm13_in(b3), .gm13_out(gm13_mb1));
+   gm13 gm13_1(.gm13_In(b3), .gm13_Out(gm13_mb1));
-   gm14 gm14_1(.gm14_in(b1), .gm14_out(gm14_mb1));
+   gm14 gm14_1(.gm14_In(b1), .gm14_Out(gm14_mb1));
    
    // mb2 Galois components
-   gm9 gm9_2(.gm9_in(b3), .gm9_out(gm9_mb2));
+   gm9 gm9_2(.gm9_In(b3), .gm9_Out(gm9_mb2));
-   gm11 gm11_2(.gm11_in(b1), .gm11_out(gm11_mb2));
+   gm11 gm11_2(.gm11_In(b1), .gm11_Out(gm11_mb2));
-   gm13 gm13_2(.gm13_in(b0), .gm13_out(gm13_mb2));
+   gm13 gm13_2(.gm13_In(b0), .gm13_Out(gm13_mb2));
-   gm14 gm14_2(.gm14_in(b2), .gm14_out(gm14_mb2));   
+   gm14 gm14_2(.gm14_In(b2), .gm14_Out(gm14_mb2));   
                                            
    // mb3 Galois components
-   gm9 gm9_3(.gm9_in(b0), .gm9_out(gm9_mb3));
+   gm9 gm9_3(.gm9_In(b0), .gm9_Out(gm9_mb3));
-   gm11 gm11_3(.gm11_in(b2), .gm11_out(gm11_mb3));
+   gm11 gm11_3(.gm11_In(b2), .gm11_Out(gm11_mb3));
-   gm13 gm13_3(.gm13_in(b1), .gm13_out(gm13_mb3));
+   gm13 gm13_3(.gm13_In(b1), .gm13_Out(gm13_mb3));
-   gm14 gm14_3(.gm14_in(b3), .gm14_out(gm14_mb3));
+   gm14 gm14_3(.gm14_In(b3), .gm14_Out(gm14_mb3));
 
    // XOR Galois components and assign output
    assign mb0 = gm9_mb0 ^ gm11_mb0 ^ gm13_mb0 ^ gm14_mb0;

src/ieu/aes_common/aes_inv_sbox.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// aes_inv_sbox.sv
+// aes_Inv_sbox.sv
 //
 // Written: ryan.swann@okstate.edu, james.stine@okstate.edu
 // Created: 20 February 2024
@@ -25,7 +25,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aes_inv_sbox(input logic [7:0] in,
+module aes_Inv_sbox(input logic [7:0] in,
 		    output logic [7:0] out);
 
    always_comb

src/ieu/aes_common/aes_inv_sbox_128.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// aes_inv_sbox_128.sv
+// aes_Inv_sbox_128.sv
 //
 // Written: ryan.swann@okstate.edu, james.stine@okstate.edu
 // Created: 20 February 2024
@@ -25,16 +25,16 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aes_inv_sbox_128(input logic [127:0] in,
+module aes_Inv_sbox_128(input logic [127:0] in,
 			output logic [127:0] out);
 
    // Declare the SBOX for (least significant) word 0 of the input
-   aes_inv_sbox_word sbox_w0(.in(in[31:0]), .out(out[31:0]));
+   aes_Inv_sbox_word sbox_w0(.in(in[31:0]), .out(out[31:0]));
    // Declare the SBOX for word 1 of the input
-   aes_inv_sbox_word sbox_w1(.in(in[63:32]), .out(out[63:32]));
+   aes_Inv_sbox_word sbox_w1(.in(in[63:32]), .out(out[63:32]));
    // Declare the SBOX for word 2 of the input
-   aes_inv_sbox_word sbox_w2(.in(in[95:64]), .out(out[95:64]));	
+   aes_Inv_sbox_word sbox_w2(.in(in[95:64]), .out(out[95:64]));	
    // Declare the SBOX for word 3 of the input	
-   aes_inv_sbox_word sbox_w3(.in(in[127:96]), .out(out[127:96]));
+   aes_Inv_sbox_word sbox_w3(.in(in[127:96]), .out(out[127:96]));
 				 
 endmodule

src/ieu/aes_common/aes_inv_sbox_word.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// aes_inv_sbox_word.sv
+// aes_Inv_sbox_word.sv
 //
 // Written: ryan.swann@okstate.edu, james.stine@okstate.edu
 // Created: 20 February 2024
@@ -25,16 +25,16 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aes_inv_sbox_word(input logic [31:0] in,
+module aes_Inv_sbox_word(input logic [31:0] in,
 			 output logic [31:0] out);
    
    // Declare the SBOX for (least significant) byte 0 of the input
-   aes_inv_sbox sbox_b0(.in(in[7:0]), .out(out[7:0]));
+   aes_Inv_sbox sbox_b0(.in(in[7:0]), .out(out[7:0]));
    // Declare the SBOX for byte 1 of the input
-   aes_inv_sbox sbox_b1(.in(in[15:8]), .out(out[15:8]));
+   aes_Inv_sbox sbox_b1(.in(in[15:8]), .out(out[15:8]));
    // Declare the SBOX for byte 2 of the input
-   aes_inv_sbox sbox_b2(.in(in[23:16]), .out(out[23:16]));	
+   aes_Inv_sbox sbox_b2(.in(in[23:16]), .out(out[23:16]));	
    // Declare the SBOX for byte 3 of the input	
-   aes_inv_sbox sbox_b3(.in(in[31:24]), .out(out[31:24]));
+   aes_Inv_sbox sbox_b3(.in(in[31:24]), .out(out[31:24]));
    
 endmodule

src/ieu/aes_common/aes_inv_shiftrow.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// aes_inv_shiftrow.sv
+// aes_Inv_shiftrow.sv
 //
 // Written: ryan.swann@okstate.edu, james.stine@okstate.edu
 // Created: 20 February 2024
@@ -25,35 +25,35 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aes_inv_shiftrow(input logic [127:0] dataIn,
+module aes_Inv_shiftrow(input logic [127:0] DataIn,
-			output logic [127:0] dataOut);
+			output logic [127:0] DataOut);
 		    
    // Separate the first (Least Significant) word into bytes
-   logic [7:0] 				     w0_b0 = dataIn[7:0];		
+   logic [7:0] 				     w0_b0 = DataIn[7:0];		
-   logic [7:0] 				     w0_b1 = dataIn[15:8];	
+   logic [7:0] 				     w0_b1 = DataIn[15:8];	
-   logic [7:0] 				     w0_b2 = dataIn[23:16];	
+   logic [7:0] 				     w0_b2 = DataIn[23:16];	
-   logic [7:0] 				     w0_b3 = dataIn[31:24];	
+   logic [7:0] 				     w0_b3 = DataIn[31:24];	
    // Separate the second word into bytes
-   logic [7:0] 				     w1_b0 = dataIn[39:32];	
+   logic [7:0] 				     w1_b0 = DataIn[39:32];	
-   logic [7:0] 				     w1_b1 = dataIn[47:40];	
+   logic [7:0] 				     w1_b1 = DataIn[47:40];	
-   logic [7:0] 				     w1_b2 = dataIn[55:48];	
+   logic [7:0] 				     w1_b2 = DataIn[55:48];	
-   logic [7:0] 				     w1_b3 = dataIn[63:56];	
+   logic [7:0] 				     w1_b3 = DataIn[63:56];	
    // Separate the third word into bytes
-   logic [7:0] 				     w2_b0 = dataIn[71:64];	
+   logic [7:0] 				     w2_b0 = DataIn[71:64];	
-   logic [7:0] 				     w2_b1 = dataIn[79:72];	
+   logic [7:0] 				     w2_b1 = DataIn[79:72];	
-   logic [7:0] 				     w2_b2 = dataIn[87:80];	
+   logic [7:0] 				     w2_b2 = DataIn[87:80];	
-   logic [7:0] 				     w2_b3 = dataIn[95:88];	
+   logic [7:0] 				     w2_b3 = DataIn[95:88];	
    // Separate the fourth (Most significant) word into bytes
-   logic [7:0] 				     w3_b0 = dataIn[103:96];	
+   logic [7:0] 				     w3_b0 = DataIn[103:96];	
-   logic [7:0] 				     w3_b1 = dataIn[111:104];	
+   logic [7:0] 				     w3_b1 = DataIn[111:104];	
-   logic [7:0] 				     w3_b2 = dataIn[119:112];	
+   logic [7:0] 				     w3_b2 = DataIn[119:112];	
-   logic [7:0] 				     w3_b3 = dataIn[127:120];    
+   logic [7:0] 				     w3_b3 = DataIn[127:120];    
    // The output words are composed of sets of the input bytes.
    logic [31:0] 			     out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0};
    logic [31:0] 			     out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0};
    logic [31:0] 			     out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0};
    logic [31:0] 			     out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0};   
    
-   assign dataOut = {out_w0, out_w1, out_w2, out_w3};
+   assign DataOut = {out_w0, out_w1, out_w2, out_w3};
    
 endmodule

src/ieu/aes_common/aes_mixcolumns.sv

@@ -38,21 +38,21 @@
  * Reference: secworks repo
  */
 
-module aes_mixcolumns(data, mixedcols);
+module aes_mixcolumns(Data, mixedcols);
 
    // Declare Inputs/Outputs
-   input  logic [127:0] data;
+   input  logic [127:0] Data;
    output logic [127:0] mixedcols;
    
    // Declare internal Logic
    logic [31:0] 	w0, w1, w2, w3;
    logic [31:0] 	ws0, ws1, ws2, ws3;
    
-   // Break up data into individual words
+   // Break up Data into individual words
-   assign w0 = data[127:96];
+   assign w0 = Data[127:96];
-   assign w1 = data[95:64];
+   assign w1 = Data[95:64];
-   assign w2 = data[63:32];
+   assign w2 = Data[63:32];
-   assign w3 = data[31:0];
+   assign w3 = Data[31:0];
    
    // Instantiate The mix words components for the words
    mixword mw0(.word(w0), .mixed_word(ws0));

src/ieu/aes_common/aes_shiftrow.sv

@@ -4,7 +4,7 @@
 // Written: ryan.swann@okstate.edu, james.stine@okstate.edu
 // Created: 20 February 2024
 //
-// Purpose: aes_shiftrow for taking in first data line
+// Purpose: aes_shiftrow for taking in first Data line
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -25,38 +25,38 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aes_shiftrow(input logic [127:0] dataIn,
+module aes_shiftrow(input logic [127:0] DataIn,
-		    output logic [127:0] dataOut);
+		    output logic [127:0] DataOut);
 		    
    // (This form of writing it may seem like more effort but I feel
    // like it is more self-explanatory this way without losing efficiency)
    
    // Seperate the first (Least Significant) word into bytes
-   logic [7:0] 				 w0_b0 = dataIn[7:0];
+   logic [7:0] 				 w0_b0 = DataIn[7:0];
-   logic [7:0] 				 w0_b1 = dataIn[79:72];
+   logic [7:0] 				 w0_b1 = DataIn[79:72];
-   logic [7:0] 				 w0_b2 = dataIn[23:16];
+   logic [7:0] 				 w0_b2 = DataIn[23:16];
-   logic [7:0] 				 w0_b3 = dataIn[95:88];
+   logic [7:0] 				 w0_b3 = DataIn[95:88];
    // Seperate the second word into bytes
-   logic [7:0] 				 w1_b0 = dataIn[39:32];
+   logic [7:0] 				 w1_b0 = DataIn[39:32];
-   logic [7:0] 				 w1_b1 = dataIn[111:104];
+   logic [7:0] 				 w1_b1 = DataIn[111:104];
-   logic [7:0] 				 w1_b2 = dataIn[55:48];
+   logic [7:0] 				 w1_b2 = DataIn[55:48];
-   logic [7:0] 				 w1_b3 = dataIn[127:120];
+   logic [7:0] 				 w1_b3 = DataIn[127:120];
    // Seperate the third word into bytes
-   logic [7:0] 				 w2_b0 = dataIn[71:64];
+   logic [7:0] 				 w2_b0 = DataIn[71:64];
-   logic [7:0] 				 w2_b1 = dataIn[15:8];
+   logic [7:0] 				 w2_b1 = DataIn[15:8];
-   logic [7:0] 				 w2_b2 = dataIn[87:80];
+   logic [7:0] 				 w2_b2 = DataIn[87:80];
-   logic [7:0] 				 w2_b3 = dataIn[31:24];
+   logic [7:0] 				 w2_b3 = DataIn[31:24];
    // Seperate the fourth (Most significant) word into bytes
-   logic [7:0] 				 w3_b0 = dataIn[103:96];
+   logic [7:0] 				 w3_b0 = DataIn[103:96];
-   logic [7:0] 				 w3_b1 = dataIn[47:40];
+   logic [7:0] 				 w3_b1 = DataIn[47:40];
-   logic [7:0] 				 w3_b2 = dataIn[119:112];
+   logic [7:0] 				 w3_b2 = DataIn[119:112];
-   logic [7:0] 				 w3_b3 = dataIn[63:56];   
+   logic [7:0] 				 w3_b3 = DataIn[63:56];   
    // The output words are composed of sets of the input bytes.
    logic [31:0] 			 out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0};
    logic [31:0] 			 out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0};
    logic [31:0] 			 out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0};
    logic [31:0] 			 out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0};
    
-   assign dataOut = {out_w0, out_w1, out_w2, out_w3};
+   assign DataOut = {out_w0, out_w1, out_w2, out_w3};
    
 endmodule

src/ieu/aes_common/aes_shiftword.sv

@@ -33,26 +33,26 @@
  input selection.
  */
 
-module aes_shiftword(input logic[1:0] shiftAmt, input logic [31:0]  dataIn,
+module aes_shiftword(input logic[1:0] shiftAmt, input logic [31:0]  DataIn,
-		     output logic [31:0] dataOut);
+		     output logic [31:0] DataOut);
    
    
-   logic [7:0] 				 b0 = dataIn[7:0];
+   logic [7:0] 				 b0 = DataIn[7:0];
-   logic [7:0] 				 b1 = dataIn[15:8];
+   logic [7:0] 				 b1 = DataIn[15:8];
-   logic [7:0] 				 b2 = dataIn[23:16];
+   logic [7:0] 				 b2 = DataIn[23:16];
-   logic [7:0] 				 b3 = dataIn[31:24];
+   logic [7:0] 				 b3 = DataIn[31:24];
    
    always_comb
      begin
 	case(shiftAmt)	  
 	  // 00 : Barrel Shift no bytes
-	  2'b00 : dataOut = {b3, b2, b1, b0};
+	  2'b00 : DataOut = {b3, b2, b1, b0};
 	  // 01 : Barrel Shift one byte
-	  2'b01 : dataOut = {b0, b3, b2, b1};
+	  2'b01 : DataOut = {b0, b3, b2, b1};
 	  // 10 : Barrel Shift two bytes
-	  2'b10 : dataOut = {b1, b0, b3, b2};
+	  2'b10 : DataOut = {b1, b0, b3, b2};
 	  // 11 : Barrel Shift three bytes
-	  default : dataOut = {b2, b1, b0, b3};
+	  default : DataOut = {b2, b1, b0, b3};
 	endcase
      end 
    

src/ieu/aes_common/gm11.sv

@@ -25,20 +25,20 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module gm11 (gm11_in, gm11_out);
+module gm11 (gm11_In, gm11_Out);
    
-   input  logic [7:0] gm11_in;
+   input  logic [7:0] gm11_In;
-   output logic [7:0] gm11_out;
+   output logic [7:0] gm11_Out;
 
    // Internal Logic
-   logic [7:0] 	      gm8_0_out;
+   logic [7:0] 	      gm8_0_Out;
-   logic [7:0] 	      gm2_0_out;
+   logic [7:0] 	      gm2_0_Out;
 
    // Sub-Modules for sub-Galois operations
-   gm8 gm8_0 (.gm8_in(gm11_in), .gm8_out(gm8_0_out));
+   gm8 gm8_0 (.gm8_In(gm11_In), .gm8_Out(gm8_0_Out));
-   gm2 gm2_0 (.gm2_in(gm11_in), .gm2_out(gm2_0_out));
+   gm2 gm2_0 (.gm2_In(gm11_In), .gm2_Out(gm2_0_Out));
 
    // Set output to gm8(in) ^ gm2(in) ^ in
-   assign gm11_out = gm8_0_out ^ gm2_0_out ^ gm11_in;
+   assign gm11_Out = gm8_0_Out ^ gm2_0_Out ^ gm11_In;
 
 endmodule 

src/ieu/aes_common/gm13.sv

@@ -25,20 +25,20 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module gm13 (gm13_in, gm13_out);
+module gm13 (gm13_In, gm13_Out);
 
-   input logic [7:0] gm13_in;
+   input logic [7:0] gm13_In;
-   output logic [7:0] gm13_out;
+   output logic [7:0] gm13_Out;
 
    // Internal Logic
-   logic [7:0] 	      gm8_0_out;
+   logic [7:0] 	      gm8_0_Out;
-   logic [7:0] 	      gm4_0_out;
+   logic [7:0] 	      gm4_0_Out;
 
    // Sub-Modules for sub-Galois operations
-   gm8 gm8_0 (.gm8_in(gm13_in), .gm8_out(gm8_0_out));
+   gm8 gm8_0 (.gm8_In(gm13_In), .gm8_Out(gm8_0_Out));
-   gm4 gm4_0 (.gm4_in(gm13_in), .gm4_out(gm4_0_out));
+   gm4 gm4_0 (.gm4_In(gm13_In), .gm4_Out(gm4_0_Out));
 
    // Set output to gm8(in) ^ gm4(in) ^ in
-   assign gm13_out = gm8_0_out ^ gm4_0_out ^ gm13_in;
+   assign gm13_Out = gm8_0_Out ^ gm4_0_Out ^ gm13_In;
 
 endmodule 

src/ieu/aes_common/gm14.sv

@@ -25,23 +25,23 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module gm14 (gm14_in, gm14_out);
+module gm14 (gm14_In, gm14_Out);
 
-   input  logic [7:0] gm14_in;
+   input  logic [7:0] gm14_In;
-   output logic [7:0] gm14_out;
+   output logic [7:0] gm14_Out;
 
    // Internal Logic
-   logic [7:0] 	      gm8_0_out;
+   logic [7:0] 	      gm8_0_Out;
-   logic [7:0] 	      gm4_0_out;
+   logic [7:0] 	      gm4_0_Out;
-   logic [7:0] 	      gm2_0_out;
+   logic [7:0] 	      gm2_0_Out;
 
    // Sub-Modules for sub-Galois operations
-   gm8 gm8_0 (.gm8_in(gm14_in), .gm8_out(gm8_0_out));
+   gm8 gm8_0 (.gm8_In(gm14_In), .gm8_Out(gm8_0_Out));
-   gm4 gm4_0 (.gm4_in(gm14_in), .gm4_out(gm4_0_out));
+   gm4 gm4_0 (.gm4_In(gm14_In), .gm4_Out(gm4_0_Out));
-   gm2 gm2_0 (.gm2_in(gm14_in), .gm2_out(gm2_0_out));
+   gm2 gm2_0 (.gm2_In(gm14_In), .gm2_Out(gm2_0_Out));
 
    //Assign output to gm8(in) ^ gm4(in) ^ gm2(in)
-   assign gm14_out = gm8_0_out ^ gm4_0_out ^ gm2_0_out;
+   assign gm14_Out = gm8_0_Out ^ gm4_0_Out ^ gm2_0_Out;
 
 endmodule 
 

src/ieu/aes_common/gm2.sv

@@ -25,12 +25,12 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module gm2 (gm2_in, gm2_out); 
+module gm2 (gm2_In, gm2_Out); 
    
-   input logic [7:0]  gm2_in;
+   input logic [7:0]  gm2_In;
-   output logic [7:0] gm2_out;
+   output logic [7:0] gm2_Out;
    
    // Set output to Galois Mult 2
-   assign gm2_out = {gm2_in[6:0], 1'b0} ^ (8'h1b & {8{gm2_in[7]}});
+   assign gm2_Out = {gm2_In[6:0], 1'b0} ^ (8'h1b & {8{gm2_In[7]}});
    
 endmodule 

src/ieu/aes_common/gm3.sv

@@ -25,18 +25,18 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module gm3 (gm3_in, gm3_out);
+module gm3 (gm3_In, gm3_Out);
    
-   input logic [7:0] gm3_in;
+   input logic [7:0] gm3_In;
-   output logic [7:0] gm3_out;
+   output logic [7:0] gm3_Out;
    
    // Internal Logic
-   logic [7:0] 	      gm2_0_out;
+   logic [7:0] 	      gm2_0_Out;
    
    // Sub-Modules for gm2 multiplication
-   gm2 gm2_0 (.gm2_in(gm3_in), .gm2_out(gm2_0_out));
+   gm2 gm2_0 (.gm2_In(gm3_In), .gm2_Out(gm2_0_Out));
    
    // Assign Output
-   assign gm3_out = gm2_0_out ^ gm3_in;
+   assign gm3_Out = gm2_0_Out ^ gm3_In;
    
 endmodule 

src/ieu/aes_common/gm4.sv

@@ -25,20 +25,20 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module gm4 (gm4_in, gm4_out); 
+module gm4 (gm4_In, gm4_Out); 
 
-   input logic [7:0] gm4_in;
+   input logic [7:0] gm4_In;
-   output logic [7:0] gm4_out;
+   output logic [7:0] gm4_Out;
 
    // Internal Logic
-   logic [7:0] 	      gm2_0_out;
+   logic [7:0] 	      gm2_0_Out;
-   logic [7:0] 	      gm2_1_out;
+   logic [7:0] 	      gm2_1_Out;
 
    // Sub-Modules for multiple gm2 multiplications
-   gm2 gm2_0 (.gm2_in(gm4_in), .gm2_out(gm2_0_out));
+   gm2 gm2_0 (.gm2_In(gm4_In), .gm2_Out(gm2_0_Out));
-   gm2 gm2_1 (.gm2_in(gm2_0_out), .gm2_out(gm2_1_out));
+   gm2 gm2_1 (.gm2_In(gm2_0_Out), .gm2_Out(gm2_1_Out));
 
    // Assign output to second gm2 output
-   assign gm4_out = gm2_1_out;
+   assign gm4_Out = gm2_1_Out;
 
 endmodule

src/ieu/aes_common/gm8.sv

@@ -25,20 +25,20 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module gm8 (gm8_in, gm8_out);
+module gm8 (gm8_In, gm8_Out);
    
-   input  logic [7:0] gm8_in;
+   input  logic [7:0] gm8_In;
-   output logic [7:0] gm8_out;
+   output logic [7:0] gm8_Out;
 
    // Internal Logic
-   logic [7:0] 	      gm2_0_out;
+   logic [7:0] 	      gm2_0_Out;
-   logic [7:0] 	      gm4_0_out;
+   logic [7:0] 	      gm4_0_Out;
 
    // Sub-Modules for sub-Galois operations
-   gm4 gm4_0 (.gm4_in(gm8_in), .gm4_out(gm4_0_out));
+   gm4 gm4_0 (.gm4_In(gm8_In), .gm4_Out(gm4_0_Out));
-   gm2 gm2_0 (.gm2_in(gm4_0_out), .gm2_out(gm2_0_out));
+   gm2 gm2_0 (.gm2_In(gm4_0_Out), .gm2_Out(gm2_0_Out));
 
    // Assign output to gm2 output
-   assign gm8_out = gm2_0_out;
+   assign gm8_Out = gm2_0_Out;
 
 endmodule 

src/ieu/aes_common/gm9.sv

@@ -25,18 +25,18 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module gm9 (gm9_in, gm9_out);
+module gm9 (gm9_In, gm9_Out);
    
-   input  logic [7:0] gm9_in;
+   input  logic [7:0] gm9_In;
-   output logic [7:0] gm9_out;
+   output logic [7:0] gm9_Out;
 
    // Internal Logic
-   logic [7:0] 	      gm8_0_out;
+   logic [7:0] 	      gm8_0_Out;
 
    // Sub-Modules for sub-Galois operations
-   gm8 gm8_0 (.gm8_in(gm9_in), .gm8_out(gm8_0_out));
+   gm8 gm8_0 (.gm8_In(gm9_In), .gm8_Out(gm8_0_Out));
 
    // Set output to gm8(in) ^ in
-   assign gm9_out = gm8_0_out ^ gm9_in;
+   assign gm9_Out = gm8_0_Out ^ gm9_In;
 
 endmodule

src/ieu/aes_common/mixword.sv

@@ -34,14 +34,14 @@ module mixword (word, mixed_word);
    // Declare Internal Signals
    logic [7:0] 	       b0, b1, b2, b3;
    logic [7:0] 	       mb0, mb1, mb2, mb3;   
-   logic [7:0] 	       gm2_0_out;
+   logic [7:0] 	       gm2_0_Out;
-   logic [7:0] 	       gm3_0_out;   
+   logic [7:0] 	       gm3_0_Out;   
-   logic [7:0] 	       gm2_1_out;
+   logic [7:0] 	       gm2_1_Out;
-   logic [7:0] 	       gm3_1_out;   
+   logic [7:0] 	       gm3_1_Out;   
-   logic [7:0] 	       gm2_2_out;
+   logic [7:0] 	       gm2_2_Out;
-   logic [7:0] 	       gm3_2_out;   
+   logic [7:0] 	       gm3_2_Out;   
-   logic [7:0] 	       gm2_3_out;
+   logic [7:0] 	       gm2_3_Out;
-   logic [7:0] 	       gm3_3_out;   
+   logic [7:0] 	       gm3_3_Out;   
    
    // Break word into bytes
    assign b0 = word[31:24];
@@ -50,23 +50,23 @@ module mixword (word, mixed_word);
    assign b3 = word[7:0];
 
    // mb0 Galois components
-   gm2 gm2_0(.gm2_in(b0), .gm2_out(gm2_0_out));
+   gm2 gm2_0(.gm2_In(b0), .gm2_Out(gm2_0_Out));
-   gm3 gm3_0(.gm3_in(b3), .gm3_out(gm3_0_out));
+   gm3 gm3_0(.gm3_In(b3), .gm3_Out(gm3_0_Out));
    // mb1 Galois components
-   gm2 gm2_1(.gm2_in(b1), .gm2_out(gm2_1_out));
+   gm2 gm2_1(.gm2_In(b1), .gm2_Out(gm2_1_Out));
-   gm3 gm3_1(.gm3_in(b0), .gm3_out(gm3_1_out));
+   gm3 gm3_1(.gm3_In(b0), .gm3_Out(gm3_1_Out));
    // mb2 Galois components
-   gm2 gm2_2(.gm2_in(b2), .gm2_out(gm2_2_out));
+   gm2 gm2_2(.gm2_In(b2), .gm2_Out(gm2_2_Out));
-   gm3 gm3_2(.gm3_in(b1), .gm3_out(gm3_2_out));
+   gm3 gm3_2(.gm3_In(b1), .gm3_Out(gm3_2_Out));
    // mb3 Galois components
-   gm2 gm2_3(.gm2_in(b3), .gm2_out(gm2_3_out));
+   gm2 gm2_3(.gm2_In(b3), .gm2_Out(gm2_3_Out));
-   gm3 gm3_3(.gm3_in(b2), .gm3_out(gm3_3_out));
+   gm3 gm3_3(.gm3_In(b2), .gm3_Out(gm3_3_Out));
 
    // Combine Componenets into mixed word
-   assign mb0 = gm2_0_out ^ gm3_0_out ^ b1 ^ b2;
+   assign mb0 = gm2_0_Out ^ gm3_0_Out ^ b1 ^ b2;
-   assign mb1 = gm2_1_out ^ gm3_1_out ^ b2 ^ b3;
+   assign mb1 = gm2_1_Out ^ gm3_1_Out ^ b2 ^ b3;
-   assign mb2 = gm2_2_out ^ gm3_2_out ^ b0 ^ b3;
+   assign mb2 = gm2_2_Out ^ gm3_2_Out ^ b0 ^ b3;
-   assign mb3 = gm2_3_out ^ gm3_3_out ^ b0 ^ b1;
+   assign mb3 = gm2_3_Out ^ gm3_3_Out ^ b0 ^ b1;
    assign mixed_word = {mb0, mb1, mb2, mb3};
    
 endmodule

src/ieu/aes_common/rotateleft.sv

@@ -25,10 +25,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module rotate_left(input logic [31:0] input_data,
+module rotate_left(input logic [31:0] Input_Data,
 		   input logic [4:0]   shamt, 
-		   output logic [31:0] rot_data);  
+		   output logic [31:0] Rot_Data);  
    
-   assign rot_data = (input_data << shamt) | (input_data >> (32 - shamt)); 
+   assign Rot_Data = (Input_Data << shamt) | (Input_Data >> (32 - shamt)); 
    
 endmodule

src/ieu/aes_instructions/aes32dsi.sv

@@ -28,13 +28,13 @@
 module aes32dsi(input logic [1:0] bs,
                 input logic [31:0]  rs1,
                 input logic [31:0]  rs2,
-                output logic [31:0] data_out);
+                output logic [31:0] Data_Out);
 
    // Declare Intermediary logic
    logic [4:0] 			    shamt;
-   logic [31:0] 		    sbox_in_32;
+   logic [31:0] 		    Sbox_In_32;
-   logic [7:0] 			    sbox_in;
+   logic [7:0] 			    Sbox_In;
-   logic [7:0] 			    sbox_out;
+   logic [7:0] 			    Sbox_Out;
    logic [31:0] 		    so;
    logic [31:0] 		    so_rotate;   
    
@@ -42,18 +42,18 @@ module aes32dsi(input logic [1:0] bs,
    assign shamt = {bs, 3'b0};
    
    // Shift rs2 right by shamt and take the lower byte
-   assign sbox_in_32 = (rs2 >> shamt);
+   assign Sbox_In_32 = (rs2 >> shamt);
-   assign sbox_in = sbox_in_32[7:0];
+   assign Sbox_In = Sbox_In_32[7:0];
    
    // Apply inverse sbox to si
-   aes_inv_sbox inv_sbox(.in(sbox_in), .out(sbox_out));
+   aes_inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out));
    
    // Pad output of inverse substitution box
-   assign so = {24'h0, sbox_out};
+   assign so = {24'h0, Sbox_Out};
    
    // Rotate the substitution box output left by shamt (bs * 8)
    rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate));
    
    // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));"
-   assign data_out = rs1 ^ so_rotate;
+   assign Data_Out = rs1 ^ so_rotate;
 endmodule

src/ieu/aes_instructions/aes32dsmi.sv

@@ -28,13 +28,13 @@
 module aes32dsmi(input logic [1:0] bs,
                  input logic [31:0]  rs1,
                  input logic [31:0]  rs2,
-                 output logic [31:0] data_out);
+                 output logic [31:0] Data_Out);
 
    // Declare Intermediary logic
    logic [4:0] 			     shamt;
-   logic [31:0] 		     sbox_in_32;
+   logic [31:0] 		     Sbox_In_32;
-   logic [7:0] 			     sbox_in;
+   logic [7:0] 			     Sbox_In;
-   logic [7:0] 			     sbox_out;
+   logic [7:0] 			     Sbox_Out;
    logic [31:0] 		     so;
    logic [31:0] 		     mixed;
    logic [31:0] 		     mixed_rotate;   
@@ -43,14 +43,14 @@ module aes32dsmi(input logic [1:0] bs,
    assign shamt = {bs, 3'b0};
    
    // Shift rs2 right by shamt and take the lower byte
-   assign sbox_in_32 = (rs2 >> shamt);
+   assign Sbox_In_32 = (rs2 >> shamt);
-   assign sbox_in = sbox_in_32[7:0];
+   assign Sbox_In = Sbox_In_32[7:0];
    
    // Apply inverse sbox to si
-   aes_inv_sbox inv_sbox(.in(sbox_in), .out(sbox_out));
+   aes_inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out));
    
    // Pad output of inverse substitution box
-   assign so = {24'h0, sbox_out};
+   assign so = {24'h0, Sbox_Out};
    
    // Run so through the mixword AES function
    inv_mixword mix(.word(so), .mixed_word(mixed));
@@ -59,5 +59,5 @@ module aes32dsmi(input logic [1:0] bs,
    rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate));
    
    // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));"
-   assign data_out = rs1 ^ mixed_rotate;
+   assign Data_Out = rs1 ^ mixed_rotate;
 endmodule

src/ieu/aes_instructions/aes32esi.sv

@@ -28,13 +28,13 @@
 module aes32esi(input logic [1:0] bs,
                 input logic [31:0] rs1,
                 input logic [31:0] rs2,
-                output logic [31:0] data_out);                
+                output logic [31:0] Data_Out);                
                 
    // Declare Intermediary logic
    logic [4:0] 			    shamt;
-   logic [31:0] 		    sbox_in_32;
+   logic [31:0] 		    Sbox_In_32;
-   logic [7:0] 			    sbox_in;
+   logic [7:0] 			    Sbox_In;
-   logic [7:0] 			    sbox_out;
+   logic [7:0] 			    Sbox_Out;
    logic [31:0] 		    so;
    logic [31:0] 		    so_rotate;   
     
@@ -42,20 +42,20 @@ module aes32esi(input logic [1:0] bs,
    assign shamt = {bs, 3'b0};
    
    // Shift rs2 right by shamt to get sbox input
-   assign sbox_in_32 = (rs2 >> shamt);
+   assign Sbox_In_32 = (rs2 >> shamt);
    
    // Take the bottom byte as an input to the substitution box
-   assign sbox_in = sbox_in_32[7:0];
+   assign Sbox_In = Sbox_In_32[7:0];
    
    // Substitute
-   aes_sbox subbox(.in(sbox_in), .out(sbox_out));
+   aes_sbox subbox(.in(Sbox_In), .out(Sbox_Out));
    
    // Pad sbox output
-   assign so = {24'h0, sbox_out};
+   assign so = {24'h0, Sbox_Out};
    
    // Rotate so left by shamt
    rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate));
    
    // Set result X(rs1)[31..0] ^ rol32(so, unsigned(shamt));
-   assign data_out = rs1 ^ so_rotate;   
+   assign Data_Out = rs1 ^ so_rotate;   
 endmodule

src/ieu/aes_instructions/aes32esmi.sv

@@ -28,13 +28,13 @@
 module aes32esmi(input logic [1:0]   bs,
                  input logic [31:0]  rs1,
                  input logic [31:0]  rs2,
-                 output logic [31:0] data_out);                
+                 output logic [31:0] Data_Out);                
                 
    // Declare Intermediary logic
    logic [4:0] 			     shamt;
-   logic [31:0] 		     sbox_in_32;
+   logic [31:0] 		     Sbox_In_32;
-   logic [7:0] 			     sbox_in;
+   logic [7:0] 			     Sbox_In;
-   logic [7:0] 			     sbox_out;
+   logic [7:0] 			     Sbox_Out;
    logic [31:0] 		     so;
    logic [31:0] 		     mixed;
    logic [31:0] 		     mixed_rotate;  
@@ -43,16 +43,16 @@ module aes32esmi(input logic [1:0]   bs,
    assign shamt = {bs, 3'b0};
    
    // Shift rs2 right by shamt to get sbox input
-   assign sbox_in_32 = (rs2 >> shamt);
+   assign Sbox_In_32 = (rs2 >> shamt);
    
    // Take the bottom byte as an input to the substitution box
-   assign sbox_in = sbox_in_32[7:0];
+   assign Sbox_In = Sbox_In_32[7:0];
    
    // Substitute
-   aes_sbox sbox(.in(sbox_in), .out(sbox_out));
+   aes_sbox sbox(.in(Sbox_In), .out(Sbox_Out));
    
    // Pad sbox output
-   assign so = {24'h0, sbox_out};
+   assign so = {24'h0, Sbox_Out};
    
    // Mix Word using aes_mixword component
    mixword mwd(.word(so), .mixed_word(mixed));
@@ -61,5 +61,5 @@ module aes32esmi(input logic [1:0]   bs,
    rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate));
    
    // Set result X(rs1)[31..0] ^ rol32(mixed, unsigned(shamt));
-   assign data_out = rs1 ^ mixed_rotate;   
+   assign Data_Out = rs1 ^ mixed_rotate;   
 endmodule

src/ieu/aes_instructions/aes64ds.sv

@@ -27,20 +27,20 @@
 
 module aes64ds(input logic [63:0] rs1,
                input logic [63:0]  rs2,
-               output logic [63:0] data_out);
+               output logic [63:0] Data_Out);
    
    // Intermediary Logic
-   logic [127:0] 		   shiftRow_out;
+   logic [127:0] 		   ShiftRow_Out;
-   logic [31:0] 		   sbox_out_0;
+   logic [31:0] 		   Sbox_Out_0;
-   logic [31:0] 		   sbox_out_1;    
+   logic [31:0] 		   Sbox_Out_1;    
    
    // Apply inverse shiftrows to rs2 and rs1
-   aes_inv_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(shiftRow_out));
+   aes_inv_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(ShiftRow_Out));
    
    // Apply full word inverse substitution to lower 2 words of shiftrow out
-   aes_inv_sbox_word inv_sbox_0(.in(shiftRow_out[31:0]), .out(sbox_out_0));
+   aes_inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0));
-   aes_inv_sbox_word inv_sbox_1(.in(shiftRow_out[63:32]), .out(sbox_out_1));
+   aes_inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1));
    
    // Concatenate the two substitution outputs to get result
-   assign data_out = {sbox_out_1, sbox_out_0};   
+   assign Data_Out = {Sbox_Out_1, Sbox_Out_0};   
 endmodule

src/ieu/aes_instructions/aes64dsm.sv

@@ -27,26 +27,26 @@
 
 module aes64dsm(input logic [63:0] rs1,
                 input logic [63:0]  rs2,
-                output logic [63:0] data_out);
+                output logic [63:0] Data_Out);
    
    // Intermediary Logic
-   logic [127:0] 		    shiftRow_out;
+   logic [127:0] 		    ShiftRow_Out;
-   logic [31:0] 		    sbox_out_0;
+   logic [31:0] 		    Sbox_Out_0;
-   logic [31:0] 		    sbox_out_1;
+   logic [31:0] 		    Sbox_Out_1;
-   logic [31:0] 		    mixcol_out_0;
+   logic [31:0] 		    Mixcol_Out_0;
-   logic [31:0] 		    mixcol_out_1;    
+   logic [31:0] 		    Mixcol_Out_1;    
    
    // Apply inverse shiftrows to rs2 and rs1
-   aes_inv_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(shiftRow_out));
+   aes_inv_shiftrow srow(.dataIn({rs2, rs1}), .dataOut(ShiftRow_Out));
    
    // Apply full word inverse substitution to lower 2 words of shiftrow out
-   aes_inv_sbox_word inv_sbox_0(.in(shiftRow_out[31:0]), .out(sbox_out_0));
+   aes_inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0));
-   aes_inv_sbox_word inv_sbox_1(.in(shiftRow_out[63:32]), .out(sbox_out_1));
+   aes_inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1));
    
    // Apply inverse mixword to sbox outputs
-   inv_mixword inv_mw_0(.word(sbox_out_0), .mixed_word(mixcol_out_0));
+   inv_mixword inv_mw_0(.word(Sbox_Out_0), .mixed_word(Mixcol_Out_0));
-   inv_mixword inv_mw_1(.word(sbox_out_1), .mixed_word(mixcol_out_1));
+   inv_mixword inv_mw_1(.word(Sbox_Out_1), .mixed_word(Mixcol_Out_1));
    
    // Concatenate mixed words for output
-   assign data_out = {mixcol_out_1, mixcol_out_0};
+   assign Data_Out = {Mixcol_Out_1, Mixcol_Out_0};
 endmodule

src/ieu/aes_instructions/aes64es.sv

@@ -27,15 +27,15 @@
 
 module aes64es(input logic [63:0]  rs1,
                input logic [63:0]  rs2,
-               output logic [63:0] data_out);
+               output logic [63:0] Data_Out);
                 
    // Intermediary Signals
-   logic [127:0] 		   shiftRow_out;
+   logic [127:0] 		   ShiftRow_Out;
    
    // AES shiftrow unit
-   aes_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(shiftRow_out));
+   aes_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(ShiftRow_Out));
    
    // Apply substitution box to 2 lower words
-   aes_sbox_word sbox_0(.in(shiftRow_out[31:0]), .out(data_out[31:0]));
+   aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Data_Out[31:0]));
-   aes_sbox_word sbox_1(.in(shiftRow_out[63:32]), .out(data_out[63:32]));       
+   aes_sbox_word sbox_1(.in(ShiftRow_Out[63:32]), .out(Data_Out[63:32]));       
 endmodule

src/ieu/aes_instructions/aes64esm.sv

@@ -27,20 +27,20 @@
 
 module aes64esm(input logic [63:0]  rs1,
                 input logic [63:0]  rs2,
-                output logic [63:0] data_out);
+                output logic [63:0] Data_Out);
    
     // Intermediary Signals
-    logic [127:0] shiftRow_out;
+    logic [127:0] ShiftRow_Out;
-    logic [63:0] sbox_out;
+    logic [63:0] Sbox_Out;
                 
     // AES shiftrow unit
-    aes_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(shiftRow_out));
+    aes_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(ShiftRow_Out));
    
     // Apply substitution box to 2 lower words
-    aes_sbox_word sbox_0(.in(shiftRow_out[31:0]), .out(sbox_out[31:0]));
+    aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out[31:0]));
-    aes_sbox_word sbox_1(.in(shiftRow_out[63:32]), .out(sbox_out[63:32]));
+    aes_sbox_word sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out[63:32]));
    
     // Apply mix columns operations
-    mixword mw0(.word(sbox_out[31:0]), .mixed_word(data_out[31:0]));
+    mixword mw0(.word(Sbox_Out[31:0]), .mixed_word(Data_Out[31:0]));
-    mixword mw1(.word(sbox_out[63:32]), .mixed_word(data_out[63:32]));    
+    mixword mw1(.word(Sbox_Out[63:32]), .mixed_word(Data_Out[63:32]));    
 endmodule

src/ieu/aes_instructions/aes64im.sv

@@ -26,8 +26,8 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module aes64im(input logic [63:0] rs1,
-               output logic [63:0] data_out);
+               output logic [63:0] Data_Out);
 
-   inv_mixword inv_mw_0(.word(rs1[31:0]), .mixed_word(data_out[31:0]));
+   inv_mixword inv_mw_0(.word(rs1[31:0]), .mixed_word(Data_Out[31:0]));
-   inv_mixword inv_mw_1(.word(rs1[63:32]), .mixed_word(data_out[63:32]));
+   inv_mixword inv_mw_1(.word(rs1[63:32]), .mixed_word(Data_Out[63:32]));
 endmodule

src/ieu/aes_instructions/aes64ks1i.sv

@@ -35,7 +35,7 @@ module aes64ks1i(input logic [3:0] roundnum,
    logic 			     lastRoundFlag;
    logic [31:0] 		     rs1_rotate;
    logic [31:0] 		     tmp2;
-   logic [31:0] 		     sbox_out;
+   logic [31:0] 		     Sbox_Out;
    
    // Get rcon value from table
    rcon_lut_128 rc(.RD(roundnum), .rcon_out(rcon_preshift));    
@@ -48,9 +48,9 @@ module aes64ks1i(input logic [3:0] roundnum,
    // Assign tmp2 to a mux based on lastRoundFlag
    assign tmp2 = lastRoundFlag ? rs1[63:32] : rs1_rotate;    
    // Substitute bytes of value obtained for tmp2 using Rijndael sbox
-   aes_sbox_word sbox(.in(tmp2),.out(sbox_out));    
+   aes_sbox_word sbox(.in(tmp2),.out(Sbox_Out));    
-   assign rd[31:0] = sbox_out ^ rcon;
+   assign rd[31:0] = Sbox_Out ^ rcon;
-   assign rd[63:32] = sbox_out ^ rcon;
+   assign rd[63:32] = Sbox_Out ^ rcon;
    
    // There may be some errors with this instruction.
    // Regression tests are passed successfully, but

src/ieu/alu.sv

@@ -2,9 +2,8 @@
 // alu.sv
 //
 // Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu
-//          kelvin.tran@okstate.edu, james.stine@okstate.edu
 // Created: 9 January 2021
-// Modified: 3 March 2023, 22 February 2024
+// Modified: 3 March 2023
 //
 // Purpose: RISC-V Arithmetic/Logic Unit
 //
@@ -92,11 +91,10 @@ module alu import cvw::*; #(parameter cvw_t P) (
   else              assign PreALUResult = FullResult;
 
   // Bit manipulation muxing
-  if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED | 
+  if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED | P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED | P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED | P.ZKNH_SUPPORTED) begin : bitmanipalu
-      P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED | P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED | P.ZKNH_SUPPORTED) begin : bitmanipalu
     bitmanipalu #(P) balu(
       .A, .B, .W64, .BSelect, .ZBBSelect, .BMUActive,
-      .Funct3, .Funct7, .Rs2E, .LT, .LTU, .BALUControl, .PreALUResult, .FullResult,
+      .Funct3, .Funct7, .Rs2E, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult,
       .CondMaskB, .CondShiftA, .ALUResult);
   end else begin
     assign ALUResult = PreALUResult;

src/ieu/controller.sv

@@ -43,7 +43,7 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   output logic        StructuralStallD,        // Structural stalls detected by controller
   output logic        LoadStallD,              // Structural stalls for load, sent to performance counters
   output logic        StoreStallD,             // load after store hazard
-  output logic [4:0]  Rs1D, Rs2D,              // Register sources to read in Decode or Execute stage
+  output logic [4:0]  Rs1D, Rs2D, Rs2E,        // Register sources to read in Decode or Execute stage
   // Execute stage control signals             
   input  logic        StallE, FlushE,          // Stall, flush Execute stage
   input  logic [1:0]  FlagsE,                  // Comparison flags ({eq, lt})
@@ -55,6 +55,7 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   output logic [2:0]  ALUSelectE,              // ALU mux select signal
   output logic        MemReadE, CSRReadE,      // Instruction reads memory, reads a CSR (needed for Hazard unit)
   output logic [2:0]  Funct3E,                 // Instruction's funct3 field
+  output logic [6:0]  Funct7E,                 // Instruction's funct7 field
   output logic        IntDivE,                 // Integer divide
   output logic        MDUE,                    // MDU (multiply/divide) operatio
   output logic        W64E,                    // RV64 W-type operation
@@ -63,8 +64,8 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   output logic        BranchE,                 // Branch instruction
   output logic        SCE,                     // Store Conditional instruction
   output logic        BranchSignedE,           // Branch comparison operands are signed (if it's a branch)
-  output logic [1:0]  BSelectE,                // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction
+  output logic [3:0]  BSelectE,                // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction
-  output logic [2:0]  ZBBSelectE,              // ZBB mux select signal in Execute stage
+  output logic [3:0]  ZBBSelectE,              // ZBB mux select signal in Execute stage
   output logic [2:0]  BALUControlE,            // ALU Control signals for B instructions in Execute Stage
   output logic        BMUActiveE,              // Bit manipulation instruction being executed
   output logic [1:0]  CZeroE,                  // {czero.nez, czero.eqz} instructions active
@@ -95,7 +96,7 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   output logic [4:0]  RdW                      // Register destinations in Execute, Memory, or Writeback stage
 );
 
-  logic [4:0] Rs1E, Rs2E;                      // pipelined register sources
+  logic [4:0] Rs1E;                      // pipelined register sources
   logic [6:0] OpD;                             // Opcode in Decode stage
   logic [2:0] Funct3D;                         // Funct3 field in Decode stage
   logic [6:0] Funct7D;                         // Funct7 field in Decode stage
@@ -138,8 +139,8 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   logic        FenceD, FenceE;                 // Fence instruction
   logic        SFenceVmaD;                     // sfence.vma instruction
   logic        IntDivM;                        // Integer divide instruction
-  logic [1:0]  BSelectD;                       // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage
+  logic [3:0]  BSelectD;                       // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage
-  logic [2:0]  ZBBSelectD;                     // ZBB Mux Select Signal
+  logic [3:0]  ZBBSelectD;                     // ZBB Mux Select Signal
   logic [1:0]  CZeroD;
   logic        IFunctD, RFunctD, MFunctD;      // Detect I, R, and M-type RV32IM/Rv64IM instructions
   logic        LFunctD, SFunctD, BFunctD;      // Detect load, store, branch instructions
@@ -351,9 +352,9 @@ module controller import cvw::*;  #(parameter cvw_t P) (
     assign SubArithD = BaseSubArithD; // TRUE If B-type or R-type instruction involves inverted operand
 
     // tie off unused bit manipulation signals
-    assign BSelectE = 2'b00;
+    assign BSelectE = 4'b0000;
-    assign BSelectD = 2'b00;
+    assign BSelectD = 4'b0000;
-    assign ZBBSelectE = 3'b000;
+    assign ZBBSelectE = 4'b0000;
     assign BALUControlE = 3'b0;
     assign BMUActiveE = 1'b0;
   end
@@ -417,9 +418,9 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   flopenrc #(1)  controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
 
   // Execute stage pipeline control register and logic
-  flopenrc #(37) controlregE(clk, reset, FlushE, ~StallE,
+  flopenrc #(44) controlregE(clk, reset, FlushE, ~StallE,
-                           {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, IFUPrefetchD, LSUPrefetchD, CZeroD, InstrValidD},
+                           {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, Funct7D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, IFUPrefetchD, LSUPrefetchD, CZeroD, InstrValidD},
-                           {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, IFUPrefetchE, LSUPrefetchE, CZeroE, InstrValidE});
+                           {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, Funct7E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, IFUPrefetchE, LSUPrefetchE, CZeroE, InstrValidE});
   flopenrc #(5)  Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E);
   flopenrc #(5)  Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
   flopenrc #(5)  RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);