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	Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
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						commit
						e067e0896f
					
				@ -1661,6 +1661,7 @@ derive imperas rv64gc
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ICACHE_SUPPORTED    0
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					ICACHE_SUPPORTED    0
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DCACHE_SUPPORTED    0
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					DCACHE_SUPPORTED    0
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VIRTMEM_SUPPORTED   0
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					VIRTMEM_SUPPORTED   0
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					ZICCLSM_SUPPORTED   0
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ZAAMO_SUPPORTED     0
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					ZAAMO_SUPPORTED     0
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ZALRSC_SUPPORTED    0
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					ZALRSC_SUPPORTED    0
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ZICBOM_SUPPORTED    0
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					ZICBOM_SUPPORTED    0
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@ -1669,3 +1670,4 @@ SVPBMT_SUPPORTED    0
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SVNAPOT_SUPPORTED   0
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					SVNAPOT_SUPPORTED   0
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BOOTROM_BASE        64'h700012340010
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					BOOTROM_BASE        64'h700012340010
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BOOTROM_RANGE       64'h10
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					BOOTROM_RANGE       64'h10
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@ -66,6 +66,7 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
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    assert ((P.ZCF_SUPPORTED == 0) | ((P.F_SUPPORTED == 1) & (P.XLEN == 32))) else $fatal(1, "ZCF requires F and XLEN == 32");
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					    assert ((P.ZCF_SUPPORTED == 0) | ((P.F_SUPPORTED == 1) & (P.XLEN == 32))) else $fatal(1, "ZCF requires F and XLEN == 32");
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    assert ((P.ZCD_SUPPORTED == 0) | (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D");
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					    assert ((P.ZCD_SUPPORTED == 0) | (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D");
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    assert ((P.LLEN == P.XLEN) | (P.DCACHE_SUPPORTED & P.DTIM_SUPPORTED == 0)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache");
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					    assert ((P.LLEN == P.XLEN) | (P.DCACHE_SUPPORTED & P.DTIM_SUPPORTED == 0)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache");
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					    assert ((P.ZICCLSM_SUPPORTED == 0) | (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICCLSM requires DCACHE_SUPPORTED");
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  end
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					  end
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endmodule
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					endmodule
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