mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Increase ulimit for verilator
This commit is contained in:
parent
a13f18fa4d
commit
e0506c0481
@ -35,7 +35,7 @@ export RISCV_OBJCOPY=$(which riscv64-unknown-elf-objcopy) # Copy this as
|
|||||||
export SPIKE_PATH=$RISCV/bin # Change this for your path to riscv-isa-sim (spike)
|
export SPIKE_PATH=$RISCV/bin # Change this for your path to riscv-isa-sim (spike)
|
||||||
|
|
||||||
# Verilator needs a larger stack to simulate CORE-V Wally
|
# Verilator needs a larger stack to simulate CORE-V Wally
|
||||||
ulimit -c 234613
|
ulimit -c 300000
|
||||||
|
|
||||||
# Imperas OVPsim; put this in if you are using it
|
# Imperas OVPsim; put this in if you are using it
|
||||||
#export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH
|
#export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH
|
||||||
|
Loading…
Reference in New Issue
Block a user