Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fix extraneous page fault stall

Browse Source
This commit is contained in:
Thomas Fleming 2021-04-03 21:28:24 -04:00
parent 35ba6f741b
commit e04ad8f304
4 changed files with 23 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
wally-pipelined/src/ebu/ahblite.sv
View File

@ -136,13 +136,13 @@ module ahblite (
// stall signals // stall signals
// Note that we need to extend both stalls when MMUTRANSLATE goes to idle, // Note that we need to extend both stalls when MMUTRANSLATE goes to idle,
// since translation might not be complete. // since translation might not be complete.
assign #2 DataStall = ~TrapM && ((NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || assign #2 DataStall = ((NextBusState == MEMREAD) || (NextBusState == MEMWRITE) ||
(NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) || (NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) ||
(NextBusState == MMUTRANSLATE) || (BusState == MMUTRANSLATE)); (NextBusState == MMUTRANSLATE) || (MMUTranslate && ~MMUTranslationComplete)); // && ~TrapM
// *** Could get finer grained stalling if we distinguish between MMU // *** Could get finer grained stalling if we distinguish between MMU
// instruction address translation and data address translation // instruction address translation and data address translation
assign #1 InstrStall = ~TrapM && ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) || assign #1 InstrStall = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) ||
(NextBusState == MMUTRANSLATE) || (BusState == MMUTRANSLATE)); (NextBusState == MMUTRANSLATE) || (MMUTranslate && ~MMUTranslationComplete)); // && ~TrapM
// bus outputs // bus outputs
assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) ||

8
wally-pipelined/src/ebu/pagetablewalker.sv
View File

@ -195,6 +195,8 @@ module pagetablewalker (
assign ITLBWriteF = ~DTLBMissM; // Prefer data over instructions assign ITLBWriteF = ~DTLBMissM; // Prefer data over instructions
end end
FAULT: begin FAULT: begin
assign TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
assign MMUTranslationComplete = '1;
assign InstrPageFaultM = ~DTLBMissM; assign InstrPageFaultM = ~DTLBMissM;
assign LoadPageFaultM = DTLBMissM && ~MemStore; assign LoadPageFaultM = DTLBMissM && ~MemStore;
assign StorePageFaultM = DTLBMissM && MemStore; assign StorePageFaultM = DTLBMissM && MemStore;
@ -206,8 +208,6 @@ module pagetablewalker (
// Capture page table entry from ahblite // Capture page table entry from ahblite
flopenr #(32) ptereg(HCLK, ~HRESETn, MMUReady, MMUReadPTE, SavedPTE); flopenr #(32) ptereg(HCLK, ~HRESETn, MMUReady, MMUReadPTE, SavedPTE);
// *** Evil hack to get CurrentPTE a cycle early before it is saved.
// Todo: Is it evil?
mux2 #(32) ptemux(SavedPTE, MMUReadPTE, MMUReady, CurrentPTE); mux2 #(32) ptemux(SavedPTE, MMUReadPTE, MMUReady, CurrentPTE);
assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
@ -300,6 +300,8 @@ module pagetablewalker (
assign ITLBWriteF = ~DTLBMissM; // Prefer data over instructions assign ITLBWriteF = ~DTLBMissM; // Prefer data over instructions
end end
FAULT: begin FAULT: begin
assign TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
assign MMUTranslationComplete = '1;
assign InstrPageFaultM = ~DTLBMissM; assign InstrPageFaultM = ~DTLBMissM;
assign LoadPageFaultM = DTLBMissM && ~MemStore; assign LoadPageFaultM = DTLBMissM && ~MemStore;
assign StorePageFaultM = DTLBMissM && MemStore; assign StorePageFaultM = DTLBMissM && MemStore;
@ -309,8 +311,6 @@ module pagetablewalker (
// Capture page table entry from ahblite // Capture page table entry from ahblite
flopenr #(`XLEN) ptereg(HCLK, ~HRESETn, MMUReady, MMUReadPTE, SavedPTE); flopenr #(`XLEN) ptereg(HCLK, ~HRESETn, MMUReady, MMUReadPTE, SavedPTE);
// *** Evil hack to get CurrentPTE a cycle early before it is saved.
// Todo: Is it evil?
mux2 #(`XLEN) ptemux(SavedPTE, MMUReadPTE, MMUReady, CurrentPTE); mux2 #(`XLEN) ptemux(SavedPTE, MMUReadPTE, MMUReady, CurrentPTE);
assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];

12
wally-pipelined/src/mmu/tlb.sv
View File

@ -132,16 +132,7 @@ module tlb #(parameter ENTRY_BITS = 3) (
tlb_ram #(ENTRY_BITS) ram(.*); tlb_ram #(ENTRY_BITS) ram(.*);
tlb_cam #(ENTRY_BITS, `VPN_BITS) cam(.*); tlb_cam #(ENTRY_BITS, `VPN_BITS) cam(.*);
always_comb begin assign PhysicalAddressFull = (TLBHit) ? {PhysicalPageNumber, PageOffset} : '0;
assign PhysicalPageNumber = PageTableEntry[`PPN_BITS+9:10];
if (TLBHit) begin
assign PhysicalAddressFull = {PhysicalPageNumber, PageOffset};
end else begin
assign PhysicalAddressFull = '0; // *** Actual behavior; disabled until walker functioning
//assign PhysicalAddressFull = {2'b0, VirtualPageNumber, PageOffset} // *** pass through should be removed as soon as walker ready
end
end
generate generate
if (`XLEN == 32) begin if (`XLEN == 32) begin
@ -155,6 +146,7 @@ module tlb #(parameter ENTRY_BITS = 3) (
assign TLBMiss = ~TLBHit & ~TLBFlush & Translate & TLBAccess; assign TLBMiss = ~TLBHit & ~TLBFlush & Translate & TLBAccess;
endmodule endmodule
// *** use actual flop notation instead of initialbegin and alwaysff
module tlb_ram #(parameter ENTRY_BITS = 3) ( module tlb_ram #(parameter ENTRY_BITS = 3) (
input clk, reset, input clk, reset,
input [ENTRY_BITS-1:0] VPNIndex, // Index to read from input [ENTRY_BITS-1:0] VPNIndex, // Index to read from

22
wally-pipelined/src/wally/wallypipelinedhart.sv
View File

@ -65,7 +65,7 @@ module wallypipelinedhart (
logic [`XLEN-1:0] SrcAE, SrcBE; logic [`XLEN-1:0] SrcAE, SrcBE;
logic [`XLEN-1:0] SrcAM; logic [`XLEN-1:0] SrcAM;
logic [2:0] Funct3E; logic [2:0] Funct3E;
// logic [31:0] InstrF; // logic [31:0] InstrF;
logic [31:0] InstrD, InstrM; logic [31:0] InstrD, InstrM;
logic [`XLEN-1:0] PCE, PCM, PCLinkE, PCLinkW; logic [`XLEN-1:0] PCE, PCM, PCLinkE, PCLinkW;
logic [`XLEN-1:0] PCTargetE; logic [`XLEN-1:0] PCTargetE;
@ -84,7 +84,7 @@ module wallypipelinedhart (
logic PCSrcE; logic PCSrcE;
logic CSRWritePendingDEM; logic CSRWritePendingDEM;
logic LoadStallD, MulDivStallD, CSRRdStallD; logic LoadStallD, MulDivStallD, CSRRdStallD;
logic DivDoneW; logic DivDoneW;
logic [4:0] SetFflagsM; logic [4:0] SetFflagsM;
logic [2:0] FRM_REGW; logic [2:0] FRM_REGW;
logic FloatRegWriteW; logic FloatRegWriteW;
@ -132,15 +132,15 @@ module wallypipelinedhart (
.Funct7M(InstrM[31:25]), .Funct7M(InstrM[31:25]),
.*); .*);
pagetablewalker pagetablewalker(.*); // can send addresses to ahblite, send out pagetablestall pagetablewalker pagetablewalker(.*); // can send addresses to ahblite, send out pagetablestall
// *** can connect to hazard unit // *** can connect to hazard unit
// changing from this to the line above breaks the program. auipc at 104 fails; seems to be flushed. // changing from this to the line above breaks the program. auipc at 104 fails; seems to be flushed.
// Would need to insertinstruction as InstrD, not InstrF // Would need to insertinstruction as InstrD, not InstrF
/*ahblite ebu( /*ahblite ebu(
.InstrReadF(1'b0), .InstrReadF(1'b0),
.InstrRData(), // hook up InstrF later .InstrRData(), // hook up InstrF later
.MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]), .MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]),
.*); */ .*); */
muldiv mdu(.*); // multiply and divide unit muldiv mdu(.*); // multiply and divide unit