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fixed 32priv tests, now passing

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This commit is contained in:
Daniel Torres 2022-07-22 15:35:20 -07:00
parent d95b266d49
commit e02c67ed5e
5 changed files with 10 additions and 10 deletions
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12
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output
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@ -9,16 +9,16 @@
00000000 # stval of faulting instruction (0x0) 00000000 # stval of faulting instruction (0x0)
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000003 # scause from Breakpoint 00000003 # scause from Breakpoint
80000168 # stval of breakpoint instruction adress 8000015c # stval of breakpoint instruction adress
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000004 # scause from load address misaligned 00000004 # scause from load address misaligned
80000171 # stval of misaligned address 80000165 # stval of misaligned address
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000005 # scause from load access 00000005 # scause from load access
00000000 # stval of accessed adress (0x0) 00000000 # stval of accessed adress (0x0)
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000006 # scause from store misaligned 00000006 # scause from store misaligned
80000189 # stval of address with misaligned store instr 8000017d # stval of address with misaligned store instr
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000007 # scause from store access 00000007 # scause from store access
00000000 # stval of accessed address (0x0) 00000000 # stval of accessed address (0x0)
@ -57,16 +57,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl
00000000 # stval of faulting instruction (0x0) 00000000 # stval of faulting instruction (0x0)
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000003 # scause from Breakpoint 00000003 # scause from Breakpoint
80000168 # stval of breakpoint instruction adress 8000015c # stval of breakpoint instruction adress
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000004 # scause from load address misaligned 00000004 # scause from load address misaligned
80000171 # stval of misaligned address 80000165 # stval of misaligned address
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000005 # scause from load access 00000005 # scause from load access
00000000 # stval of accessed adress (0x0) 00000000 # stval of accessed adress (0x0)
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000006 # scause from store misaligned 00000006 # scause from store misaligned
80000189 # stval of address with misaligned store instr 8000017d # stval of address with misaligned store instr
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000007 # scause from store access 00000007 # scause from store access
00000000 # stval of accessed address (0x0) 00000000 # stval of accessed address (0x0)

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S
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@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-32.h" #include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I") RVTEST_ISA("RV32I")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",clint) #def NO_SAIL=True; RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S
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@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-32.h" #include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I") RVTEST_ISA("RV32I")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",trap-sret) RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap-sret)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S
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@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-32.h" #include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I") RVTEST_ISA("RV32I")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",trap-u) RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap-u)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S
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@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-32.h" #include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I") RVTEST_ISA("RV32I")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",wfi) RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",wfi)
INIT_TESTS INIT_TESTS