From e02c1008bc581684ef11902c1f3a54589f071bf8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 10 Jun 2024 07:55:35 -0700 Subject: [PATCH] postprocessor shift amount simplification --- src/fpu/postproc/divshiftcalc.sv | 4 ---- src/fpu/postproc/fmashiftcalc.sv | 4 ++-- src/fpu/postproc/postprocess.sv | 5 ++--- 3 files changed, 4 insertions(+), 9 deletions(-) diff --git a/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv index 0a222d724..d45afeea6 100644 --- a/src/fpu/postproc/divshiftcalc.sv +++ b/src/fpu/postproc/divshiftcalc.sv @@ -28,10 +28,8 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module divshiftcalc import cvw::*; #(parameter cvw_t P) ( - input logic [P.DIVb:0] DivUm, // divsqrt significand input logic [P.NE+1:0] DivUe, // divsqrt exponent output logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt, // divsqrt shift amount - output logic [P.NORMSHIFTSZ-1:0] DivShiftIn, // divsqrt shift input output logic DivResSubnorm, // is the divsqrt result subnormal output logic DivSubnormShiftPos // is the subnormal shift amount positive ); @@ -68,6 +66,4 @@ module divshiftcalc import cvw::*; #(parameter cvw_t P) ( assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[P.LOGNORMSHIFTSZ-1:0] : '0; assign DivShiftAmt = DivResSubnorm ? DivSubnormShiftAmt : NormShift; - // pre-shift the divider result for normalization - assign DivShiftIn = {{P.NF{1'b0}}, DivUm, {P.NORMSHIFTSZ-P.DIVb-1-P.NF{1'b0}}}; endmodule diff --git a/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv index 1d33f7337..cf334aa9b 100644 --- a/src/fpu/postproc/fmashiftcalc.sv +++ b/src/fpu/postproc/fmashiftcalc.sv @@ -53,6 +53,7 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) ( //convert the sum's exponent into the proper precision if (P.FPSIZES == 1) begin assign NormSumExp = PreNormSumExp; + assign BiasCorr = '0; end else if (P.FPSIZES == 2) begin assign BiasCorr = Fmt ? (P.NE+2)'(0) : (P.NE+2)'(P.BIAS1-P.BIAS); assign NormSumExp = PreNormSumExp+BiasCorr; @@ -129,6 +130,5 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) ( // set and calculate the shift input and amount // - shift once if killing a product and the result is subnormal - if (P.FPSIZES == 1) assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(P.FMALEN-1)-1:0]+($clog2(P.FMALEN-1))'(P.NF+3): FmaSCnt+1; - else assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(P.FMALEN-1)-1:0]+($clog2(P.FMALEN-1))'(P.NF+3)+BiasCorr[$clog2(P.FMALEN-1)-1:0]: FmaSCnt+1; + assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(P.FMALEN-1)-1:0]+($clog2(P.FMALEN-1))'(P.NF+3)+BiasCorr[$clog2(P.FMALEN-1)-1:0]: FmaSCnt+1; endmodule diff --git a/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv index 20968dad7..2db03cb16 100644 --- a/src/fpu/postproc/postprocess.sv +++ b/src/fpu/postproc/postprocess.sv @@ -91,7 +91,6 @@ module postprocess import cvw::*; #(parameter cvw_t P) ( logic [$clog2(P.FMALEN+1)-1:0] FmaShiftAmt; // normalization shift amount for fma // division signals logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt; // divsqrt shif amount - logic [P.NORMSHIFTSZ-1:0] DivShiftIn; // divsqrt shift input logic [P.NE+1:0] Ue; // divsqrt corrected exponent after corretion shift logic DivByZero; // divide by zero flag logic DivResSubnorm; // is the divsqrt result subnormal @@ -147,7 +146,7 @@ module postprocess import cvw::*; #(parameter cvw_t P) ( fmashiftcalc #(P) fmashiftcalc(.FmaSCnt, .Fmt, .NormSumExp, .FmaSe, .FmaSm, .FmaSZero, .FmaPreResultSubnorm, .FmaShiftAmt); - divshiftcalc #(P) divshiftcalc(.DivUe, .DivUm, .DivResSubnorm, .DivSubnormShiftPos, .DivShiftAmt, .DivShiftIn); + divshiftcalc #(P) divshiftcalc(.DivUe, .DivResSubnorm, .DivSubnormShiftPos, .DivShiftAmt); // select which unit's output to shift always_comb @@ -162,7 +161,7 @@ module postprocess import cvw::*; #(parameter cvw_t P) ( end 2'b01: begin //divsqrt ShiftAmt = DivShiftAmt; - ShiftIn = DivShiftIn; + ShiftIn = {{P.NF{1'b0}}, DivUm, {P.NORMSHIFTSZ-P.DIVb-1-P.NF{1'b0}}}; end default: begin ShiftAmt = {P.LOGNORMSHIFTSZ{1'bx}};