diff --git a/.gitmodules b/.gitmodules
index eed0bb58f..34a374174 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -25,9 +25,10 @@
 	sparseCheckout = true
 	path = addins/verilog-ethernet
 	url = https://github.com/rosethompson/verilog-ethernet.git
-[submodule "cvw-arch-verif"]
+[submodule "addins/cvw-arch-verif"]
 	path = addins/cvw-arch-verif
 	url = https://github.com/openhwgroup/cvw-arch-verif
+	ignore = dirty
 [submodule "addins/riscvISACOV"]
 	path = addins/riscvISACOV
 	url = https://github.com/riscv-verification/riscvISACOV.git
diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif
index 189974e49..6d658b7b4 160000
--- a/addins/cvw-arch-verif
+++ b/addins/cvw-arch-verif
@@ -1 +1 @@
-Subproject commit 189974e497d7b8d2c08bb1d151b1ccdeaf3a64c9
+Subproject commit 6d658b7b42c83fd584008d72964cc75d0876b769
diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index 7152865ac..3843c736e 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit 7152865aca51062c87ff2cbb014e199a24bdc874
+Subproject commit 3843c736e427a2b52a0d06e6220b073afa4be401