From e00d404154317f05575befd9ee434015d23c8c5c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Feb 2022 10:43:37 -0600 Subject: [PATCH] More cache cleanup. --- pipelined/src/cache/cache.sv | 10 +++--- pipelined/src/cache/cacheway.sv | 18 +++++----- .../src/cache/{sram1rw.sv => sram1p1rw.sv} | 36 ++++++------------- 3 files changed, 25 insertions(+), 39 deletions(-) rename pipelined/src/cache/{sram1rw.sv => sram1p1rw.sv} (65%) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 863919b55..11cc9e7c0 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -70,7 +70,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( logic [1:0] SelAdr; logic [SETLEN-1:0] RAdr; - logic [LINELEN-1:0] SRAMWriteData; + logic [LINELEN-1:0] CacheWriteData; logic SetValid, ClearValid; logic SetDirty, ClearDirty; logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0]; @@ -115,9 +115,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0]( .clk, .reset, .RAdr, .PAdr, - .WriteWordEn(WriteWordWayEn), - .WriteLineEn(WriteLineWayEn), - .WriteData(SRAMWriteData), + .WriteWordWayEn, + .WriteLineWayEn, + .CacheWriteData, .SetValid(SetValidWay), .ClearValid(ClearValidWay), .SetDirty(SetDirtyWay), .ClearDirty(ClearDirtyWay), .SelEvict, .Victim(VictimWay), .Flush(FlushWay), .SelFlush, @@ -150,7 +150,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( ///////////////////////////////////////////////////////////////////////////////////////////// mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}), - .d1(CacheMemWriteData), .s(FSMLineWriteEn), .y(SRAMWriteData)); + .d1(CacheMemWriteData), .s(FSMLineWriteEn), .y(CacheWriteData)); mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 73d40a3ac..d9956ca89 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -37,9 +37,9 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, input logic [$clog2(NUMLINES)-1:0] RAdr, input logic [`PA_BITS-1:0] PAdr, - input logic WriteWordEn, - input logic WriteLineEn, - input logic [LINELEN-1:0] WriteData, + input logic WriteWordWayEn, + input logic WriteLineWayEn, + input logic [LINELEN-1:0] CacheWriteData, input logic SetValid, input logic ClearValid, input logic SetDirty, @@ -82,15 +82,15 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, onehotdecoder #(LOGWPL) adrdec( .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded)); // If writing the whole line set all write enables to 1, else only set the correct word. - assign SelectedWriteWordEn = WriteLineEn ? '1 : WriteWordEn ? MemPAdrDecoded : '0; // OR-AND + assign SelectedWriteWordEn = WriteLineWayEn ? '1 : WriteWordWayEn ? MemPAdrDecoded : '0; // OR-AND ///////////////////////////////////////////////////////////////////////////////////////////// // Tag Array ///////////////////////////////////////////////////////////////////////////////////////////// - sram1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk(clk), - .Adr(RAdr), .ReadData(ReadTag), - .WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(WriteLineEn)); + sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, + .Adr(RAdr), .ReadData(ReadTag), + .CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(WriteLineWayEn)); // AND portion of distributed tag multiplexer assign SelTag = SelFlush ? Flush : Victim; @@ -104,9 +104,9 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, // *** Potential optimization: if byte write enables are available, could remove subwordwrites genvar words; for(words = 0; words < LINELEN/`XLEN; words++) begin: word - sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk(clk), .Adr(RAdr), + sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk, .Adr(RAdr), .ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ), - .WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]), + .CacheWriteData(CacheWriteData[(words+1)*`XLEN-1:words*`XLEN]), .WriteEnable(SelectedWriteWordEn[words])); end diff --git a/pipelined/src/cache/sram1rw.sv b/pipelined/src/cache/sram1p1rw.sv similarity index 65% rename from pipelined/src/cache/sram1rw.sv rename to pipelined/src/cache/sram1p1rw.sv index 41dcbee04..33f022a86 100644 --- a/pipelined/src/cache/sram1rw.sv +++ b/pipelined/src/cache/sram1p1rw.sv @@ -3,7 +3,7 @@ // // Written: ross1728@gmail.com May 3, 2021 // Basic sram with 1 read write port. -// When clk rises Addr and WriteData are sampled. +// When clk rises Addr and CacheWriteData are sampled. // Following the clk edge read data is output from the sampled Addr. // Write // @@ -33,39 +33,25 @@ // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words -module sram1rw #(parameter DEPTH=128, WIDTH=256) ( - input logic clk, - input logic [$clog2(DEPTH)-1:0] Adr, - input logic [WIDTH-1:0] WriteData, - input logic WriteEnable, - output logic [WIDTH-1:0] ReadData); +module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( + input logic clk, + input logic [$clog2(DEPTH)-1:0] Adr, + input logic [WIDTH-1:0] CacheWriteData, + input logic WriteEnable, + output logic [WIDTH-1:0] ReadData); - logic [WIDTH-1:0] StoredData[DEPTH-1:0]; - logic [$clog2(DEPTH)-1:0] AdrD; - logic [WIDTH-1:0] WriteDataD; - logic WriteEnableD; + logic [WIDTH-1:0] StoredData[DEPTH-1:0]; + logic [$clog2(DEPTH)-1:0] AdrD; + logic WriteEnableD; - //*** model as single port - // *** merge with simpleram always_ff @(posedge clk) begin AdrD <= Adr; - //WriteDataD <= WriteData; /// ****** this is not right. there should not need to be a delay. Implement alternative cache stall to avoid this. Eliminates a bunch of delay flops elsewhere - //WriteEnableD <= WriteEnable; - //if (WriteEnableD) begin - //StoredData[AddrD] <= #1 WriteDataD; - //end if (WriteEnable) begin - StoredData[Adr] <= #1 WriteData; + StoredData[Adr] <= #1 CacheWriteData; end end assign ReadData = StoredData[AdrD]; -/* - always_ff @(posedge clk) begin - ReadData <= RAM[Adr]; - if (WriteEnable) RAM[Adr] <= WriteData; - end - */ endmodule