diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv index dd291ecea..661d53cba 100755 --- a/pipelined/src/fpu/fctrl.sv +++ b/pipelined/src/fpu/fctrl.sv @@ -47,7 +47,7 @@ module fctrl ( output logic FRegWriteM, FRegWriteW, // FP register write enable output logic [2:0] FrmM, // FP rounding mode output logic [`FMTBITS-1:0] FmtE, FmtM, // FP format - output logic DivStartE, // Start division or squareroot + output logic FDivStartE, IDivStartE, // Start division or squareroot output logic XEnE, YEnE, ZEnE, output logic YEnForwardE, ZEnForwardE, output logic FWriteIntE, FCvtIntE, FWriteIntM, // Write to integer register @@ -62,7 +62,7 @@ module fctrl ( logic [`FCTRLW-1:0] ControlsD; logic IllegalFPUInstrD, IllegalFPUInstrE; logic FRegWriteD; // FP register write enable - logic FDivStartD, FDivStartE, IDivStartE; // integer register write enable + logic FDivStartD; // integer register write enable logic FWriteIntD; // integer register write enable logic FRegWriteE; // FP register write enable logic [2:0] OpCtrlD; // Select which opperation to do in each component @@ -266,10 +266,8 @@ module fctrl ( flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]}, {Adr1E, Adr2E, Adr3E}); flopenrc #(1) DEFDivStartReg(clk, reset, FlushE, ~StallE|FDivBusyE, FDivStartD, FDivStartE); - if (`M_SUPPORTED) begin - assign IDivStartE = MDUE & Funct3E[2]; - assign DivStartE = FDivStartE | IDivStartE; // integer or floating-point division - end else assign DivStartE = FDivStartE; + if (`M_SUPPORTED) assign IDivStartE = MDUE & Funct3E[2]; + else assign IDivStartE = 0; assign FCvtIntE = (FResSelE == 2'b01); diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index 14e7cfa99..e675d3574 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -40,7 +40,7 @@ module fdivsqrt( input logic XInfE, YInfE, input logic XZeroE, YZeroE, input logic XNaNE, YNaNE, - input logic DivStartE, + input logic FDivStartE, IDivStartE, input logic StallM, input logic StallE, input logic SqrtE, SqrtM, @@ -66,6 +66,7 @@ module fdivsqrt( logic SpecialCaseM; logic [`DIVBLEN:0] n, m; logic OTFCSwap, ALTB, BZero, As; + logic DivStartE; fdivsqrtpreproc fdivsqrtpreproc( .clk, .DivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), @@ -74,7 +75,7 @@ module fdivsqrt( .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E); fdivsqrtfsm fdivsqrtfsm( .clk, .reset, .FmtE, .XsE, .SqrtE, - .DivBusy, .DivStartE,.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, + .DivBusy, .FDivStartE, .IDivStartE, .DivStartE, .StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .MDUE, .n, .XInfE, .YInfE, .WZero, .SpecialCaseM); fdivsqrtiter fdivsqrtiter( diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 9222c0c4f..03f519049 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -37,7 +37,7 @@ module fdivsqrtfsm( input logic XInfE, YInfE, input logic XZeroE, YZeroE, input logic XNaNE, YNaNE, - input logic DivStartE, + input logic FDivStartE, IDivStartE, input logic XsE, input logic SqrtE, input logic StallE, @@ -45,6 +45,7 @@ module fdivsqrtfsm( input logic WZero, input logic MDUE, input logic [`DIVBLEN:0] n, + output logic DivStartE, output logic DivDone, output logic DivBusy, output logic SpecialCaseM @@ -57,6 +58,17 @@ module fdivsqrtfsm( logic [`DURLEN-1:0] cycles; logic SpecialCaseE; + // *** start logic is presently in fctl. Make it look more like integer division start logic + // DivStartE comes from fctrl, reflecitng the start of floating-point and possibly integer division + assign DivStartE = (FDivStartE | IDivStartE); // & (state == IDLE) & ~StallM; + //assign DivStartE = (FDivStartE | IDivStartE) & (state == IDLE) & ~StallM; + assign DivDone = (state == DONE) | (WZero & (state == BUSY)); + assign DivBusy = (state == BUSY & ~DivDone); + + // Divider control signals from MDU + //assign DivStartE = DivE & (state == IDLE) & ~StallM; + //assign DivBusyE = (state == BUSY) | DivStartE; + // terminate immediately on special cases assign SpecialCaseE = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE); flopenr #(1) SpecialCaseReg(clk, reset, ~StallM, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc @@ -120,8 +132,5 @@ module fdivsqrtfsm( end end - // *** start logic is presently in fctl. Make it look more like integer division start logic - assign DivDone = (state == DONE) | (WZero & (state == BUSY)); - assign DivBusy = (state == BUSY & ~DivDone); endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index dcc0db6d5..2f6dcce5a 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -67,7 +67,7 @@ module fpu ( logic FRegWriteW; // FP register write enable logic [2:0] FrmM; // FP rounding mode logic [`FMTBITS-1:0] FmtE, FmtM; // FP precision 0-single 1-double - logic DivStartE; // Start division or squareroot + logic FDivStartE, IDivStartE; // Start division or squareroot logic FWriteIntM; // Write to integer register logic [1:0] ForwardXE, ForwardYE, ForwardZE; // forwarding mux control signals logic [2:0] OpCtrlE, OpCtrlM; // Select which opperation to do in each component @@ -167,7 +167,7 @@ module fpu ( .Funct3E, .MDUE, .InstrD, .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE, .reset, .clk, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM, .YEnForwardE, .ZEnForwardE, - .DivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .IllegalFPUInstrM, .XEnE, .YEnE, .ZEnE, + .FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .IllegalFPUInstrM, .XEnE, .YEnE, .ZEnE, .FResSelE, .FResSelM, .FResSelW, .PostProcSelE, .PostProcSelM, .FCvtIntW, .Adr1E, .Adr2E, .Adr3E); // FP register file @@ -261,7 +261,7 @@ module fpu ( // - fsqrt // *** add other opperations fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]), - .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .DivStartE(DivStartE), .XsE, + .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E, .StallE, .StallM, .DivSM, .DivBusy(FDivBusyE), .QeM, //***change divbusyE to M signal .QmM, .DivDone(DivDoneM));