diff --git a/.gitignore b/.gitignore index 7f65a18a6..1b19857de 100644 --- a/.gitignore +++ b/.gitignore @@ -16,8 +16,8 @@ wlft* /imperas-riscv-tests/FunctionRadix.addr /imperas-riscv-tests/ProgramMap.txt /imperas-riscv-tests/logs -/wally-pipelined/busybear-testgen/gdbcombined.txt -/wally-pipelined/busybear-testgen/first10.txt +/wally-pipelined/linux-testgen/qemu_output.txt +/wally-pipelined/linux-testgen/qemu_in_gdb_format.txt *.o *.d testsBP/*/*/*.elf* diff --git a/wally-pipelined/linux-testgen/logAllBuildroot.sh b/wally-pipelined/linux-testgen/logAllBuildroot.sh index dfb5205a5..df8b506a8 100755 --- a/wally-pipelined/linux-testgen/logAllBuildroot.sh +++ b/wally-pipelined/linux-testgen/logAllBuildroot.sh @@ -2,25 +2,26 @@ # Uncomment this version for GDB/QEMU debugging # - Opens up GDB interactively # - Logs raw QEMU output to qemu_output.txt -#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2> /mnt/scratch/wally_linux_output/qemu_output.txt) & riscv64-unknown-elf-gdb +#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2> qemu_output.txt) & riscv64-unknown-elf-gdb # Uncomment this version to generate qemu_output.txt # - Uses GDB script # - Logs raw QEMU output to qemu_output.txt -#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2>/mnt/scratch/wally_linux_output/qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_qemulog +#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2>qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_qemulog_debug # Uncomment this version for parse_qemu.py debugging # - Uses qemu_output.txt # - Makes qemu_in_gdb_format.txt # - Logs parse_qemu.py's simulated gdb output to qemu_in_gdb_format.txt -#cat /mnt/scratch/wally_linux_output/qemu_output.txt | ./parse_qemu.py >/mnt/scratch/wally_linux_output/qemu_in_gdb_format.txt +#cat qemu_output.txt | ./parse_qemu.py >qemu_in_gdb_format.txt +#cat qemu_output.txt | ./parse_qemu.py | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/" # Uncomment this version for parse_gdb_output.py debugging # - Uses qemu_in_gdb_format.txt # - Logs info needed by buildroot testbench -cat /mnt/scratch/wally_linux_output/qemu_in_gdb_format.txt | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/" +#cat qemu_in_gdb_format.txt | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/" # =========== Just Do the Thing ========== -# Uncomment this version for the whole thing (if it works ha ha_ +# Uncomment this version for the whole thing # - Logs info needed by buildroot testbench -#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2>&1 >/dev/null | pv -l | ./parse_qemu.py | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/") & riscv64-unknown-elf-gdb -x gdbinit_qemulog +(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2>&1 >/dev/null | pv -l | ./parse_qemu.py | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/") & riscv64-unknown-elf-gdb -x gdbinit_qemulog diff --git a/wally-pipelined/linux-testgen/parse_gdb_output.py b/wally-pipelined/linux-testgen/parse_gdb_output.py index 5ae62b326..739a97e31 100755 --- a/wally-pipelined/linux-testgen/parse_gdb_output.py +++ b/wally-pipelined/linux-testgen/parse_gdb_output.py @@ -27,7 +27,7 @@ try: readType = '' lastReadType = '' readLoc = '' - instrStart = -1 + lineOffset = -1 lastRegs = '' curRegs = '' storeReg = '' @@ -40,10 +40,12 @@ try: for l in fileinput.input('-'): l = l.split("#")[0].rstrip() if l.startswith('=>'): + # Begin new instruction instrs += 1 storeAMO = '' if instrs % 10000 == 0: print(instrs) + # Instr in human assembly wPC.write('{} ***\n'.format(' '.join(l.split(':')[1].split()[0:2]))) if '\tld' in l or '\tlw' in l or '\tlh' in l or '\tlb' in l: currentRead = l.split()[-1].split(',')[0] @@ -53,7 +55,6 @@ try: readLoc = l.split()[-1].split(',')[1].split('(')[1][:-1] readType = l.split()[-2] if 'amo' in l: - #print(l) currentRead = l.split()[-1].split(',')[0] readOffset = "0" readLoc = l.split()[-1].split('(')[1][:-1] @@ -63,7 +64,6 @@ try: storeReg = l.split()[-1].split(',')[1] storeAMO = l.split()[-2] if '\tsd' in l or '\tsw' in l or '\tsh' in l or '\tsb' in l: - #print(l) s = l.split('#')[0].split()[-1] storeReg = s.split(',')[0] if len(s.split(',')) < 2: @@ -74,17 +74,19 @@ try: print(l) storeOffset = s.split(',')[1].split('(')[0] storeLoc = s.split(',')[1].split('(')[1][:-1] - instrStart = 0 - elif instrStart != -1: - instrStart += 1 - if instrStart == 1: + lineOffset = 0 + elif lineOffset != -1: + lineOffset += 1 + if lineOffset == 1: + # Instr in hex comes one line after the instruction wPC.write('{}\n'.format(l.split()[-1][2:])) - elif instrStart < 34: + # As well as instr address + wPC.write('{}\n'.format(l.split()[0][2:].strip(":"))) + elif lineOffset <= (1+32): + # Next 32 lines are the Register File if lastRead == l.split()[0]: readData = int(l.split()[1][2:], 16) readData <<= (8 * (lastReadLoc % 8)) - #if(lastReadLoc % 8 != 0 and ('lw' in lastReadType or 'lb' in lastReadType)): - # readData <<= 32 wMem.write('{:x}\n'.format(readData)) if readLoc == l.split()[0]: readLoc = l.split()[1][2:] @@ -92,16 +94,12 @@ try: storeReg = l.split()[1] if storeLoc == l.split()[0]: storeLoc = l.split()[1][2:] - if instrStart > 2: - #print(l) - #print(instrStart) + if lineOffset > (1+1): + # Start logging x1 onwards (we don't care about x0) curRegs += '{}\n'.format(l.split()[1][2:]) - elif instrStart < 35: - #print("----------") - #print(l.split()[1][2:]) - wPC.write('{}\n'.format(l.split()[1][2:])) - #print(l.split()[1][2:]) - if any([c == l.split()[0] for c in csrs]): + #elif "pc" in l: + # wPC.write('{}\n'.format(l.split()[1][2:])) + if any([csr == l.split()[0] for csr in csrs]): if l.split()[0] in curCSRs: if curCSRs[l.split()[0]] != l.split()[1]: if firstCSR: @@ -112,51 +110,53 @@ try: wCSRs.write('{}\n{}\n'.format(l.split()[0], l.split()[1][2:])) curCSRs[l.split()[0]] = l.split()[1] if '-----' in l: # end of each cycle - if curRegs != lastRegs: - if lastRegs == '': - wReg.write(curRegs) - else: - for i in range(32): - if curRegs.split('\n')[i] != lastRegs.split('\n')[i]: - wReg.write('{}\n'.format(i+1)) - wReg.write('{}\n'.format(curRegs.split('\n')[i])) - break - lastRegs = curRegs - if lastAMO != '': - if 'amoadd' in lastAMO: - lastStoreReg = hex(int(lastStoreReg[2:], 16) + readData)[2:] - elif 'amoand' in lastAMO: - lastStoreReg = hex(int(lastStoreReg[2:], 16) & readData)[2:] - elif 'amoor' in lastAMO: - lastStoreReg = hex(int(lastStoreReg[2:], 16) | readData)[2:] - elif 'amoswap' in lastAMO: - lastStoreReg = hex(int(lastStoreReg[2:], 16))[2:] - else: - print(lastAMO) - exit() - wMemW.write('{}\n'.format(lastStoreReg)) - wMemW.write('{:x}\n'.format(int(lastStoreLoc, 16))) - if storeReg != '' and storeOffset != '' and storeLoc != '' and storeAMO == '': - storeLocOffset = int(storeOffset,10) + int(storeLoc, 16) - #wMemW.write('{:x}\n'.format(int(storeReg, 16) << (8 * (storeLocOffset % 8)))) - wMemW.write('{}\n'.format(storeReg[2:])) - wMemW.write('{:x}\n'.format(storeLocOffset)) - if readOffset != '' and readLoc != '': - wMem.write('{:x}\n'.format(int(readOffset,10) + int(readLoc, 16))) - lastReadLoc = int(readOffset,10) + int(readLoc, 16) - lastReadType = readType - readOffset = '' - readLoc = '' - curRegs = '' - instrStart = -1 - lastRead = currentRead - currentRead = '' - lastStoreReg = storeReg - lastStoreLoc = storeLoc - storeReg = '' - storeOffset = '' - storeLoc = '' - lastAMO = storeAMO + if curRegs != lastRegs: + if lastRegs == '': + wReg.write(curRegs) + else: + for i in range(32): + if curRegs.split('\n')[i] != lastRegs.split('\n')[i]: + wReg.write('{}\n'.format(i+1)) + wReg.write('{}\n'.format(curRegs.split('\n')[i])) + break + lastRegs = curRegs + if lastAMO != '': + if 'amoadd' in lastAMO: + lastStoreReg = hex(int(lastStoreReg[2:], 16) + readData)[2:] + elif 'amoand' in lastAMO: + lastStoreReg = hex(int(lastStoreReg[2:], 16) & readData)[2:] + elif 'amoor' in lastAMO: + lastStoreReg = hex(int(lastStoreReg[2:], 16) | readData)[2:] + elif 'amoswap' in lastAMO: + lastStoreReg = hex(int(lastStoreReg[2:], 16))[2:] + else: + print(lastAMO) + exit() + #print('lastStoreReg {}\n'.format(lastStoreReg)) + #print('lastStoreLoc '+str(lastStoreLoc)) + wMemW.write('{}\n'.format(lastStoreReg)) + wMemW.write('{:x}\n'.format(int(lastStoreLoc, 16))) + if storeReg != '' and storeOffset != '' and storeLoc != '' and storeAMO == '': + storeLocOffset = int(storeOffset,10) + int(storeLoc, 16) + #wMemW.write('{:x}\n'.format(int(storeReg, 16) << (8 * (storeLocOffset % 8)))) + wMemW.write('{}\n'.format(storeReg[2:])) + wMemW.write('{:x}\n'.format(storeLocOffset)) + if readOffset != '' and readLoc != '': + wMem.write('{:x}\n'.format(int(readOffset,10) + int(readLoc, 16))) + lastReadLoc = int(readOffset,10) + int(readLoc, 16) + lastReadType = readType + readOffset = '' + readLoc = '' + curRegs = '' + lineOffset = -1 + lastRead = currentRead + currentRead = '' + lastStoreReg = storeReg + lastStoreLoc = storeLoc + storeReg = '' + storeOffset = '' + storeLoc = '' + lastAMO = storeAMO except (FileNotFoundError): diff --git a/wally-pipelined/linux-testgen/parse_qemu.py b/wally-pipelined/linux-testgen/parse_qemu.py index 91d45800c..c7f31fb22 100755 --- a/wally-pipelined/linux-testgen/parse_qemu.py +++ b/wally-pipelined/linux-testgen/parse_qemu.py @@ -39,12 +39,14 @@ def parseCSRs(l): csr = l.split()[0] val = int(l.split()[1],16) if inPageFault: - if l.startswith("mstatus") or l.startswith("mepc") or l.startswith("mcause") or l.startswith("mtval") or l.startswith("sepc") or l.startswith("scause") or l.startswith("stval"): - # We do update some CSRs - CSRs[csr] = val - else: - # Others we preserve until changed later - pageFaultCSRs[csr] = val + # Not sure if these CSRs should be updated or not during page fault. + #if l.startswith("mstatus") or l.startswith("mepc") or l.startswith("mcause") or l.startswith("mtval") or l.startswith("sepc") or l.startswith("scause") or l.startswith("stval"): + # # We do update some CSRs + # CSRs[csr] = val + #else: + # # Others we preserve until changed later + # pageFaultCSRs[csr] = val + pageFaultCSRs[csr] = val elif pageFaultCSRs and (csr in pageFaultCSRs): if (val != pageFaultCSRs[csr]): del pageFaultCSRs[csr] diff --git a/wally-pipelined/regression/wally-buildroot.do b/wally-pipelined/regression/wally-buildroot.do index c212831e8..21767385e 100644 --- a/wally-pipelined/regression/wally-buildroot.do +++ b/wally-pipelined/regression/wally-buildroot.do @@ -35,7 +35,7 @@ vopt +acc work.testbench -o workopt vsim workopt -suppress 8852,12070 -do ./wave-dos/busybear-waves.do +do ./wave-dos/linux-waves.do #-- Run the Simulation run -all diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index 3638a7755..11876dded 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -35,7 +35,7 @@ vopt +acc work.testbench -o workopt vsim workopt -suppress 8852,12070 -do ./wave-dos/bens-busybear-waves.do +do ./wave-dos/linux-waves.do #-- Run the Simulation diff --git a/wally-pipelined/regression/wave-dos/bens-busybear-waves.do b/wally-pipelined/regression/wave-dos/bens-busybear-waves.do deleted file mode 100644 index 0d672167c..000000000 --- a/wally-pipelined/regression/wave-dos/bens-busybear-waves.do +++ /dev/null @@ -1,64 +0,0 @@ -# busybear-waves.do -restart -f -delete wave /* -view wave - -add wave /testbench/dut/hart/DataStall -add wave /testbench/dut/hart/ICacheStallF -add wave /testbench/dut/hart/StallF -add wave /testbench/dut/hart/StallD -add wave /testbench/dut/hart/StallE -add wave /testbench/dut/hart/StallM -add wave /testbench/dut/hart/StallW -add wave /testbench/dut/hart/FlushD -add wave /testbench/dut/hart/FlushE -add wave /testbench/dut/hart/FlushM -add wave /testbench/dut/hart/FlushW -add wave -divider - -add wave /testbench/clk -add wave /testbench/reset -add wave -divider - -add wave -hex /testbench/dut/hart/ifu/PCF -add wave -hex /testbench/PCtext -add wave -hex /testbench/pcExpected -add wave -hex /testbench/dut/hart/ifu/PCD -add wave -hex /testbench/dut/hart/ifu/InstrD -add wave /testbench/InstrDName -add wave -divider -add wave -hex /testbench/dut/hart/ifu/PCE -add wave -hex /testbench/dut/hart/ifu/InstrE -add wave /testbench/InstrEName -add wave -hex /testbench/dut/hart/ieu/dp/SrcAE -add wave -hex /testbench/dut/hart/ieu/dp/SrcBE -add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE -#add wave /testbench/dut/hart/ieu/dp/PCSrcE -add wave -divider -add wave -hex /testbench/dut/hart/ifu/PCM -add wave -hex /testbench/dut/hart/ifu/InstrM -add wave /testbench/InstrMName -add wave /testbench/dut/uncore/dtim/memwrite -add wave -hex /testbench/dut/uncore/HADDR -add wave -hex /testbench/dut/uncore/HWDATA -add wave -divider -add wave -hex /testbench/PCW -add wave -hex /testbench/InstrW -add wave /testbench/InstrWName -add wave /testbench/dut/hart/ieu/dp/RegWriteW -add wave -hex /testbench/dut/hart/ieu/dp/ResultW -add wave -hex /testbench/dut/hart/ieu/dp/RdW -add wave -divider - -# appearance -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {100 ps} -configure wave -namecolwidth 250 -configure wave -valuecolwidth 150 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -set DefaultRadix hexadecimal \ No newline at end of file diff --git a/wally-pipelined/regression/wave-dos/busybear-waves.do b/wally-pipelined/regression/wave-dos/linux-waves.do similarity index 53% rename from wally-pipelined/regression/wave-dos/busybear-waves.do rename to wally-pipelined/regression/wave-dos/linux-waves.do index 00df1087a..58da63301 100644 --- a/wally-pipelined/regression/wave-dos/busybear-waves.do +++ b/wally-pipelined/regression/wave-dos/linux-waves.do @@ -1,58 +1,66 @@ -# busybear-waves.do - +# linux-waves.do restart -f delete wave /* view wave --- display input and output signals as hexidecimal values -# Diplays All Signals recursively +add wave -divider add wave /testbench/clk add wave /testbench/reset -add wave -divider -add wave -hex /testbench/PCtext + +add wave -divider Stalls_and_Flushes +add wave /testbench/dut/hart/StallF +add wave /testbench/dut/hart/StallD +add wave /testbench/dut/hart/StallE +add wave /testbench/dut/hart/StallM +add wave /testbench/dut/hart/StallW +add wave -group stall_srcs /testbench/dut/hart/DataStall +add wave -group stall_srcs /testbench/dut/hart/ICacheStallF +add wave /testbench/dut/hart/FlushD +add wave /testbench/dut/hart/FlushE +add wave /testbench/dut/hart/FlushM +add wave /testbench/dut/hart/FlushW + +add wave -divider F +add wave -hex /testbench/dut/hart/ifu/PCF +add wave -divider D add wave -hex /testbench/pcExpected add wave -hex /testbench/dut/hart/ifu/PCD +add wave -hex /testbench/PCtextD +add wave /testbench/InstrDName add wave -hex /testbench/dut/hart/ifu/InstrD -add wave -hex /testbench/dut/hart/ifu/StallD -add wave -hex /testbench/dut/hart/ifu/FlushD -add wave -hex /testbench/dut/hart/ifu/StallE -add wave -hex /testbench/dut/hart/ifu/FlushE -add wave -hex /testbench/dut/hart/ifu/InstrRawD -add wave /testbench/CheckInstrD -add wave /testbench/lastCheckInstrD -add wave /testbench/speculative -add wave /testbench/lastPC2 -add wave -divider -add wave -divider -add wave /testbench/dut/uncore/HSELBootTim -add wave /testbench/dut/uncore/HSELTim -add wave /testbench/dut/uncore/HREADTim -add wave /testbench/dut/uncore/dtim/HREADTim0 -add wave /testbench/dut/uncore/HREADYTim -add wave -divider -add wave /testbench/dut/uncore/HREADBootTim -add wave /testbench/dut/uncore/bootdtim/HREADTim0 -add wave /testbench/dut/uncore/HREADYBootTim -add wave /testbench/dut/uncore/HADDR -add wave /testbench/dut/uncore/HRESP -add wave /testbench/dut/uncore/HREADY -add wave /testbench/dut/uncore/HRDATA -#add wave -hex /testbench/dut/hart/priv/csr/MTVEC_REG -#add wave -hex /testbench/dut/hart/priv/csr/MSTATUS_REG -#add wave -hex /testbench/dut/hart/priv/csr/SCOUNTEREN_REG -#add wave -hex /testbench/dut/hart/priv/csr/MIE_REG -#add wave -hex /testbench/dut/hart/priv/csr/MIDELEG_REG -#add wave -hex /testbench/dut/hart/priv/csr/MEDELEG_REG -add wave -divider -# registers! +add wave -hex /testbench/dut/hart/ieu/c/InstrValidD +add wave -divider E +add wave -hex /testbench/dut/hart/ifu/PCE +add wave -hex /testbench/PCtextE +add wave /testbench/InstrEName +add wave -hex /testbench/dut/hart/ifu/InstrE +add wave -hex /testbench/dut/hart/ieu/c/InstrValidE +add wave -hex /testbench/dut/hart/ieu/dp/SrcAE +add wave -hex /testbench/dut/hart/ieu/dp/SrcBE +add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE +add wave -divider M +add wave -hex /testbench/dut/hart/ifu/PCM +add wave -hex /testbench/PCtextM +add wave /testbench/InstrMName +add wave -hex /testbench/dut/hart/ifu/InstrM +add wave -hex /testbench/dut/hart/ieu/c/InstrValidM +add wave /testbench/dut/uncore/dtim/memwrite +add wave -hex /testbench/dut/uncore/HADDR +add wave -hex /testbench/HWRITE +add wave -hex /testbench/dut/uncore/HWDATA +add wave -hex /testbench/HRDATA +add wave -hex /testbench/readAdrExpected +add wave -divider W +add wave -hex /testbench/PCW +add wave -hex /testbench/PCtextW +add wave -hex /testbench/dut/hart/ieu/c/InstrValidW +add wave /testbench/dut/hart/ieu/dp/RegWriteW +add wave -hex /testbench/dut/hart/ieu/dp/ResultW +add wave -hex /testbench/dut/hart/ieu/dp/RdW + +add wave -divider RegFile add wave -hex /testbench/regExpected add wave -hex /testbench/regNumExpected -add wave -hex /testbench/HWRITE -add wave -hex /testbench/dut/hart/MemRWM[1] -add wave -hex /testbench/HWDATA -add wave -hex /testbench/HRDATA -add wave -hex /testbench/HADDR -add wave -hex /testbench/readAdrExpected add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[1] add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[2] add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[3] @@ -84,36 +92,10 @@ add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[28] add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[29] add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[30] add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[31] -add wave /testbench/InstrFName -add wave -hex /testbench/dut/hart/ifu/PCD -#add wave -hex /testbench/dut/hart/ifu/InstrD -add wave /testbench/InstrDName -#add wave -divider -add wave -hex /testbench/dut/hart/ifu/PCE -##add wave -hex /testbench/dut/hart/ifu/InstrE -add wave /testbench/InstrEName -#add wave -hex /testbench/dut/hart/ieu/dp/SrcAE -#add wave -hex /testbench/dut/hart/ieu/dp/SrcBE -add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE -#add wave /testbench/dut/hart/ieu/dp/PCSrcE -#add wave -divider -add wave -hex /testbench/dut/hart/ifu/PCM -##add wave -hex /testbench/dut/hart/ifu/InstrM -add wave /testbench/InstrMName -#add wave /testbench/dut/hart/dmem/dtim/memwrite -#add wave -hex /testbench/dut/hart/dmem/AdrM -#add wave -hex /testbench/dut/hart/dmem/WriteDataM -#add wave -divider -add wave -hex /testbench/PCW -##add wave -hex /testbench/dut/hart/ifu/InstrW -add wave /testbench/InstrWName -#add wave /testbench/dut/hart/ieu/dp/RegWriteW -#add wave -hex /testbench/dut/hart/ieu/dp/ResultW -#add wave -hex /testbench/dut/hart/ieu/dp/RdW -#add wave -divider -##add ww + +add wave -divider add wave -hex -r /testbench/* -# + # appearance TreeUpdate [SetDefaultTree] WaveRestoreZoom {0 ps} {100 ps} diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv index a42e29376..ae192e4dd 100644 --- a/wally-pipelined/src/privileged/csr.sv +++ b/wally-pipelined/src/privileged/csr.sv @@ -39,6 +39,7 @@ module csr #(parameter input logic InterruptM, input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM, input logic TimerIntM, ExtIntM, SwIntM, + input logic [63:0] MTIME, MTIMECMP, input logic InstrValidW, FloatRegWriteW, LoadStallD, input logic BPPredDirWrongM, input logic BTBPredPCWrongM, diff --git a/wally-pipelined/src/privileged/csrc.sv b/wally-pipelined/src/privileged/csrc.sv index 131338921..f1cb9e0b8 100644 --- a/wally-pipelined/src/privileged/csrc.sv +++ b/wally-pipelined/src/privileged/csrc.sv @@ -27,11 +27,11 @@ /////////////////////////////////////////// `include "wally-config.vh" - +// Ben 06/17/21: I brought in MTIME, MTIMECMP from CLINT. *** this probably isn't perfect though because it doesn't yet provide the ability to change these through CSR writes; overall this whole thing might need some rethinking module csrc #(parameter MCYCLE = 12'hB00, -// MTIME = 12'hB01, // address not specified in privileged spec. Consider moving to CLINT to match SiFive - // MTIMECMP = 12'hB21, // not specified in privileged spec. Move to CLINT + MTIMEadr = 12'hB01, // address not specified in privileged spec. Consider moving to CLINT to match SiFive + MTIMECMPadr = 12'hB21, // not specified in privileged spec. Move to CLINT MINSTRET = 12'hB02, MHPMCOUNTERBASE = 12'hB00, //MHPMCOUNTER3 = 12'hB03, @@ -39,8 +39,8 @@ module csrc #(parameter // ... more counters //MHPMCOUNTER31 = 12'hB1F, MCYCLEH = 12'hB80, -// MTIMEH = 12'hB81, // address not specified in privileged spec. Consider moving to CLINT to match SiFive -// MTIMECMPH = 12'hBA1, // not specified in privileged spec. Move to CLINT + MTIMEHadr = 12'hB81, // address not specified in privileged spec. Consider moving to CLINT to match SiFive + MTIMECMPHadr = 12'hBA1, // not specified in privileged spec. Move to CLINT MINSTRETH = 12'hB82, MHPMCOUNTERHBASE = 12'hB80, //MHPMCOUNTER3H = 12'hB83, @@ -54,7 +54,7 @@ module csrc #(parameter // ... more counters //MHPMEVENT31 = 12'h33F, CYCLE = 12'hC00, -// TIME = 12'hC01, // not specified + TIME = 12'hC01, INSTRET = 12'hC02, HPMCOUNTERBASE = 12'hC00, //HPMCOUNTER3 = 12'hC03, @@ -62,7 +62,7 @@ module csrc #(parameter // ...more counters //HPMCOUNTER31 = 12'hC1F, CYCLEH = 12'hC80, -// TIMEH = 12'hC81, // not specified + TIMEH = 12'hC81, // not specified INSTRETH = 12'hC82, HPMCOUNTERHBASE = 12'hC80 //HPMCOUNTER3H = 12'hC83, @@ -71,17 +71,18 @@ module csrc #(parameter //HPMCOUNTER31H = 12'hC9F ) ( input logic clk, reset, - input logic StallD, StallE, StallM, StallW, + input logic StallD, StallE, StallM, StallW, input logic InstrValidW, LoadStallD, CSRMWriteM, - input logic BPPredDirWrongM, - input logic BTBPredPCWrongM, - input logic RASPredPCWrongM, - input logic BPPredClassNonCFIWrongM, - input logic [4:0] InstrClassM, + input logic BPPredDirWrongM, + input logic BTBPredPCWrongM, + input logic RASPredPCWrongM, + input logic BPPredClassNonCFIWrongM, + input logic [4:0] InstrClassM, input logic [11:0] CSRAdrM, input logic [1:0] PrivilegeModeW, input logic [`XLEN-1:0] CSRWriteValM, input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW, + input logic [63:0] MTIME, MTIMECMP, output logic [`XLEN-1:0] CSRCReadValM, output logic IllegalCSRCAccessM ); @@ -112,12 +113,12 @@ module csrc #(parameter // Counter adders with inhibits for power savings assign CYCLEPlusM = CYCLE_REGW + {63'b0, ~MCOUNTINHIBIT_REGW[0]}; - // assign TIMEPlusM = TIME_REGW + 1; // can't be inhibited + //assign TIMEPlusM = TIME_REGW + 1; // can't be inhibited assign INSTRETPlusM = INSTRET_REGW + {63'b0, InstrValidW & ~MCOUNTINHIBIT_REGW[2]}; //assign HPMCOUNTER3PlusM = HPMCOUNTER3_REGW + {63'b0, LoadStallD & ~MCOUNTINHIBIT_REGW[3]}; // count load stalls - ///assign HPMCOUNTER4PlusM = HPMCOUNTER4_REGW + {63'b0, 1'b0 & ~MCOUNTINHIBIT_REGW[4]}; // change to count signals + //assign HPMCOUNTER4PlusM = HPMCOUNTER4_REGW + {63'b0, 1'b0 & ~MCOUNTINHIBIT_REGW[4]}; // change to count signals assign NextCYCLEM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[`XLEN-1:0]; - // assign NextTIMEM = WriteTIMEM ? CSRWriteValM : TIMEPlusM[`XLEN-1:0]; + //assign NextTIMEM = WriteTIMEM ? CSRWriteValM : TIMEPlusM[`XLEN-1:0]; assign NextINSTRETM = WriteINSTRETM ? CSRWriteValM : INSTRETPlusM[`XLEN-1:0]; //assign NextHPMCOUNTER3M = WriteHPMCOUNTER3M ? CSRWriteValM : HPMCOUNTER3PlusM[`XLEN-1:0]; //assign NextHPMCOUNTER4M = WriteHPMCOUNTER4M ? CSRWriteValM : HPMCOUNTER4PlusM[`XLEN-1:0]; @@ -211,7 +212,7 @@ module csrc #(parameter //flopr #(32) HPMCOUNTER4Hreg(clk, reset, NextHPMCOUNTER4HM, HPMCOUNTER4_REGW[63:32]); end - // eventually move TIME and TIMECMP to the CLINT + // eventually move TIME and TIMECMP to the CLINT -- Ben 06/17/21: sure let's give that a shot! // run TIME off asynchronous reference clock // synchronize write enable to TIME // four phase handshake to synchronize reads from TIME @@ -229,13 +230,13 @@ module csrc #(parameter if (CSRAdrM >= MHPMCOUNTERBASE+3 && CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-MHPMCOUNTERBASE]; else if (CSRAdrM >= HPMCOUNTERBASE+3 && CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-HPMCOUNTERBASE]; else case (CSRAdrM) - // MTIME: CSRCReadValM = TIME_REGW; - // MTIMECMP: CSRCReadValM = TIMECMP_REGW; + MTIMEadr: CSRCReadValM = MTIME; + MTIMECMPadr: CSRCReadValM = MTIMECMP; MCYCLE: CSRCReadValM = CYCLE_REGW; MINSTRET: CSRCReadValM = INSTRET_REGW; //MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW; //MHPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW; - // TIME: CSRCReadValM = TIME_REGW; + TIME: CSRCReadValM = MTIME; CYCLE: CSRCReadValM = CYCLE_REGW; INSTRET: CSRCReadValM = INSTRET_REGW; //HPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW; @@ -258,24 +259,24 @@ module csrc #(parameter else if (CSRAdrM >= MHPMCOUNTERHBASE+3 && CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CSRAdrM-MHPMCOUNTERHBASE]; else if (CSRAdrM >= HPMCOUNTERHBASE+3 && CSRAdrM < HPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CSRAdrM-HPMCOUNTERHBASE]; else case (CSRAdrM) - // MTIME: CSRCReadValM = TIME_REGW[31:0]; - // MTIMECMP: CSRCReadValM = TIMECMP_REGW[31:0]; + MTIMEadr: CSRCReadValM = MTIME[31:0]; + MTIMECMPadr: CSRCReadValM = MTIMECMP[31:0]; MCYCLE: CSRCReadValM = CYCLE_REGW[31:0]; MINSTRET: CSRCReadValM = INSTRET_REGW[31:0]; //MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW[31:0]; //MHPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW[31:0]; - // TIME: CSRCReadValM = TIME_REGW[31:0]; + TIME: CSRCReadValM = MTIME[31:0]; CYCLE: CSRCReadValM = CYCLE_REGW[31:0]; INSTRET: CSRCReadValM = INSTRET_REGW[31:0]; //HPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW[31:0]; //HPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW[31:0]; - // MTIMEH: CSRCReadValM = TIME_REGW[63:32]; - // MTIMECMPH: CSRCReadValM = TIMECMP_REGW[63:32]; + MTIMEHadr: CSRCReadValM = MTIME[63:32]; + MTIMECMPHadr: CSRCReadValM = MTIMECMP[63:32]; MCYCLEH: CSRCReadValM = CYCLE_REGW[63:32]; MINSTRETH: CSRCReadValM = INSTRET_REGW[63:32]; //MHPMCOUNTER3H: CSRCReadValM = HPMCOUNTER3_REGW[63:32]; //MHPMCOUNTER4H: CSRCReadValM = HPMCOUNTER4_REGW[63:32]; - // TIMEH: CSRCReadValM = TIME_REGW[63:32]; + TIMEH: CSRCReadValM = MTIME[63:32]; CYCLEH: CSRCReadValM = CYCLE_REGW[63:32]; INSTRETH: CSRCReadValM = INSTRET_REGW[63:32]; //HPMCOUNTER3H: CSRCReadValM = HPMCOUNTER3_REGW[63:32]; diff --git a/wally-pipelined/src/privileged/csrm.sv b/wally-pipelined/src/privileged/csrm.sv index bbf765dc5..209eadd8b 100644 --- a/wally-pipelined/src/privileged/csrm.sv +++ b/wally-pipelined/src/privileged/csrm.sv @@ -172,7 +172,7 @@ module csrm #(parameter // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop generate genvar i; - for (i = 0; i < `PMP_ENTRIES-1; i++) begin: pmp_flop + for (i = 0; i < `PMP_ENTRIES; i++) begin: pmp_flop flopenr #(`XLEN) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM, PMPADDR_ARRAY_REGW[i]); end endgenerate diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index 4f4ecd70f..839bae942 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -52,6 +52,7 @@ module privileged ( input logic LoadMisalignedFaultM, input logic StoreMisalignedFaultM, input logic TimerIntM, ExtIntM, SwIntM, + input logic [63:0] MTIME, MTIMECMP, input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, input logic [4:0] SetFflagsM, diff --git a/wally-pipelined/src/uncore/clint.sv b/wally-pipelined/src/uncore/clint.sv index df4c1e8fa..d2014468a 100644 --- a/wally-pipelined/src/uncore/clint.sv +++ b/wally-pipelined/src/uncore/clint.sv @@ -36,9 +36,9 @@ module clint ( input logic [1:0] HTRANS, output logic [`XLEN-1:0] HREADCLINT, output logic HRESPCLINT, HREADYCLINT, + output logic [63:0] MTIME, MTIMECMP, output logic TimerIntM, SwIntM); - logic [63:0] MTIMECMP, MTIME; logic MSIP; logic [15:0] entry, entryd; diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv index 0eae1e611..af9f6b6b5 100644 --- a/wally-pipelined/src/uncore/uncore.sv +++ b/wally-pipelined/src/uncore/uncore.sv @@ -57,7 +57,8 @@ module uncore ( input logic [31:0] GPIOPinsIn, output logic [31:0] GPIOPinsOut, GPIOPinsEn, input logic UARTSin, - output logic UARTSout + output logic UARTSout, + output logic [63:0] MTIME, MTIMECMP ); logic [`XLEN-1:0] HWDATA; diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 538f91546..9cc8058a5 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -34,6 +34,7 @@ module wallypipelinedhart ( input logic TimerIntM, ExtIntM, SwIntM, input logic InstrAccessFaultF, input logic DataAccessFaultM, + input logic [63:0] MTIME, MTIMECMP, // Bus Interface input logic [15:0] rd2, // bogus, delete when real multicycle fetch works input logic [`AHBW-1:0] HRDATA, diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv index 7974b7ace..bde2eb2be 100644 --- a/wally-pipelined/src/wally/wallypipelinedsoc.sv +++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv @@ -63,6 +63,7 @@ module wallypipelinedsoc ( logic [5:0] HSELRegions; logic InstrAccessFaultF, DataAccessFaultM; logic TimerIntM, SwIntM; // from CLINT + logic [63:0] MTIME, MTIMECMP; // from CLINT to CSRs logic ExtIntM; // from PLIC logic [2:0] HADDRD; logic [3:0] HSIZED; diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 52c40060c..6cf20e674 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -162,7 +162,7 @@ module testbench(); // read CSR trace file integer data_file_csr, scan_file_csr; initial begin - data_file_csr = $fopen({`LINUX_TEST_VECTORS,"parsedCSRs2.txt"}, "r"); + data_file_csr = $fopen({`LINUX_TEST_VECTORS,"parsedCSRs.txt"}, "r"); if (data_file_csr == 0) begin $display("file couldn't be opened"); $stop; @@ -473,7 +473,21 @@ module testbench(); end end - string PCtext, PCtext2; + string PCtextD,PCtextE,PCtextM,PCtext2; + always_ff @(posedge clk, posedge reset) + if (reset) begin + PCtextE <= #1 "(reset)"; + PCtextM <= #1 "(reset)"; + end else begin + if (~dut.hart.StallE) + if (dut.hart.FlushE) PCtextE <= #1 "(flushed)"; + else PCtextE <= #1 PCtextD; + if (~dut.hart.StallM) + if (dut.hart.FlushM) PCtextM <= #1 "(flushed)"; + else PCtextM <= #1 PCtextE; + end + + initial begin instrs = 0; end @@ -495,7 +509,7 @@ module testbench(); (dut.hart.ifu.PCD == 32'h80001dc6) || // as well as stores to PLIC (dut.hart.ifu.PCD == 32'h80001de0) || (dut.hart.ifu.PCD == 32'h80001de2)) begin - $display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.hart.ifu.PCD, instrs, $time); + $display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtextD, dut.hart.ifu.PCD, instrs, $time); force CheckInstrD = 32'b0010011; force dut.hart.ifu.InstrRawD = 32'b0010011; while (clk != 0) #1; @@ -515,10 +529,10 @@ module testbench(); $display("no more PC data to read"); `ERROR end - scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext); + scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtextD); PCtext2 = ""; while (PCtext2 != "***") begin - PCtext = {PCtext, " ", PCtext2}; + PCtextD = {PCtextD, " ", PCtext2}; scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2); end scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrD); @@ -527,7 +541,7 @@ module testbench(); (dut.hart.ifu.PCD == 32'h80001dc6) || // as well as stores to PLIC (dut.hart.ifu.PCD == 32'h80001de0) || (dut.hart.ifu.PCD == 32'h80001de2)) begin - $display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.hart.ifu.PCD, instrs, $time); + $display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtextD, dut.hart.ifu.PCD, instrs, $time); force CheckInstrD = 32'b0010011; force dut.hart.ifu.InstrRawD = 32'b0010011; while (clk != 0) #1;