diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh
index d117f6128..d48a06d09 100644
--- a/wally-pipelined/config/busybear/wally-config.vh
+++ b/wally-pipelined/config/busybear/wally-config.vh
@@ -97,3 +97,4 @@
`define TWO_BIT_PRELOAD "../config/busybear/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/busybear/BTBPredictor.txt"
+`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh
index 2103d65b4..7653f3903 100644
--- a/wally-pipelined/config/coremark/wally-config.vh
+++ b/wally-pipelined/config/coremark/wally-config.vh
@@ -95,3 +95,4 @@
`define TWO_BIT_PRELOAD "../config/coremark/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/coremark/BTBPredictor.txt"
+`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh
index 171c461fe..edcd6107c 100644
--- a/wally-pipelined/config/rv32ic/wally-config.vh
+++ b/wally-pipelined/config/rv32ic/wally-config.vh
@@ -92,3 +92,4 @@
`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
+`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh
index f5e1cf3ae..7057db955 100644
--- a/wally-pipelined/config/rv64ic/wally-config.vh
+++ b/wally-pipelined/config/rv64ic/wally-config.vh
@@ -95,3 +95,4 @@
`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt"
+`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
diff --git a/wally-pipelined/config/rv64icfd/wally-config.vh b/wally-pipelined/config/rv64icfd/wally-config.vh
index 85082bf4e..617be64ae 100644
--- a/wally-pipelined/config/rv64icfd/wally-config.vh
+++ b/wally-pipelined/config/rv64icfd/wally-config.vh
@@ -95,3 +95,4 @@
`define TWO_BIT_PRELOAD "../config/rv64icfd/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/rv64icfd/BTBPredictor.txt"
+`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index 89d0fdeef..379c7ab49 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -36,11 +36,9 @@ add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
add wave -noupdate -group Bpred -expand -group direction -divider Update
-add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdatePC
-add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdateEN
-add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdatePCIndex
-add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdatePrediction
-add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
+add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/UpdatePC
+add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/UpdateEN
+add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/UpdatePrediction
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/TargetWrongE
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/FallThroughWrongE
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionDirWrongE
@@ -144,7 +142,7 @@ add wave -noupdate -group {function radix debug} /testbench/functionRadix/functi
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramAddrIndex
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/FunctionName
TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {181681 ns} 0} {{Cursor 3} {20231927 ns} 0}
+WaveRestoreCursors {{Cursor 2} {3758805 ns} 0}
quietly wave cursor active 1
configure wave -namecolwidth 250
configure wave -valuecolwidth 229
@@ -160,4 +158,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
-WaveRestoreZoom {11339470 ns} {14752202 ns}
+WaveRestoreZoom {1644110 ns} {15262484 ns}
diff --git a/wally-pipelined/src/ifu/bpred.sv b/wally-pipelined/src/ifu/bpred.sv
index 35ac6cfb5..38d959484 100644
--- a/wally-pipelined/src/ifu/bpred.sv
+++ b/wally-pipelined/src/ifu/bpred.sv
@@ -66,14 +66,44 @@ module bpred
// Part 1 branch direction prediction
- twoBitPredictor DirPredictor(.clk(clk),
- .reset(reset),
- .LookUpPC(PCNextF),
- .Prediction(BPPredF),
- // update
- .UpdatePC(PCE),
- .UpdateEN(InstrClassE[0]),
- .UpdatePrediction(UpdateBPPredE));
+ generate
+ if (`BPTYPE == "BPTWOBIT") begin:Predictor
+ twoBitPredictor DirPredictor(.clk(clk),
+ .reset(reset),
+ .LookUpPC(PCNextF),
+ .Prediction(BPPredF),
+ // update
+ .UpdatePC(PCE),
+ .UpdateEN(InstrClassE[0]),
+ .UpdatePrediction(UpdateBPPredE));
+
+ end else if (`BPTYPE == "BPGLOBAL") begin:Predictor
+
+ globalHistoryPredictor DirPredictor(.clk(clk),
+ .reset(reset),
+ .*, // Stalls and flushes
+ .LookUpPC(PCNextF),
+ .Prediction(BPPredF),
+ // update
+ .UpdatePC(PCE),
+ .UpdateEN(InstrClassE[0]),
+ .PCSrcE(PCSrcE),
+ .UpdatePrediction(UpdateBPPredE));
+ end else if (`BPTYPE == "BPGSHARE") begin:Predictor
+
+ gsharePredictor DirPredictor(.clk(clk),
+ .reset(reset),
+ .*, // Stalls and flushes
+ .LookUpPC(PCNextF),
+ .Prediction(BPPredF),
+ // update
+ .UpdatePC(PCE),
+ .UpdateEN(InstrClassE[0]),
+ .PCSrcE(PCSrcE),
+ .UpdatePrediction(UpdateBPPredE));
+ end
+ endgenerate
+
// this predictor will have two pieces of data,
// 1) A direction (1 = Taken, 0 = Not Taken)
diff --git a/wally-pipelined/src/ifu/globalHistoryPredictor.sv b/wally-pipelined/src/ifu/globalHistoryPredictor.sv
new file mode 100644
index 000000000..b9addb381
--- /dev/null
+++ b/wally-pipelined/src/ifu/globalHistoryPredictor.sv
@@ -0,0 +1,109 @@
+///////////////////////////////////////////
+// globalHistoryPredictor.sv
+//
+// Written: Shreya Sanghai
+// Email: ssanghai@hmc.edu
+// Created: March 16, 2021
+// Modified:
+//
+// Purpose: Global History Branch predictor with parameterized global history register
+//
+// A component of the Wally configurable RISC-V project.
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module globalHistoryPredictor
+ #(parameter int k = 10
+ )
+ (input logic clk,
+ input logic reset,
+ input logic StallF, StallD, StallE, FlushF, FlushD, FlushE,
+ input logic [`XLEN-1:0] LookUpPC,
+ output logic [1:0] Prediction,
+ // update
+ input logic [`XLEN-1:0] UpdatePC,
+ input logic UpdateEN, PCSrcE, /// *** need to add as input from bpred.sv
+ input logic [1:0] UpdatePrediction
+
+ );
+ logic [k-1:0] GHRF, GHRD, GHRE;
+
+ flopenr #(k) GlobalHistoryRegister(.clk(clk),
+ .reset(reset),
+ .en(UpdateEN),
+ .d({PCSrcE, GHRF[k-1:1] }),
+ .q(GHRF));
+
+
+
+ logic [1:0] PredictionMemory;
+ logic DoForwarding, DoForwardingF;
+ logic [1:0] UpdatePredictionF;
+
+ // for gshare xor the PC with the GHR
+ // TODO: change in sram memory2 module
+ // assign UpdatePCIndex = GHRE ^ UpdatePC;
+ // assign LookUpPCIndex = LookUpPC ^ GHR;
+ // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT
+ // GHR referes to the address that the past k branches points to in the prediction stage
+ // GHRE refers to the address that the past k branches points to in the exectution stage
+ SRAM2P1R1W #(k, 2) PHT(.clk(clk),
+ .reset(reset),
+ .RA1(GHRF),
+ .RD1(PredictionMemory),
+ .REN1(1'b1),
+ .WA1(GHRE),
+ .WD1(UpdatePrediction),
+ .WEN1(UpdateEN),
+ .BitWEN1(2'b11));
+
+
+ // need to forward when updating to the same address as reading.
+ // first we compare to see if the update and lookup addreses are the same
+ assign DoForwarding = GHRF == GHRE;
+
+ // register the update value and the forwarding signal into the Fetch stage
+ // TODO: add stall logic ***
+ flopr #(1) DoForwardingReg(.clk(clk),
+ .reset(reset),
+ .d(DoForwarding),
+ .q(DoForwardingF));
+
+ flopr #(2) UpdatePredictionReg(.clk(clk),
+ .reset(reset),
+ .d(UpdatePrediction),
+ .q(UpdatePredictionF));
+
+ assign Prediction = DoForwardingF ? UpdatePredictionF : PredictionMemory;
+
+ //pipeline for GHR
+ flopenrc #(k) GHRDReg(.clk(clk),
+ .reset(reset),
+ .en(~StallD),
+ .clear(FlushD),
+ .d(GHRF),
+ .q(GHRD));
+
+ flopenrc #(k) GHREReg(.clk(clk),
+ .reset(reset),
+ .en(~StallE),
+ .clear(FlushE),
+ .d(GHRD),
+ .q(GHRE));
+
+endmodule
diff --git a/wally-pipelined/src/ifu/gshare.sv b/wally-pipelined/src/ifu/gshare.sv
new file mode 100644
index 000000000..a1c5bbc7a
--- /dev/null
+++ b/wally-pipelined/src/ifu/gshare.sv
@@ -0,0 +1,109 @@
+///////////////////////////////////////////
+// gshare.sv
+//
+// Written: Shreya Sanghai
+// Email: ssanghai@hmc.edu
+// Created: March 16, 2021
+// Modified:
+//
+// Purpose: Gshare predictor with parameterized global history register
+//
+// A component of the Wally configurable RISC-V project.
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module gsharePredictor
+ #(parameter int k = 10
+ )
+ (input logic clk,
+ input logic reset,
+ input logic StallF, StallD, StallE, FlushF, FlushD, FlushE,
+ input logic [`XLEN-1:0] LookUpPC,
+ output logic [1:0] Prediction,
+ // update
+ input logic [`XLEN-1:0] UpdatePC,
+ input logic UpdateEN, PCSrcE,
+ input logic [1:0] UpdatePrediction
+
+ );
+
+ logic [k-1:0] GHRF, GHRD, GHRE;
+ logic [k-1:0] LookUpPCIndexD, LookUpPCIndexE;
+ logic [k-1:0] LookUpPCIndex, UpdatePCIndex;
+ logic [1:0] PredictionMemory;
+ logic DoForwarding, DoForwardingF;
+ logic [1:0] UpdatePredictionF;
+
+ flopenr #(k) GlobalHistoryRegister(.clk(clk),
+ .reset(reset),
+ .en(UpdateEN),
+ .d({PCSrcE, GHRF[k-1:1] }),
+ .q(GHRF));
+
+
+ // for gshare xor the PC with the GHR
+ assign UpdatePCIndex = GHRE ^ UpdatePC[k:1];
+ assign LookUpPCIndex = GHRF ^ LookUpPC[k:1];
+ // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT
+ // GHR referes to the address that the past k branches points to in the prediction stage
+ // GHRE refers to the address that the past k branches points to in the exectution stage
+ SRAM2P1R1W #(k, 2) PHT(.clk(clk),
+ .reset(reset),
+ .RA1(LookUpPCIndex),
+ .RD1(PredictionMemory),
+ .REN1(1'b1),
+ .WA1(UpdatePCIndex),
+ .WD1(UpdatePrediction),
+ .WEN1(UpdateEN),
+ .BitWEN1(2'b11));
+
+
+ // need to forward when updating to the same address as reading.
+ // first we compare to see if the update and lookup addreses are the same
+ assign DoForwarding = LookUpPCIndex == UpdatePCIndex;
+
+ // register the update value and the forwarding signal into the Fetch stage
+ // TODO: add stall logic ***
+ flopr #(1) DoForwardingReg(.clk(clk),
+ .reset(reset),
+ .d(DoForwarding),
+ .q(DoForwardingF));
+
+ flopr #(2) UpdatePredictionReg(.clk(clk),
+ .reset(reset),
+ .d(UpdatePrediction),
+ .q(UpdatePredictionF));
+
+ assign Prediction = DoForwardingF ? UpdatePredictionF : PredictionMemory;
+
+ //pipeline for GHR
+ flopenrc #(k) LookUpDReg(.clk(clk),
+ .reset(reset),
+ .en(~StallD),
+ .clear(FlushD),
+ .d(LookUpPCIndex),
+ .q(LookUpPCIndexD));
+
+ flopenrc #(k) LookUpEReg(.clk(clk),
+ .reset(reset),
+ .en(~StallE),
+ .clear(FlushE),
+ .d(LookUpPCIndexD),
+ .q(LookUpPCIndexE));
+
+endmodule
diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv
index 5d3c24a49..118922867 100644
--- a/wally-pipelined/src/privileged/csr.sv
+++ b/wally-pipelined/src/privileged/csr.sv
@@ -33,7 +33,7 @@ module csr (
input logic [`XLEN-1:0] PCM, SrcAM,
input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM,
input logic TimerIntM, ExtIntM, SwIntM,
- input logic InstrValidW, FloatRegWriteW, LoadStallD,
+ input logic InstrValidW, FloatRegWriteW, LoadStallD, BPPredWrongE,
input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
input logic [`XLEN-1:0] CauseM, NextFaultMtvalM,
output logic [1:0] STATUS_MPP,
diff --git a/wally-pipelined/src/privileged/csrc.sv b/wally-pipelined/src/privileged/csrc.sv
index ae14f0f3b..57bac3c24 100644
--- a/wally-pipelined/src/privileged/csrc.sv
+++ b/wally-pipelined/src/privileged/csrc.sv
@@ -29,7 +29,7 @@
module csrc (
input logic clk, reset,
- input logic InstrValidW, LoadStallD, CSRMWriteM,
+ input logic InstrValidW, LoadStallD, CSRMWriteM, BPPredWrongE,
input logic [11:0] CSRAdrM,
input logic [1:0] PrivilegeModeW,
input logic [`XLEN-1:0] CSRWriteValM,
@@ -62,7 +62,8 @@ module csrc (
assign MCOUNTEN[1] = 1'b0;
assign MCOUNTEN[2] = InstrValidW;
assign MCOUNTEN[3] = LoadStallD;
- assign MCOUNTEN[`COUNTERS:4] = 0;
+ assign MCOUNTEN[4] = BPPredWrongE;
+ assign MCOUNTEN[`COUNTERS:5] = 0;
genvar j;
generate
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index 0830d3475..a2818b6a4 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -36,7 +36,7 @@ module privileged (
output logic [`XLEN-1:0] CSRReadValW,
output logic [`XLEN-1:0] PrivilegedNextPCM,
output logic RetM, TrapM,
- input logic InstrValidW, FloatRegWriteW, LoadStallD,
+ input logic InstrValidW, FloatRegWriteW, LoadStallD, BPPredWrongE,
input logic PrivilegedM,
input logic InstrMisalignedFaultM, InstrAccessFaultF, IllegalIEUInstrFaultD,
input logic LoadMisalignedFaultM, LoadAccessFaultM,
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index 7b7d7f95b..2f6f0efbc 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -484,7 +484,7 @@ string tests32i[] = {
// initialize the branch predictor
initial begin
- $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.DirPredictor.memory.memory);
+ $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);
end