From 8648d0c25c730b0ad87d138c0d7c22bab8b584ba Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 30 May 2023 15:51:13 -0500
Subject: [PATCH] Hacked it together, but I think testfloat is working.

---
 sim/testfloat.do          |  2 +-
 testbench/testbench-fp.sv | 17 +++++++++++++----
 2 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/sim/testfloat.do b/sim/testfloat.do
index b2fb2e1dc..c8e8ae7b4 100644
--- a/sim/testfloat.do
+++ b/sim/testfloat.do
@@ -25,7 +25,7 @@ vlib work
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
 # $num = the added words after the call
-vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv  ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 
+vlog +incdir+../config/$1 +incdir+../config/shared ../src/wally/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv  ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 
 
 vsim -voptargs=+acc work.testbenchfp -G TEST=$2
 
diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv
index b7fcc237f..497557f58 100644
--- a/testbench/testbench-fp.sv
+++ b/testbench/testbench-fp.sv
@@ -24,8 +24,11 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 `include "wally-config.vh"
+`include "config.vh"
 `include "tests-fp.vh"
 
+import cvw::*;
+
 module testbenchfp;
   parameter TEST="none";
 
@@ -106,7 +109,10 @@ module testbenchfp;
    logic                       IFDivStartE, FDivDoneE;
    logic [`NE+1:0]             QeM;
    logic [`DIVb:0]             QmM;
-   logic [`XLEN-1:0]           FIntDivResultM;   
+   logic [`XLEN-1:0]           FIntDivResultM;
+
+  `include "parameter-defs.vh"
+  
 
 
   ///////////////////////////////////////////////////////////////////////////////////////////////
@@ -681,7 +687,7 @@ module testbenchfp;
             .ASticky); 
   end
               
-  postprocess postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]),
+  postprocess #(P) postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]),
               .OpCtrl(OpCtrlVal), .DivQm(Quot), .DivQe(DivCalcExp),
               .Xm(Xm), .Ym(Ym), .Zm(Zm), .CvtCe(CvtCalcExpE), .DivSticky(DivSticky), .FmaSs(Ss),
               .XNaN(XNaN), .YNaN(YNaN), .ZNaN(ZNaN), .CvtResSubnormUf(CvtResSubnormUfE),
@@ -704,7 +710,7 @@ module testbenchfp;
                 .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
   end
   if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt
-     fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), 
+     fdivsqrt #(P) fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), 
 		       .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
                        .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), 
 		       .XNaNE(XNaN), .YNaNE(YNaN), 
@@ -982,6 +988,8 @@ module readvectors (
 );
   logic XEn, YEn, ZEn;
 
+  `include "parameter-defs.vh"
+
   // apply test vectors on rising edge of clk
   // Format of vectors Inputs(1/2/3)_AnsFlg
   always @(VectorNum) begin
@@ -1338,7 +1346,8 @@ module readvectors (
   assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0]));
   assign ZEn = (Unit == `FMAUNIT);
   
-  unpack unpack(.X, .Y, .Z, .Fmt(ModFmt), .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,
+
+  unpack #(P) unpack(.X, .Y, .Z, .Fmt(ModFmt), .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,
                 .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
                 .XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
                 .XEn, .YEn, .ZEn, .XExpMax, .XPostBox);