Added PLIC and UART tests and new functions to the test library

This commit is contained in:
slmnemo 2022-07-22 07:10:39 -07:00
parent d22587090b
commit df568fd202
4 changed files with 81 additions and 10 deletions

@ -1 +1 @@
Subproject commit e5020bf7b345f8efb96c6c939de3162525b7f545 Subproject commit be67c99bd461742aa1c100bcc0732657faae2230

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@ -1603,9 +1603,9 @@ string wally32i[] = '{
string wally32periph[] = '{ string wally32periph[] = '{
`WALLYTEST, `WALLYTEST,
"rv32i_m/privilege/WALLY-gpio-01", // "rv32i_m/privilege/WALLY-gpio-01",
"rv32i_m/privilege/WALLY-clint-01" // "rv32i_m/privilege/WALLY-clint-01"
// "rv32i_m/privilege/WALLY-plic-01" "rv32i_m/privilege/WALLY-plic-01"
// "rv32i_m/privilege/WALLY-uart-01" // "rv32i_m/privilege/WALLY-uart-01"
}; };

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@ -55,6 +55,8 @@ target_tests_nosim = \
WALLY-status-tw-01 \ WALLY-status-tw-01 \
WALLY-gpio-01 \ WALLY-gpio-01 \
WALLY-clint-01 \ WALLY-clint-01 \
WALLY-plic-01 \
WALLY-uart-01 \
rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))

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@ -954,6 +954,17 @@ read08_test:
// address to read in t3, expected 8 bit value in t4 (unused, but there for your perusal). // address to read in t3, expected 8 bit value in t4 (unused, but there for your perusal).
li t2, 0xBAD // bad value that will be overwritten on good reads. li t2, 0xBAD // bad value that will be overwritten on good reads.
lb t2, 0(t3) lb t2, 0(t3)
andi t2, t2, 0xFF // mask to lower 8 bits
sw t2, 0(t1)
addi t1, t1, 4
addi a6, a6, 4
j test_loop // go to next test case
read04_test:
// address to read in t3, expected 8 bit value in t4 (unused, but there for your perusal).
li t2, 0xBAD // bad value that will be overwritten on good reads.
lb t2, 0(t3)
andi t2, t2, 15 // mask lower 4 bits
sw t2, 0(t1) sw t2, 0(t1)
addi t1, t1, 4 addi t1, t1, 4
addi a6, a6, 4 addi a6, a6, 4
@ -974,6 +985,18 @@ readsip_test: // read the MIP into the signature
j test_loop // go to next test case j test_loop // go to next test case
claim_m_plic_interrupts: // clears one non-pending PLIC interrupt claim_m_plic_interrupts: // clears one non-pending PLIC interrupt
li t2, 0x0C00000C // GPIO priority
li t3, 7
lw t4, 0(t2)
sw t3, 0(t2)
sw t4, -4(sp)
addi sp, sp, -4
li t2, 0x0C000028 // UART priority
li t3, 7
lw t4, 0(t2)
sw t3, 0(t2)
sw t4, -4(sp)
addi sp, sp, -4
li t2, 0x0C002000 li t2, 0x0C002000
li t3, 0x0C200004 li t3, 0x0C200004
li t4, 0xFFF li t4, 0xFFF
@ -982,9 +1005,28 @@ claim_m_plic_interrupts: // clears one non-pending PLIC interrupt
lw t5, 0(t3) // make PLIC claim lw t5, 0(t3) // make PLIC claim
sw t5, 0(t3) // complete claim made sw t5, 0(t3) // complete claim made
sw t6, 0(t2) // restore saved enable status sw t6, 0(t2) // restore saved enable status
li t2, 0x0C00000C // GPIO priority
li t3, 0x0C000028 // UART priority
lw t4, 4(sp) // load stored GPIO and UART priority
lw t5, 0(sp)
addi sp, sp, 8 // restore stack pointer
sw t4, 0(t2)
sw t5, 0(t3)
j test_loop j test_loop
claim_s_plic_interrupts: // clears one non-pending PLIC interrupt claim_s_plic_interrupts: // clears one non-pending PLIC interrupt
li t2, 0x0C00000C // GPIO priority
li t3, 7
lw t4, 0(t2)
sw t3, 0(t2)
sw t4, -4(sp)
addi sp, sp, -4
li t2, 0x0C000028 // UART priority
li t3, 7
lw t4, 0(t2)
sw t3, 0(t2)
sw t4, -4(sp)
addi sp, sp, -4
li t2, 0x0C002080 li t2, 0x0C002080
li t3, 0x0C201004 li t3, 0x0C201004
li t4, 0xFFF li t4, 0xFFF
@ -993,25 +1035,52 @@ claim_s_plic_interrupts: // clears one non-pending PLIC interrupt
lw t5, 0(t3) // make PLIC claim lw t5, 0(t3) // make PLIC claim
sw t5, 0(t3) // complete claim made sw t5, 0(t3) // complete claim made
sw t6, 0(t2) // restore saved enable status sw t6, 0(t2) // restore saved enable status
li t2, 0x0C00000C // GPIO priority
li t3, 0x0C000028 // UART priority
lw t4, 4(sp) // load stored GPIO and UART priority
lw t5, 0(sp)
addi sp, sp, 8 // restore stack pointer
sw t4, 0(t2)
sw t5, 0(t3)
j test_loop
uart_lsr_intr_wait: // waits for interrupts to be ready
li t2, 0x10000002 // IIR
li t4, 0x6
uart_lsr_intr_loop:
lb t3, 0(t2)
andi t3, t3, 0x7
bne t3, t4, uart_lsr_intr_loop
sw t3, 0(t1)
addi t1, t1, 4
addi a6, a6, 4
j test_loop j test_loop
uart_data_wait: uart_data_wait:
li t2, 0x10000005 // LSR li t2, 0x10000005 // LSR
li t3, 0x10000002 // IIR li t3, 0x10000002 // IIR
li a4, 0x61
uart_read_LSR_IIR:
lb t4, 0(t3) // save IIR before potential clear lb t4, 0(t3) // save IIR before potential clear
lb t5, 0(t2) lb t5, 0(t2)
andi t5, t5, 1 // only care if data is ready andi t6, t5, 0x61 // only care if all transmissions are done
li t6, 1 bne a4, t6, uart_read_LSR_IIR
beq t5, t6, uart_data_ready
j uart_data_wait
uart_data_ready: uart_data_ready:
sb t4, 0(t1) li t2, 0
sb t5, 1(t1) sw t2, 0(t1) // clear entry deadbeef from memory
andi t5, t5, 0x9F // mask THRE and TEMT from signature
sb t4, 1(t1) // IIR
sb t5, 0(t1) // LSR
addi t1, t1, 4 addi t1, t1, 4
addi a6, a6, 4 addi a6, a6, 4
j test_loop j test_loop
uart_clearmodemintr:
li t2, 0x10000006
lb t2, 0(t2)
j test_loop
goto_s_mode: goto_s_mode:
// return to address in t3, // return to address in t3,
li a0, 3 // Trap handler behavior (go to supervisor mode) li a0, 3 // Trap handler behavior (go to supervisor mode)