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bus rw bugfix and peripherals testing
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108
wally-pipelined/regression/wally-peripherals.do
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108
wally-pipelined/regression/wally-peripherals.do
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@ -0,0 +1,108 @@
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# wally-peripherals.do
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#
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# Created by Ben Bracker (bbracker@hmc.edu) on 11 Feb. 2021
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#
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# Based on wally-pipelined.do by
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# James Stine, 2008; David Harris 2021
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# Go Cowboys!!!!!!
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# Use this wally-pipelined.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-pipelined.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally-pipelined.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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# create library
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if [file exists work] {
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vdel -all
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}
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vlib work
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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# default to config/rv64ic, but allow this to be overridden at the command line. For example:
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# do wally-pipelined.do ../config/rv32ic
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# That said, I don't think there are any peripherals that use anything but rv64i just yet.
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switch $argc {
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0 {vlog +incdir+../config/rv64ic ../testbench/testbench-peripherals.sv ../src/*/*.sv -suppress 2583}
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1 {vlog +incdir+$1 ../testbench/testbench-peripherals.sv ../src/*/*.sv -suppress 2583}
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}
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt +acc work.testbench -o workopt
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vsim workopt
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view wave
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-- display input and output signals as hexidecimal values
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# Diplays All Signals recursively
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add wave /testbench/clk
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add wave /testbench/reset
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add wave -divider
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add wave /testbench/dut/hart/ebu/IReadF
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add wave /testbench/dut/hart/DataStall
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add wave /testbench/dut/hart/InstrStall
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add wave /testbench/dut/hart/StallF
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add wave /testbench/dut/hart/StallD
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add wave /testbench/dut/hart/FlushD
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add wave /testbench/dut/hart/FlushE
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add wave /testbench/dut/hart/FlushM
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add wave /testbench/dut/hart/FlushW
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add wave -divider
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add wave -hex /testbench/dut/hart/ifu/PCF
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add wave -hex /testbench/dut/hart/ifu/InstrF
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add wave /testbench/InstrFName
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#add wave -hex /testbench/dut/hart/ifu/PCD
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add wave -hex /testbench/dut/hart/ifu/InstrD
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add wave /testbench/InstrDName
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add wave -divider
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#add wave -hex /testbench/dut/hart/ifu/PCE
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#add wave -hex /testbench/dut/hart/ifu/InstrE
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add wave /testbench/InstrEName
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add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
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add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
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add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
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add wave /testbench/dut/hart/ieu/dp/PCSrcE
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add wave -divider
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#add wave -hex /testbench/dut/hart/ifu/PCM
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#add wave -hex /testbench/dut/hart/ifu/InstrM
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add wave /testbench/InstrMName
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add wave /testbench/dut/uncore/dtim/memwrite
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add wave -hex /testbench/dut/uncore/HADDR
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add wave -hex /testbench/dut/uncore/HWDATA
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add wave -divider
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add wave -hex /testbench/dut/hart/ifu/PCW
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add wave /testbench/InstrWName
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add wave /testbench/dut/hart/ieu/dp/RegWriteW
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add wave -hex /testbench/dut/hart/ieu/dp/ResultW
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add wave -hex /testbench/dut/hart/ieu/dp/RdW
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add wave -divider
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add wave -hex /testbench/dut/uncore/uart/u/*
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add wave -divider
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#add ww
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add wave -hex -r /testbench/*
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-- Set Wave Output Items
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TreeUpdate [SetDefaultTree]
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WaveRestoreZoom {0 ps} {100 ps}
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 120
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configure wave -justifyvalue left
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configure wave -signalnamewidth 0
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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set DefaultRadix hexadecimal
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-- Run the Simulation
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run 5000
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#run -all
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#quit
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@ -76,7 +76,6 @@ module uartPC16550D(
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// shift registrs and FIFOs
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logic [9:0] rxshiftreg;
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logic [11:0] txshiftreg;
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logic [10:0] rxfifo[15:0];
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logic [7:0] txfifo[15:0];
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logic [3:0] rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel;
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@ -323,7 +322,7 @@ module uartPC16550D(
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txbitssent <= 0;
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end else if ((txstate == UART_IDLE) && txsrfull) begin // start transmitting
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txstate <= UART_ACTIVE;
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txoversampledcnt <= 0;
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txoversampledcnt <= 1;
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txbitssent <= 0;
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end else if (txbaudpulse & (txstate == UART_ACTIVE)) begin
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txoversampledcnt <= txoversampledcnt + 1;
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@ -366,7 +365,7 @@ module uartPC16550D(
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// registers & FIFO
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always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) begin
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txfifohead <= 0; txfifotail <= 0; txhrfull <= 0; txsrfull <= 0; TXHR <= 0; txsr <= 0;
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txfifohead <= 0; txfifotail <= 0; txhrfull <= 0; txsrfull <= 0; TXHR <= 0; txsr <= 12'hfff;
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end else begin
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if (~MEMWb && A == 3'b000 && ~DLAB) begin // writing transmit holding register or fifo
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if (fifoenabled) begin
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@ -378,19 +377,19 @@ module uartPC16550D(
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end
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$display("UART transmits: %c",Din); // for testbench
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end
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if (txstate == UART_IDLE) // move data into tx shift register if available
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if (fifoenabled)
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if (txstate == UART_IDLE) begin // move data into tx shift register if available
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if (fifoenabled) begin
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if (~txfifoempty) begin
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txsr <= txdata;
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txfifotail <= txfifotail+1;
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txsrfull <= 1;
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end
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else if (txhrfull) begin
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end else if (txhrfull) begin
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txsr <= txdata;
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txhrfull <= 0;
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txsrfull <= 1;
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end
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else if (txstate == UART_DONE) txsrfull <= 0; // done transmitting shift register
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end else if (txstate == UART_DONE) txsrfull <= 0; // done transmitting shift register
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else if (txstate == UART_ACTIVE && txnextbit) txsr <= {txsr[10:0], 1'b1}; // shift txhr
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if (!MEMWb && A == 3'b010) // writes to FIFO control register
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if (Din[2] | ~Din[0]) begin // tx FIFO reste or FIFO disable clears FIFO contents
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@ -58,7 +58,7 @@ module uncore (
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logic HSELTim, HSELCLINT, HSELGPIO, PreHSELUART, HSELUART;
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logic HRESPTim, HRESPCLINT, HRESPGPIO, HRESPUART;
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logic HREADYTim, HREADYCLINT, HREADYGPIO, HREADYUART;
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logic MemRW;
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logic [1:0] MemRW;
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logic [1:0] MemRWtim, MemRWclint, MemRWgpio, MemRWuart;
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logic UARTIntr;// *** will need to tie INTR to an interrupt handler
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305
wally-pipelined/testbench/testbench-peripherals.sv
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305
wally-pipelined/testbench/testbench-peripherals.sv
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@ -0,0 +1,305 @@
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///////////////////////////////////////////
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// testbench-peripherals.sv
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//
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// Written: Ben Bracker (bbracker@hmc.edu) 11 Feb. 2021
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// Based on: testbench-imperas.sv by David Harris
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//
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// Purpose: Wally Testbench and helper modules
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// Applies test programs meant to test peripherals
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// These tests assume the processor itself is already working!
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module testbench();
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logic clk;
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logic reset;
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int test, i, errors, totalerrors;
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logic [31:0] sig32[0:10000];
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logic [`XLEN-1:0] signature[0:10000];
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logic [`XLEN-1:0] testadr;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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logic [`XLEN-1:0] meminit;
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string tests[] = '{
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"peripherals/WALLY-UART", "2000"
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};
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic [31:0] HADDR;
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logic [`AHBW-1:0] HWDATA;
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logic HWRITE;
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logic [2:0] HSIZE;
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logic [2:0] HBURST;
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logic [3:0] HPROT;
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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// pick tests based on modes supported
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// *** actually I no longer support this
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// would need to put this back in if you wanted to test anything other than rv64i
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string signame, memfilename;
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logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
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logic UARTSin, UARTSout;
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// instantiate device to be tested
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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assign HREADYEXT = 1;
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assign HRESPEXT = 0;
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assign HRDATAEXT = 0;
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wallypipelinedsoc dut(.*);
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// Track names of instructions
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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dut.hart.ifu.InstrM, InstrW,
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InstrDName, InstrEName, InstrMName, InstrWName);
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// initialize tests
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initial
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begin
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test = 0;
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totalerrors = 0;
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testadr = 0;
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// fill memory with defined values to reduce Xs in simulation
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if (`XLEN == 32) meminit = 32'hFEDC0123;
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else meminit = 64'hFEDCBA9876543210;
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for (i=0; i<=65535; i = i+1) begin
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//dut.imem.RAM[i] = meminit;
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// dut.uncore.RAM[i] = meminit;
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end
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// read test vectors into memory
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memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
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$readmemh(memfilename, dut.imem.RAM);
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$readmemh(memfilename, dut.uncore.dtim.RAM);
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reset = 1; # 22; reset = 0;
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end
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// generate clock to sequence tests
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always
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begin
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clk = 1; # 5; clk = 0; # 5;
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end
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// check results
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always @(negedge clk)
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begin
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if (dut.hart.priv.EcallFaultM &&
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(dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.hart.ieu.dp.regf.we3 && dut.hart.ieu.dp.regf.a3 == 3 && dut.hart.ieu.dp.regf.wd3 == 1))) begin
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$display("Code ended with ecall with gp = 1");
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#60; // give time for instructions in pipeline to finish
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// clear signature to prevent contamination from previous tests
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for(i=0; i<10000; i=i+1) begin
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sig32[i] = 'bx;
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end
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// read signature, reformat in 64 bits if necessary
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signame = {"../../imperas-riscv-tests/work/", tests[test], ".signature.output"};
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$readmemh(signame, sig32);
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i = 0;
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while (i < 10000) begin
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if (`XLEN == 32) begin
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signature[i] = sig32[i];
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i = i+1;
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end else begin
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signature[i/2] = {sig32[i+1], sig32[i]};
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i = i + 2;
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end
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end
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// Check errors
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i = 0;
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errors = 0;
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if (`XLEN == 32)
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testadr = tests[test+1].atohex()/4;
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else
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testadr = tests[test+1].atohex()/8;
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/* verilator lint_off INFINITELOOP */
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while (signature[i] !== 'bx) begin
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//$display("signature[%h] = %h", i, signature[i]);
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if (signature[i] !== dut.uncore.dtim.RAM[testadr+i]) begin
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if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
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// report errors unless they are garbage at the end of the sim
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// kind of hacky test for garbage right now
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errors = errors+1;
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$display(" Error on test %s result %d: adr = %h sim = %h, signature = %h",
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tests[test], i, (testadr+i)*`XLEN/8, dut.uncore.dtim.RAM[testadr+i], signature[i]);
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end
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end
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i = i + 1;
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end
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/* verilator lint_on INFINITELOOP */
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if (errors == 0) $display("%s succeeded. Brilliant!!!", tests[test]);
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else begin
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$display("%s failed with %d errors. :(", tests[test], errors);
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totalerrors = totalerrors+1;
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end
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test = test + 2;
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if (test == tests.size()) begin
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if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
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else $display("FAIL: %d test programs had errors", totalerrors);
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$stop;
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end
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else begin
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memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
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$readmemh(memfilename, dut.imem.RAM);
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$readmemh(memfilename, dut.uncore.dtim.RAM);
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$display("Read memfile %s", memfilename);
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reset = 1; # 17; reset = 0;
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end
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end
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end
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endmodule
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/* verilator lint_on STMTDLY */
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/* verilator lint_on WIDTH */
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module instrTrackerTB(
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input logic clk, reset, FlushE,
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input logic [31:0] InstrD,
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input logic [31:0] InstrE, InstrM,
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output logic [31:0] InstrW,
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output string InstrDName, InstrEName, InstrMName, InstrWName);
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// stage Instr to Writeback for visualization
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flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
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instrNameDecTB ddec(InstrD, InstrDName);
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instrNameDecTB edec(InstrE, InstrEName);
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instrNameDecTB mdec(InstrM, InstrMName);
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instrNameDecTB wdec(InstrW, InstrWName);
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endmodule
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// decode the instruction name, to help the test bench
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module instrNameDecTB(
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input logic [31:0] instr,
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output string name);
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logic [6:0] op;
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logic [2:0] funct3;
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logic [6:0] funct7;
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logic [11:0] imm;
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assign op = instr[6:0];
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assign funct3 = instr[14:12];
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assign funct7 = instr[31:25];
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assign imm = instr[31:20];
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// it would be nice to add the operands to the name
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// create another variable called decoded
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always_comb
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casez({op, funct3})
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10'b0000000_000: name = "BAD";
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10'b0000011_000: name = "LB";
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10'b0000011_001: name = "LH";
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10'b0000011_010: name = "LW";
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10'b0000011_011: name = "LD";
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10'b0000011_100: name = "LBU";
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10'b0000011_101: name = "LHU";
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10'b0000011_110: name = "LWU";
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10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH";
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else name = "ADDI";
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10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
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else name = "ILLEGAL";
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10'b0010011_010: name = "SLTI";
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10'b0010011_011: name = "SLTIU";
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10'b0010011_100: name = "XORI";
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10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI";
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else if (funct7[6:1] == 6'b010000) name = "SRAI";
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else name = "ILLEGAL";
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10'b0010011_110: name = "ORI";
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10'b0010011_111: name = "ANDI";
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10'b0010111_???: name = "AUIPC";
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10'b0100011_000: name = "SB";
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10'b0100011_001: name = "SH";
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10'b0100011_010: name = "SW";
|
||||
10'b0100011_011: name = "SD";
|
||||
10'b0011011_000: name = "ADDIW";
|
||||
10'b0011011_001: name = "SLLIW";
|
||||
10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW";
|
||||
else if (funct7 == 7'b0100000) name = "SRAIW";
|
||||
else name = "ILLEGAL";
|
||||
10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW";
|
||||
else if (funct7 == 7'b0100000) name = "SUBW";
|
||||
else name = "ILLEGAL";
|
||||
10'b0111011_001: name = "SLLW";
|
||||
10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW";
|
||||
else if (funct7 == 7'b0100000) name = "SRAW";
|
||||
else name = "ILLEGAL";
|
||||
10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD";
|
||||
else if (funct7 == 7'b0000001) name = "MUL";
|
||||
else if (funct7 == 7'b0100000) name = "SUB";
|
||||
else name = "ILLEGAL";
|
||||
10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL";
|
||||
else if (funct7 == 7'b0000001) name = "MULH";
|
||||
else name = "ILLEGAL";
|
||||
10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT";
|
||||
else if (funct7 == 7'b0000001) name = "MULHSU";
|
||||
else name = "ILLEGAL";
|
||||
10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU";
|
||||
else if (funct7 == 7'b0000001) name = "DIV";
|
||||
else name = "ILLEGAL";
|
||||
10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR";
|
||||
else if (funct7 == 7'b0000001) name = "MUL";
|
||||
else name = "ILLEGAL";
|
||||
10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
|
||||
else if (funct7 == 7'b0000001) name = "DIVU";
|
||||
else if (funct7 == 7'b0100000) name = "SRA";
|
||||
else name = "ILLEGAL";
|
||||
10'b0110011_110: if (funct7 == 7'b0000000) name = "OR";
|
||||
else if (funct7 == 7'b0000001) name = "REM";
|
||||
else name = "ILLEGAL";
|
||||
10'b0110011_111: if (funct7 == 7'b0000000) name = "AND";
|
||||
else if (funct7 == 7'b0000001) name = "REMU";
|
||||
else name = "ILLEGAL";
|
||||
10'b0110111_???: name = "LUI";
|
||||
10'b1100011_000: name = "BEQ";
|
||||
10'b1100011_001: name = "BNE";
|
||||
10'b1100011_100: name = "BLT";
|
||||
10'b1100011_101: name = "BGE";
|
||||
10'b1100011_110: name = "BLTU";
|
||||
10'b1100011_111: name = "BGEU";
|
||||
10'b1100111_000: name = "JALR";
|
||||
10'b1101111_???: name = "JAL";
|
||||
10'b1110011_000: if (imm == 0) name = "ECALL";
|
||||
else if (imm == 1) name = "EBREAK";
|
||||
else if (imm == 2) name = "URET";
|
||||
else if (imm == 258) name = "SRET";
|
||||
else if (imm == 770) name = "MRET";
|
||||
else name = "ILLEGAL";
|
||||
10'b1110011_001: name = "CSRRW";
|
||||
10'b1110011_010: name = "CSRRS";
|
||||
10'b1110011_011: name = "CSRRC";
|
||||
10'b1110011_101: name = "CSRRWI";
|
||||
10'b1110011_110: name = "CSRRSI";
|
||||
10'b1110011_111: name = "CSRRCI";
|
||||
10'b0001111_???: name = "FENCE";
|
||||
default: name = "ILLEGAL";
|
||||
endcase
|
||||
endmodule
|
Loading…
Reference in New Issue
Block a user