diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc
index c11d69a17..30cba8cc5 100644
--- a/fpga/constraints/constraints-ArtyA7.xdc
+++ b/fpga/constraints/constraints-ArtyA7.xdc
@@ -42,8 +42,8 @@ set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [g
# *** IOSTANDARD is probably wrong
set_property PACKAGE_PIN A9 [get_ports UARTSin]
set_property PACKAGE_PIN D10 [get_ports UARTSout]
-set_max_delay -from [get_ports UARTSin] 10.000
-set_max_delay -to [get_ports UARTSout] 10.000
+set_max_delay -from [get_ports UARTSin] 14.000
+set_max_delay -to [get_ports UARTSout] 14.000
set_property IOSTANDARD LVCMOS33 [get_ports UARTSin]
set_property IOSTANDARD LVCMOS33 [get_ports UARTSout]
set_property DRIVE 4 [get_ports UARTSout]
diff --git a/fpga/generator/xlnx_ddr3-artya7-mig.prj b/fpga/generator/xlnx_ddr3-artya7-mig.prj
index d53a20691..32905a5b4 100644
--- a/fpga/generator/xlnx_ddr3-artya7-mig.prj
+++ b/fpga/generator/xlnx_ddr3-artya7-mig.prj
@@ -65,57 +65,57 @@
14
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- 1.5V
+ 1.35V
BANK_ROW_COLUMN
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diff --git a/fpga/src/fpgaTopArtyA7.v b/fpga/src/fpgaTopArtyA7.v
index 352d07ccf..c682bca88 100644
--- a/fpga/src/fpgaTopArtyA7.v
+++ b/fpga/src/fpgaTopArtyA7.v
@@ -416,7 +416,6 @@ module fpgaTop
.ddr3_dm(ddr3_dm),
.ddr3_odt(ddr3_odt),
- // clocks. I still don't understand why this needs two?
.sys_clk_i(clk167),
.clk_ref_i(clk200),