mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm.
One downside is it increases the icache complexity. However it also fixes an untested bug. If a region was uncacheable it would have been possible for the request to be made multiple times. Now that is not possible. Additionally spills were oscillating between the spill hit states without this change. The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits.
This commit is contained in:
Ross Thompson
parent
62d91e9ea1
commit
de9e234ffa
@ -16,41 +16,41 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate /testbench/dut/hart/ieu/dp/ResultM
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add wave -noupdate /testbench/dut/hart/ieu/dp/ResultM
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add wave -noupdate /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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@ -98,11 +98,12 @@ add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/if
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/icache/FinalInstrRawF
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add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -group {instruction pipeline} /testbench/InstrW
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
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add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrW
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
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@ -160,12 +161,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
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add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group PCS /testbench/dut/hart/PCF
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
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add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
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add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
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add wave -noupdate -group PCS /testbench/dut/hart/PCE
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
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add wave -noupdate -group PCS /testbench/dut/hart/PCM
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
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add wave -noupdate -group PCS /testbench/PCW
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add wave -noupdate -expand -group PCS /testbench/PCW
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
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@ -185,7 +186,7 @@ add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
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add wave -noupdate -expand -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
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@ -193,6 +194,8 @@ add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLine
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add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/icachemem/word[0]/CacheDataMem/Addr}
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add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/icachemem/word[0]/CacheDataMem/Addr}
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add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/icachemem/word[0]/CacheDataMem/WriteData}
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add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/icachemem/word[0]/CacheDataMem/WriteData}
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add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/icachemem/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/icachemem/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/PCNextIndexF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
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@ -456,16 +459,38 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
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add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset0
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add wave -noupdate -color Gold /testbench/dut/hart/lsu/dcache/subwordread/offset0
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset1
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset1
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset2
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset2
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset3
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add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset3
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add wave -noupdate /testbench/dut/hart/ExceptionM
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add wave -noupdate /testbench/dut/hart/ExceptionM
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add wave -noupdate /testbench/dut/hart/PendingInterruptM
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add wave -noupdate /testbench/dut/hart/PendingInterruptM
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add wave -noupdate /testbench/dut/hart/TrapM
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add wave -noupdate /testbench/dut/hart/TrapM
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add wave -noupdate /testbench/dut/hart/ifu/icache/CompressedF
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add wave -noupdate /testbench/dut/hart/ifu/icache/PCPF
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add wave -noupdate /testbench/dut/hart/ifu/PCPFmmu
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add wave -noupdate /testbench/dut/hart/ifu/PCPF
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add wave -noupdate /testbench/dut/hart/ifu/PCF
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add wave -noupdate /testbench/dut/hart/ifu/immu/Translate
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add wave -noupdate /testbench/dut/hart/ifu/icache/FinalInstrRawF
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add wave -noupdate /testbench/dut/hart/ifu/icache/StallF
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add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheMemReadData
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add wave -noupdate {/testbench/dut/hart/ifu/icache/icachemem/word[0]/CacheDataMem/Addr}
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add wave -noupdate {/testbench/dut/hart/ifu/icache/icachemem/word[0]/CacheDataMem/ReadData}
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add wave -noupdate {/testbench/dut/hart/ifu/icache/icachemem/word[1]/CacheDataMem/Addr}
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add wave -noupdate {/testbench/dut/hart/ifu/icache/icachemem/word[1]/CacheDataMem/ReadData}
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add wave -noupdate {/testbench/dut/hart/ifu/icache/icachemem/word[2]/CacheDataMem/Addr}
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add wave -noupdate {/testbench/dut/hart/ifu/icache/icachemem/word[2]/CacheDataMem/ReadData}
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add wave -noupdate {/testbench/dut/hart/ifu/icache/icachemem/word[3]/CacheDataMem/Addr}
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add wave -noupdate {/testbench/dut/hart/ifu/icache/icachemem/word[3]/CacheDataMem/ReadData}
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add wave -noupdate /testbench/dut/hart/ifu/icache/icachemem/WayHit
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add wave -noupdate /testbench/dut/hart/ifu/icache/PCTagF
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add wave -noupdate /testbench/dut/hart/ifu/icache/PCPSpillF
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add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheReadEn
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add wave -noupdate /testbench/dut/hart/ifu/icache/PCMux_q
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TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 6} {32245 ns} 0} {{Cursor 2} {176 ns} 0} {{Cursor 3} {25666 ns} 0} {{Cursor 4} {2221 ns} 0}
|
WaveRestoreCursors {{Cursor 6} {53451 ns} 0}
|
||||||
quietly wave cursor active 2
|
quietly wave cursor active 1
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 297
|
configure wave -valuecolwidth 297
|
||||||
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
||||||
@ -480,4 +505,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {0 ns} {1124571 ns}
|
WaveRestoreZoom {53011 ns} {53891 ns}
|
||||||
|
|||||||
@ -9,7 +9,7 @@ should continue.
|
|||||||
It is important to note ITLB misses and faults DO NOT flush a memory operation
|
It is important to note ITLB misses and faults DO NOT flush a memory operation
|
||||||
in the memory stage. This is the core reason for the complexity.
|
in the memory stage. This is the core reason for the complexity.
|
||||||
|
|
||||||
| Type | ITLB miss | DTLB miss | mem op | |
|
| Type | ITLB miss | DTLB miss | mem op | |
|
||||||
|-------+-----------+-----------+--------+--------------|
|
|-------+-----------+-----------+--------+--------------|
|
||||||
| 0 | 0 | 0 | 0 | |
|
| 0 | 0 | 0 | 0 | |
|
||||||
| 1 | 0 | 0 | 1 | |
|
| 1 | 0 | 0 | 1 | |
|
||||||
|
|||||||
3
wally-pipelined/src/cache/icache.sv
vendored
3
wally-pipelined/src/cache/icache.sv
vendored
@ -109,7 +109,7 @@ module icache
|
|||||||
assign PCPSpillF = PCPF + {{{PA_WIDTH}{1'b0}}, 2'b10}; // *** modelsim does not allow the use of PA_BITS for literal width.
|
assign PCPSpillF = PCPF + {{{PA_WIDTH}{1'b0}}, 2'b10}; // *** modelsim does not allow the use of PA_BITS for literal width.
|
||||||
|
|
||||||
// now we have to select between these three PCs
|
// now we have to select between these three PCs
|
||||||
assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf, but it is necessary
|
assign PCPreFinalF = PCMux[0] ? PCPF : PCNextF; // *** don't like the stallf, but it is necessary
|
||||||
// for the data cache i used a cpu busy state which is triggered by StallW. In the case of the icache I
|
// for the data cache i used a cpu busy state which is triggered by StallW. In the case of the icache I
|
||||||
// modified the select on this address mux. Both are not ideal; however the cpu_busy state is required for the
|
// modified the select on this address mux. Both are not ideal; however the cpu_busy state is required for the
|
||||||
// dcache as a write would repeatedly update the sram or worse for an uncached write multiple times.
|
// dcache as a write would repeatedly update the sram or worse for an uncached write multiple times.
|
||||||
@ -243,6 +243,7 @@ module icache
|
|||||||
icachefsm #(.BLOCKLEN(BLOCKLEN))
|
icachefsm #(.BLOCKLEN(BLOCKLEN))
|
||||||
controller(.clk,
|
controller(.clk,
|
||||||
.reset,
|
.reset,
|
||||||
|
.StallF,
|
||||||
.ICacheReadEn,
|
.ICacheReadEn,
|
||||||
.ICacheMemWriteEnable,
|
.ICacheMemWriteEnable,
|
||||||
.ICacheStallF,
|
.ICacheStallF,
|
||||||
|
|||||||
90
wally-pipelined/src/cache/icachefsm.sv
vendored
90
wally-pipelined/src/cache/icachefsm.sv
vendored
@ -30,6 +30,8 @@ module icachefsm #(parameter BLOCKLEN = 256)
|
|||||||
// Inputs from pipeline
|
// Inputs from pipeline
|
||||||
input logic clk, reset,
|
input logic clk, reset,
|
||||||
|
|
||||||
|
input logic StallF,
|
||||||
|
|
||||||
// inputs from mmu
|
// inputs from mmu
|
||||||
input logic ITLBMissF,
|
input logic ITLBMissF,
|
||||||
input logic ITLBWriteF,
|
input logic ITLBWriteF,
|
||||||
@ -88,7 +90,8 @@ module icachefsm #(parameter BLOCKLEN = 256)
|
|||||||
|
|
||||||
STATE_MISS_FETCH_WDV, // aligned miss, issue read to AHB and wait for data.
|
STATE_MISS_FETCH_WDV, // aligned miss, issue read to AHB and wait for data.
|
||||||
STATE_MISS_FETCH_DONE, // write data into SRAM/LUT
|
STATE_MISS_FETCH_DONE, // write data into SRAM/LUT
|
||||||
STATE_MISS_READ, // read block 1 from SRAM/LUT
|
STATE_MISS_READ, // read block 1 from SRAM/LUT
|
||||||
|
STATE_MISS_READ_DELAY, // read block 1 from SRAM/LUT
|
||||||
|
|
||||||
STATE_MISS_SPILL_FETCH_WDV, // spill, miss on block 0, issue read to AHB and wait
|
STATE_MISS_SPILL_FETCH_WDV, // spill, miss on block 0, issue read to AHB and wait
|
||||||
STATE_MISS_SPILL_FETCH_DONE, // write data into SRAM/LUT
|
STATE_MISS_SPILL_FETCH_DONE, // write data into SRAM/LUT
|
||||||
@ -104,7 +107,10 @@ module icachefsm #(parameter BLOCKLEN = 256)
|
|||||||
|
|
||||||
STATE_INVALIDATE, // *** not sure if invalidate or evict? invalidate by cache block or address?
|
STATE_INVALIDATE, // *** not sure if invalidate or evict? invalidate by cache block or address?
|
||||||
STATE_TLB_MISS,
|
STATE_TLB_MISS,
|
||||||
STATE_TLB_MISS_DONE
|
STATE_TLB_MISS_DONE,
|
||||||
|
|
||||||
|
STATE_CPU_BUSY,
|
||||||
|
STATE_CPU_BUSY_SPILL
|
||||||
} statetype;
|
} statetype;
|
||||||
|
|
||||||
statetype CurrState, NextState;
|
statetype CurrState, NextState;
|
||||||
@ -138,7 +144,12 @@ module icachefsm #(parameter BLOCKLEN = 256)
|
|||||||
end else if (hit & ~spill) begin
|
end else if (hit & ~spill) begin
|
||||||
SavePC = 1'b1;
|
SavePC = 1'b1;
|
||||||
ICacheStallF = 1'b0;
|
ICacheStallF = 1'b0;
|
||||||
NextState = STATE_READY;
|
if(StallF) begin
|
||||||
|
NextState = STATE_CPU_BUSY;
|
||||||
|
PCMux = 2'b01;
|
||||||
|
end else begin
|
||||||
|
NextState = STATE_READY;
|
||||||
|
end
|
||||||
end else if (hit & spill) begin
|
end else if (hit & spill) begin
|
||||||
spillSave = 1'b1;
|
spillSave = 1'b1;
|
||||||
PCMux = 2'b10;
|
PCMux = 2'b10;
|
||||||
@ -151,7 +162,12 @@ module icachefsm #(parameter BLOCKLEN = 256)
|
|||||||
PCMux = 2'b01;
|
PCMux = 2'b01;
|
||||||
NextState = STATE_MISS_SPILL_FETCH_WDV;
|
NextState = STATE_MISS_SPILL_FETCH_WDV;
|
||||||
end else begin
|
end else begin
|
||||||
NextState = STATE_READY;
|
if(StallF) begin
|
||||||
|
NextState = STATE_CPU_BUSY;
|
||||||
|
PCMux = 2'b01;
|
||||||
|
end else begin
|
||||||
|
NextState = STATE_READY;
|
||||||
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
// branch 1, hit spill and 2, miss spill hit
|
// branch 1, hit spill and 2, miss spill hit
|
||||||
@ -192,8 +208,14 @@ module icachefsm #(parameter BLOCKLEN = 256)
|
|||||||
PCMux = 2'b00;
|
PCMux = 2'b00;
|
||||||
UnalignedSelect = 1'b1;
|
UnalignedSelect = 1'b1;
|
||||||
SavePC = 1'b1;
|
SavePC = 1'b1;
|
||||||
NextState = STATE_READY;
|
ICacheStallF = 1'b0;
|
||||||
ICacheStallF = 1'b0;
|
if(StallF) begin
|
||||||
|
NextState = STATE_CPU_BUSY_SPILL;
|
||||||
|
PCMux = 2'b10;
|
||||||
|
end else begin
|
||||||
|
NextState = STATE_READY;
|
||||||
|
end
|
||||||
|
|
||||||
end
|
end
|
||||||
// branch 3 miss no spill
|
// branch 3 miss no spill
|
||||||
STATE_MISS_FETCH_WDV: begin
|
STATE_MISS_FETCH_WDV: begin
|
||||||
@ -214,7 +236,19 @@ module icachefsm #(parameter BLOCKLEN = 256)
|
|||||||
STATE_MISS_READ: begin
|
STATE_MISS_READ: begin
|
||||||
PCMux = 2'b01;
|
PCMux = 2'b01;
|
||||||
ICacheReadEn = 1'b1;
|
ICacheReadEn = 1'b1;
|
||||||
NextState = STATE_READY;
|
NextState = STATE_MISS_READ_DELAY;
|
||||||
|
end
|
||||||
|
STATE_MISS_READ_DELAY: begin
|
||||||
|
//PCMux = 2'b01;
|
||||||
|
ICacheReadEn = 1'b1;
|
||||||
|
ICacheStallF = 1'b0;
|
||||||
|
if(StallF) begin
|
||||||
|
PCMux = 2'b01;
|
||||||
|
NextState = STATE_CPU_BUSY;
|
||||||
|
PCMux = 2'b01;
|
||||||
|
end else begin
|
||||||
|
NextState = STATE_READY;
|
||||||
|
end
|
||||||
end
|
end
|
||||||
// branch 4 miss spill hit, and 5 miss spill miss
|
// branch 4 miss spill hit, and 5 miss spill miss
|
||||||
STATE_MISS_SPILL_FETCH_WDV: begin
|
STATE_MISS_SPILL_FETCH_WDV: begin
|
||||||
@ -249,12 +283,17 @@ module icachefsm #(parameter BLOCKLEN = 256)
|
|||||||
CntReset = 1'b1;
|
CntReset = 1'b1;
|
||||||
NextState = STATE_MISS_SPILL_MISS_FETCH_WDV;
|
NextState = STATE_MISS_SPILL_MISS_FETCH_WDV;
|
||||||
end else begin
|
end else begin
|
||||||
NextState = STATE_READY;
|
|
||||||
ICacheReadEn = 1'b1;
|
ICacheReadEn = 1'b1;
|
||||||
PCMux = 2'b00;
|
PCMux = 2'b00;
|
||||||
UnalignedSelect = 1'b1;
|
UnalignedSelect = 1'b1;
|
||||||
SavePC = 1'b1;
|
SavePC = 1'b1;
|
||||||
ICacheStallF = 1'b0;
|
ICacheStallF = 1'b0;
|
||||||
|
if(StallF) begin
|
||||||
|
NextState = STATE_CPU_BUSY;
|
||||||
|
PCMux = 2'b01;
|
||||||
|
end else begin
|
||||||
|
NextState = STATE_READY;
|
||||||
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
STATE_MISS_SPILL_MISS_FETCH_WDV: begin
|
STATE_MISS_SPILL_MISS_FETCH_WDV: begin
|
||||||
@ -284,7 +323,12 @@ module icachefsm #(parameter BLOCKLEN = 256)
|
|||||||
UnalignedSelect = 1'b1;
|
UnalignedSelect = 1'b1;
|
||||||
SavePC = 1'b1;
|
SavePC = 1'b1;
|
||||||
ICacheStallF = 1'b0;
|
ICacheStallF = 1'b0;
|
||||||
NextState = STATE_READY;
|
if(StallF) begin
|
||||||
|
NextState = STATE_CPU_BUSY;
|
||||||
|
PCMux = 2'b01;
|
||||||
|
end else begin
|
||||||
|
NextState = STATE_READY;
|
||||||
|
end
|
||||||
end
|
end
|
||||||
STATE_TLB_MISS: begin
|
STATE_TLB_MISS: begin
|
||||||
if (WalkerInstrPageFaultF) begin
|
if (WalkerInstrPageFaultF) begin
|
||||||
@ -297,8 +341,34 @@ module icachefsm #(parameter BLOCKLEN = 256)
|
|||||||
end
|
end
|
||||||
end
|
end
|
||||||
STATE_TLB_MISS_DONE: begin
|
STATE_TLB_MISS_DONE: begin
|
||||||
|
PCMux = 2'b01;
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
end
|
end
|
||||||
|
STATE_CPU_BUSY: begin
|
||||||
|
ICacheStallF = 1'b0;
|
||||||
|
if (ITLBMissF) begin
|
||||||
|
NextState = STATE_TLB_MISS;
|
||||||
|
end else if(StallF) begin
|
||||||
|
NextState = STATE_CPU_BUSY;
|
||||||
|
PCMux = 2'b01;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
NextState = STATE_READY;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
STATE_CPU_BUSY_SPILL: begin
|
||||||
|
ICacheStallF = 1'b0;
|
||||||
|
ICacheReadEn = 1'b1;
|
||||||
|
if (ITLBMissF) begin
|
||||||
|
NextState = STATE_TLB_MISS;
|
||||||
|
end else if(StallF) begin
|
||||||
|
NextState = STATE_CPU_BUSY_SPILL;
|
||||||
|
PCMux = 2'b10;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
NextState = STATE_READY;
|
||||||
|
end
|
||||||
|
end
|
||||||
default: begin
|
default: begin
|
||||||
PCMux = 2'b01;
|
PCMux = 2'b01;
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user