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Cleaned up synthesis warnings

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This commit is contained in:
David Harris 2022-02-11 01:15:16 +00:00
parent cd243a965f
commit de5e80696d
10 changed files with 12 additions and 18 deletions
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2
pipelined/src/cache/cachefsm.sv vendored
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@ -86,7 +86,7 @@ module cachefsm
logic DoAMOMiss, DoReadMiss, DoWriteMiss; logic DoAMOMiss, DoReadMiss, DoWriteMiss;
logic FlushFlag; logic FlushFlag;
typedef enum {STATE_READY, typedef enum logic [3:0] {STATE_READY,
STATE_MISS_FETCH_WDV, STATE_MISS_FETCH_WDV,
STATE_MISS_FETCH_DONE, STATE_MISS_FETCH_DONE,

9
pipelined/src/ebu/ahblite.sv
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@ -35,10 +35,6 @@
`include "wally-config.vh" `include "wally-config.vh"
package ahbliteState;
typedef enum logic [3:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype;
endpackage
module ahblite ( module ahblite (
input logic clk, reset, input logic clk, reset,
// Load control // Load control
@ -75,6 +71,9 @@ module ahblite (
(* mark_debug = "true" *) output logic HWRITED (* mark_debug = "true" *) output logic HWRITED
); );
typedef enum logic [1:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype;
statetype BusState, NextBusState;
logic GrantData; logic GrantData;
logic [31:0] AccessAddress; logic [31:0] AccessAddress;
logic [2:0] ISize; logic [2:0] ISize;
@ -88,8 +87,6 @@ module ahblite (
// Data accesses have priority over instructions. However, if a data access comes // Data accesses have priority over instructions. However, if a data access comes
// while an instruction read is occuring, the instruction read finishes before // while an instruction read is occuring, the instruction read finishes before
// the data access can take place. // the data access can take place.
import ahbliteState::*;
statetype BusState, NextBusState;
flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState); flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState);

2
pipelined/src/ieu/controller.sv
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@ -228,5 +228,5 @@ module controller(
assign CSRWritePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM; assign CSRWritePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM;
assign StoreStallD = MemRWE[0] & (|MemRWD | |AtomicD); assign StoreStallD = MemRWE[0] & ((|MemRWD) | (|AtomicD));
endmodule endmodule

2
pipelined/src/ifu/spillsupport.sv
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@ -64,7 +64,7 @@ module spillsupport (
assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1]; assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
typedef enum {STATE_SPILL_READY, STATE_SPILL_SPILL} statetype; typedef enum logic [1:0] {STATE_SPILL_READY, STATE_SPILL_SPILL} statetype;
(* mark_debug = "true" *) statetype CurrState, NextState; (* mark_debug = "true" *) statetype CurrState, NextState;
always_ff @(posedge clk) always_ff @(posedge clk)

2
pipelined/src/lsu/busfsm.sv
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@ -64,7 +64,7 @@ module busfsm #(parameter integer WordCountThreshold,
logic UnCachedAccess; logic UnCachedAccess;
typedef enum {STATE_BUS_READY, typedef enum logic [2:0] {STATE_BUS_READY,
STATE_BUS_FETCH, STATE_BUS_FETCH,
STATE_BUS_WRITE, STATE_BUS_WRITE,
STATE_BUS_UNCACHED_WRITE, STATE_BUS_UNCACHED_WRITE,

2
pipelined/src/lsu/interlockfsm.sv
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@ -49,7 +49,7 @@ module interlockfsm
output logic IgnoreRequestTrapM); output logic IgnoreRequestTrapM);
typedef enum {STATE_T0_READY, typedef enum logic[2:0] {STATE_T0_READY,
STATE_T0_REPLAY, STATE_T0_REPLAY,
STATE_T3_DTLB_MISS, STATE_T3_DTLB_MISS,
STATE_T4_ITLB_MISS, STATE_T4_ITLB_MISS,

2
pipelined/src/mmu/hptw.sv
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@ -46,7 +46,7 @@ module hptw
output logic [2:0] HPTWSize // 32 or 64 bit access. output logic [2:0] HPTWSize // 32 or 64 bit access.
); );
typedef enum {L0_ADR, L0_RD, typedef enum logic [3:0] {L0_ADR, L0_RD,
L1_ADR, L1_RD, L1_ADR, L1_RD,
L2_ADR, L2_RD, L2_ADR, L2_RD,
L3_ADR, L3_RD, L3_ADR, L3_RD,

2
pipelined/src/uncore/uartPC16550D.sv
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@ -55,7 +55,7 @@ module uartPC16550D(
); );
// transmit and receive states // *** neeed to work on synth warning -- it wants to make enums 32 bits by default // transmit and receive states // *** neeed to work on synth warning -- it wants to make enums 32 bits by default
typedef enum {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype; typedef enum logic [1:0] {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
// Registers // Registers
logic [10:0] RBR; logic [10:0] RBR;

4
synthDC/.synopsys_dc.setup
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@ -12,10 +12,10 @@ if { [info exists ::env(RISCV)] } {
} }
if {$tech == "sky130"} { if {$tech == "sky130"} {
set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib/ set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib
lappend search_path $s8lib lappend search_path $s8lib
} elseif {$tech == "sky90"} { } elseif {$tech == "sky90"} {
set s9lib $timing_lib/sky90/tech_files/ set s9lib $timing_lib/sky90/sky90_sc/V1.7.4/lib
lappend search_path $s9lib lappend search_path $s9lib
} }

3
synthDC/scripts/synth.tcl
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@ -3,7 +3,6 @@
# james.stine@okstate.edu 27 Sep 2015 # james.stine@okstate.edu 27 Sep 2015
# #
<<<<<<< HEAD
# Ignore unnecessary warnings: # Ignore unnecessary warnings:
# intraassignment delays for nonblocking assignments are ignored # intraassignment delays for nonblocking assignments are ignored
suppress_message {VER-130} suppress_message {VER-130}
@ -11,8 +10,6 @@ suppress_message {VER-130}
suppress_message {VER-281} suppress_message {VER-281}
suppress_message {VER-173} suppress_message {VER-173}
=======
>>>>>>> 524ba78808f28905d48c866eec9f8e7badd42ea8
# get outputDir from environment (Makefile) # get outputDir from environment (Makefile)
set outputDir $::env(OUTPUTDIR) set outputDir $::env(OUTPUTDIR)
set cfgName $::env(CONFIG) set cfgName $::env(CONFIG)