diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 07eab1ae5..480575aa6 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -316,7 +316,7 @@ connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/core/hzu/IF create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe61] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61] -connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FStallD ]] +connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FPUStallD ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe62] diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index 8dff84a49..f39a9bce9 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -1,13 +1,13 @@ dst := IP # vcu118 -#export XILINX_PART := xcvu9p-flga2104-2L-e -#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 -#export board := vcu118 +export XILINX_PART := xcvu9p-flga2104-2L-e +export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 +export board := vcu118 # vcu108 -export XILINX_PART := xcvu095-ffva2104-2-e -export XILINX_BOARD := xilinx.com:vcu108:part0:1.2 -export board := vcu108 +#export XILINX_PART := xcvu095-ffva2104-2-e +#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2 +#export board := vcu108 all: FPGA diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index ca82c4f87..8190b3178 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -127,10 +127,10 @@ module fdivsqrtpostproc( always_comb if (RemOpM) begin - NormShiftM = (m + (`DIVBLEN)'(`DIVa)); + NormShiftM = (m + (`DIVBLEN+1)'(`DIVa)); PreResultM = IntRemM; end else begin - NormShiftM = ((`DIVBLEN)'(`DIVb) - (n << `LOGR)); + NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (n << `LOGR)); PreResultM = {3'b000, IntQuotM}; end diff --git a/pipelined/src/fpu/fma/fma.sv b/pipelined/src/fpu/fma/fma.sv index 6a872d6d5..ce42aaa19 100644 --- a/pipelined/src/fpu/fma/fma.sv +++ b/pipelined/src/fpu/fma/fma.sv @@ -37,9 +37,7 @@ module fma( input logic XZero, YZero, ZZero, // is the input zero input logic [2:0] OpCtrl, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y) input logic [`FMTBITS-1:0] Fmt, // format of the result single double half or quad - output logic [`NE+1:0] Pe, // the product's exponent B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign output logic ZmSticky, // sticky bit that is calculated during alignment - output logic KillProd, // set the product to zero before addition if the product is too small to matter output logic [3*`NF+5:0] Sm, // the positive sum's significand output logic InvA, // Was A inverted for effective subtraction (P-A or -P+A) output logic As, // the aligned addend's sign (modified Z sign for other opperations) @@ -47,12 +45,15 @@ module fma( output logic Ss, // the sum's sign output logic [`NE+1:0] Se, output logic [$clog2(3*`NF+7)-1:0] SCnt // normalization shift count - ); +); logic [2*`NF+1:0] Pm; // the product's significand in U(2.2Nf) format logic [3*`NF+5:0] Am; // addend aligned's mantissa for addition in U(NF+5.2NF+1) logic [3*`NF+5:0] AmInv; // aligned addend's mantissa possibly inverted logic [2*`NF+1:0] PmKilled; // the product's mantissa possibly killed + logic KillProd; // set the product to zero before addition if the product is too small to matter + logic [`NE+1:0] Pe; // the product's exponent B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign + /////////////////////////////////////////////////////////////////////////////// // Calculate the product // - When multipliying two fp numbers, add the exponents diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index c264cff3a..afa645cde 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -108,10 +108,8 @@ module fpu ( // Fma Signals logic [3*`NF+5:0] SmE, SmM; - logic [`NE+1:0] PeE, PeM; logic ZmStickyE, ZmStickyM; logic [`NE+1:0] SeE,SeM; - logic KillProdE, KillProdM; logic InvAE, InvAM; logic AsE, AsM; logic PsE, PsM; @@ -256,9 +254,9 @@ module fpu ( .XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), .OpCtrl(OpCtrlE), .Fmt(FmtE), .As(AsE), .Ps(PsE), .Ss(SsE), .Se(SeE), - .Sm(SmE), .Pe(PeE), + .Sm(SmE), .InvA(InvAE), .SCnt(SCntE), - .ZmSticky(ZmStickyE), .KillProd(KillProdE)); + .ZmSticky(ZmStickyE)); // divide and squareroot // - fdiv @@ -353,10 +351,9 @@ module fpu ( {XsM, YsM, XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM, ZDenormM}); flopenrc #(1) EMRegCmpFlg (clk, reset, FlushM, ~StallM, PreNVE, PreNVM); flopenrc #(3*`NF+6) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM); - flopenrc #(`NE+2) EMRegFma3(clk, reset, FlushM, ~StallM, PeE, PeM); - flopenrc #($clog2(3*`NF+7)+8+`NE) EMRegFma4(clk, reset, FlushM, ~StallM, - {ZmStickyE, KillProdE, InvAE, SCntE, AsE, PsE, SsE, SeE}, - {ZmStickyM, KillProdM, InvAM, SCntM, AsM, PsM, SsM, SeM}); + flopenrc #($clog2(3*`NF+7)+7+`NE) EMRegFma4(clk, reset, FlushM, ~StallM, + {ZmStickyE, InvAE, SCntE, AsE, PsE, SsE, SeE}, + {ZmStickyM, InvAM, SCntM, AsM, PsM, SsM, SeM}); flopenrc #(`NE+`LOGCVTLEN+`CVTLEN+4) EMRegCvt(clk, reset, FlushM, ~StallM, {CeE, CvtShiftAmtE, CvtResDenormUfE, CsE, IntZeroE, CvtLzcInE}, {CeM, CvtShiftAmtM, CvtResDenormUfM, CsM, IntZeroM, CvtLzcInM}); @@ -375,8 +372,8 @@ module fpu ( assign FpLoadStoreM = FResSelM[1]; - postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), .FmaPe(PeM), - .FmaZmS(ZmStickyM), .FmaKillProd(KillProdM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM), + postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), + .FmaZmS(ZmStickyM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM), .ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SmM), .DivQe(QeM), /*.DivDone(DivDoneM), */ .ZDenorm(ZDenormM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM), .CvtCe(CeM), .CvtResDenormUf(CvtResDenormUfM),.CvtShiftAmt(CvtShiftAmtM), .CvtCs(CsM), .ToInt(FWriteIntM), .DivS(DivSM), diff --git a/pipelined/src/fpu/postproc/fmashiftcalc.sv b/pipelined/src/fpu/postproc/fmashiftcalc.sv index 03209ca9b..ce9ff79b1 100644 --- a/pipelined/src/fpu/postproc/fmashiftcalc.sv +++ b/pipelined/src/fpu/postproc/fmashiftcalc.sv @@ -32,10 +32,8 @@ module fmashiftcalc( input logic [3*`NF+5:0] FmaSm, // the positive sum input logic [`NE-1:0] Ze, // exponent of Z - input logic [`NE+1:0] FmaPe, // X exponent + Y exponent - bias input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // normalization shift count input logic [`FMTBITS-1:0] Fmt, // precision 1 = double 0 = single - input logic FmaKillProd, // is the product set to zero input logic [`NE+1:0] FmaSe, output logic [`NE+1:0] NormSumExp, // exponent of the normalized sum not taking into account denormal or zero results output logic FmaSZero, // is the result denormalized - calculated before LZA corection diff --git a/pipelined/src/fpu/postproc/postprocess.sv b/pipelined/src/fpu/postproc/postprocess.sv index e5577a9ea..0880d33e2 100644 --- a/pipelined/src/fpu/postproc/postprocess.sv +++ b/pipelined/src/fpu/postproc/postprocess.sv @@ -48,10 +48,8 @@ module postprocess ( input logic FmaAs, // the modified Z sign - depends on instruction input logic FmaPs, // the product's sign input logic [`NE+1:0] FmaSe, - input logic [`NE+1:0] FmaPe, // Product exponent input logic [3*`NF+5:0] FmaSm, // the positive sum input logic FmaZmS, // sticky bit that is calculated during alignment - input logic FmaKillProd, // set the product to zero before addition if the product is too small to matter input logic FmaSs, input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // the normalization shift count //divide signals @@ -148,7 +146,7 @@ module postprocess ( cvtshiftcalc cvtshiftcalc(.ToInt, .CvtCe, .CvtResDenormUf, .Xm, .CvtLzcIn, .XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn); - fmashiftcalc fmashiftcalc(.FmaSm, .Ze, .FmaPe, .FmaSCnt, .Fmt, .FmaKillProd, .NormSumExp, .FmaSe, + fmashiftcalc fmashiftcalc(.FmaSm, .Ze, .FmaSCnt, .Fmt, .NormSumExp, .FmaSe, .FmaSZero, .FmaPreResultDenorm, .FmaShiftAmt, .FmaShiftIn); divshiftcalc divshiftcalc(.Fmt, .Sqrt, .DivQe, .DivQm, .DivResDenorm, .DivDenormShiftPos, .DivShiftAmt, .DivShiftIn); diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 1b2ed42ee..dbb852e84 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -233,7 +233,7 @@ module csr #(parameter .STATUS_TVM, .CSRWriteValM, .PrivilegeModeW, .CSRSReadValM, .STVEC_REGW, .SEPC_REGW, .SCOUNTEREN_REGW, - .SATP_REGW, .MIP_REGW, .MIE_REGW, + .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .WriteSSTATUSM, .IllegalCSRSAccessM); csru csru(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM, diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index bebad50dd..aa4de62af 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -62,7 +62,7 @@ module csri #(parameter // SSIP is writable in SIP if S mode exists if (`S_SUPPORTED) begin:mask assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writeable in MIP (20210108-draft 3.1.9) - assign SIP_WRITE_MASK = 12'h002; // SSIP is writeable in SIP (privileged 20210108-draft 4.1.3) + assign SIP_WRITE_MASK = 12'h002; // SSIP is writeable in SIP (privileged 20210108-draft 4.1.3) assign MIE_WRITE_MASK = 12'hAAA; end else begin:mask assign MIP_WRITE_MASK = 12'h000; diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv index 33ffa0ecf..3a8e73ee6 100644 --- a/pipelined/src/privileged/csrm.sv +++ b/pipelined/src/privileged/csrm.sv @@ -151,8 +151,8 @@ module csrm #(parameter // CSRs flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); if (`S_SUPPORTED) begin:deleg // DELEG registers should exist - flopenr #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK /*12'h7FF*/, MEDELEG_REGW); - flopenr #(12) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM[11:0] & MIDELEG_MASK /*12'h222*/, MIDELEG_REGW); + flopenr #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK, MEDELEG_REGW); + flopenr #(12) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM[11:0] & MIDELEG_MASK, MIDELEG_REGW); end else assign {MEDELEG_REGW, MIDELEG_REGW} = 0; flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW); diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv index d4000cdba..cf1a4d2f3 100644 --- a/pipelined/src/privileged/csrs.sv +++ b/pipelined/src/privileged/csrs.sv @@ -61,7 +61,7 @@ module csrs #(parameter (* mark_debug = "true" *) output logic [`XLEN-1:0] SEPC_REGW, output logic [31:0] SCOUNTEREN_REGW, output logic [`XLEN-1:0] SATP_REGW, - (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, + (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, output logic WriteSSTATUSM, output logic IllegalCSRSAccessM ); @@ -102,7 +102,7 @@ module csrs #(parameter case (CSRAdrM) SSTATUS: CSRSReadValM = SSTATUS_REGW; STVEC: CSRSReadValM = STVEC_REGW; - SIP: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW & 12'h222}; // only read supervisor fields + SIP: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields // *** and with MIDELEG instead of 222 SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW & 12'h222}; // only read supervisor fields SSCRATCH: CSRSReadValM = SSCRATCH_REGW; SEPC: CSRSReadValM = SEPC_REGW; diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile index 8292b9888..2918494dd 100644 --- a/tests/riscof/Makefile +++ b/tests/riscof/Makefile @@ -8,6 +8,7 @@ wally_workdir = $(work)/wally-riscv-arch-test current_dir = $(shell pwd) #XLEN ?= 64 +#all: root wally32 wally64 all: root arch32 wally32 wally32e arch64 wally64 root: diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index 82279e92d..7dfe1f0a3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -1295,6 +1295,12 @@ write_pmpaddr_end: addi a6, a6, 4 j test_loop +write_mideleg: + // writes the value in t4 to the mideleg register + // Doesn't log anything + csrw mideleg, t4 + j test_loop + executable_test: // Execute the code at the address in t3, returning the value in t2. // Assumes the code modifies t2, to become the value stored in t4 for this test. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S index b5a70625a..414fb44b3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S @@ -784,6 +784,7 @@ test_cases: # =========== S-mode enable tests (7.X) =========== +.4byte 0x0, 0x222, write_mideleg # delegate supervisor interrupts to S mode .4byte 0x0, 0x0, goto_s_mode # go to s-mode. 0xb written to output .4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 .4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S index 68dcf82b6..a6ed546a8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S @@ -102,6 +102,7 @@ test_cases: # =========== Enter Supervisor Mode =========== +.4byte 0x0, 0x222, write_mideleg # delegate supervisor interrupts to S mode .4byte 0x0, 0x0, goto_s_mode # Enter supervisor mode # =========== Test interrupt enables and priorities =========== diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index bd43eb117..7310857ab 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -1335,6 +1335,12 @@ write_pmpaddr_end: addi a6, a6, 8 j test_loop +write_mideleg: + // writes the value in t4 to the mideleg register + // Doesn't log anything + csrw mideleg, t4 + j test_loop + executable_test: // Execute the code at the address in t3, returning the value in t2. // Assumes the code modifies t2, to become the value stored in t4 for this test. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S index 43ceabfcf..b50b20f96 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S @@ -784,6 +784,7 @@ test_cases: # =========== S-mode enable tests (7.X) =========== +.8byte 0x0, 0x222, write_mideleg # delegate supervisor interrupts to S mode .8byte 0x0, 0x0, goto_s_mode # go to s-mode. 0xb written to output .8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 .8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S index ed5063e86..5a6dc34e2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S @@ -102,6 +102,7 @@ test_cases: # =========== Enter Supervisor Mode =========== +.8byte 0x0, 0x222, write_mideleg # delegate supervisor interrupts to S mode .8byte 0x0, 0x0, goto_s_mode # Enter supervisor mode # =========== Test interrupt enables and priorities ===========