From aaf36d11b5d299101ebf4a2cd084350be15e0fe4 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 5 Nov 2024 15:20:53 -0600 Subject: [PATCH 001/212] Now have the vcu108 kind of working with the new spi controller. However, it still has issues mounting the ext4 partition. --- fpga/constraints/big-debug-spi.xdc | 267 ++++++++++++++++++++++++ fpga/constraints/constraints-vcu108.xdc | 5 +- fpga/constraints/marked_debug.txt | 49 +++-- fpga/src/fpgaTop.sv | 5 +- 4 files changed, 304 insertions(+), 22 deletions(-) create mode 100644 fpga/constraints/big-debug-spi.xdc diff --git a/fpga/constraints/big-debug-spi.xdc b/fpga/constraints/big-debug-spi.xdc new file mode 100644 index 000000000..b5318e7d2 --- /dev/null +++ b/fpga/constraints/big-debug-spi.xdc @@ -0,0 +1,267 @@ +create_debug_core u_ila_0 ila + + + + +set_property C_DATA_DEPTH 65536 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +startgroup +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] +endgroup +connect_debug_port u_ila_0/clk [get_nets CPUCLK] + +set_property port_width 64 [get_debug_ports u_ila_0/probe0] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe1] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe2] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe3] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe4] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsoc/core/lsu/MemRWM[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe5] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe6] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsoc/core/lsu/ReadDataM[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe7] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]] + + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe8] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/SDCCLK}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe9] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/SDCIn}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe10] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/SDCCS[0]}]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe11] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] +connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/InterruptPending[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/InterruptPending[1]}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe12] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] +connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOWriteInc}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe13] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] +connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOEmpty}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe14] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] +connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOReadInc}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe15] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] +connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitLoad}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe16] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] +connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/SDCCmd}]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe17] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] +connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ShiftEdge}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe18] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] +connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SampleEdge}]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe19] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] +connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe20] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] +connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe21] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] +connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitLoad}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe22] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] +connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ShiftIn}]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe23] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] +connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/SCLKenable} ]] + +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe24] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] +connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/CurrState[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/CurrState[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/CurrState[2]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe25] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] +connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/EndOfFrame}]] + +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe26] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] +connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/NextState[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/NextState[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/NextState[2]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe27] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] +connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/BitNum[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/BitNum[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/BitNum[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/BitNum[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe28] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] +connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/ContinueTransmit}]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe29] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] +connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptrnext[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptrnext[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptrnext[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptrnext[3]} ]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe30] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] +connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitRegLoaded}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe31] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] +connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/PhaseOneOffset}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe32] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] +connect_debug_port u_ila_0/probe32 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/SPICLK}]] + +create_debug_port u_ila_0 probe +set_property port_width 9 [get_debug_ports u_ila_0/probe33] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] +connect_debug_port u_ila_0/probe33 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[7]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[8]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe34] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] +connect_debug_port u_ila_0/probe34 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOWriteInc}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe35] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] +connect_debug_port u_ila_0/probe35 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOReadInc}]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe36] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36] +connect_debug_port u_ila_0/probe36 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe37] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] +connect_debug_port u_ila_0/probe37 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveWatermark[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveWatermark[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveWatermark[2]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe38] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] +connect_debug_port u_ila_0/probe38 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveReadWatermarkLevel[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveReadWatermarkLevel[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveReadWatermarkLevel[2]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe39] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] +connect_debug_port u_ila_0/probe39 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe40] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] +connect_debug_port u_ila_0/probe40 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOFull}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe41] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41] +connect_debug_port u_ila_0/probe41 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOEmpty}]] + +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe42] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42] +connect_debug_port u_ila_0/probe42 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/raddr[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/raddr[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/raddr[2]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe43] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43] +connect_debug_port u_ila_0/probe43 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/waddr[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/waddr[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/waddr[2]} ]] + + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe44] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44] +connect_debug_port u_ila_0/probe44 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptr[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptr[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptr[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptr[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe45] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45] +connect_debug_port u_ila_0/probe45 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe46] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46] +connect_debug_port u_ila_0/probe46 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[3]} ]] + + + +# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock. +#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk] +connect_debug_port dbg_hub/clk [get_nets CPUCLK] + diff --git a/fpga/constraints/constraints-vcu108.xdc b/fpga/constraints/constraints-vcu108.xdc index 0defeeb10..a25eae2aa 100644 --- a/fpga/constraints/constraints-vcu108.xdc +++ b/fpga/constraints/constraints-vcu108.xdc @@ -83,7 +83,7 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_port ##### SD Card I/O ##### # create the generated SPICLK -create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/spi.spi/SPICLK] +create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPICLK] set_output_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCS}] set_output_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCS}] @@ -95,8 +95,9 @@ set_input_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCWP}] set_input_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCWP}] set_output_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCmd}] set_output_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCmd}] -create_generated_clock -name SPISDCClockOut -multiply_by 1 -source [get_pins sdcclkoddr/C] [get_ports SDCCLK] +#create_generated_clock -name SPISDCClockOut -multiply_by 1 -source [get_pins sdcclkoddr/C] [get_ports SDCCLK] set_clock_latency -source -max 3.0 [get_ports SDCCLK] +#set_output_delay -clock [get_clocks SPISDCClock] 0.000 [get_ports SDCCLK] set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCS}] diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index a50091827..a5ffb3c83 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -5,22 +5,39 @@ wally/wallypipelinedcore.sv: logic InstrM lsu/lsu.sv: logic IEUAdrM lsu/lsu.sv: logic MemRWM mmu/hptw.sv: logic SATP_REGW -uncore/spi_apb.sv: logic ShiftIn -uncore/spi_apb.sv: logic ReceiveShiftReg -uncore/spi_apb.sv: logic SCLKenable -uncore/spi_apb.sv: logic SampleEdge -uncore/spi_apb.sv: logic Active -uncore/spi_apb.sv: statetype state -uncore/spi_apb.sv: typedef rsrstatetype -uncore/spi_apb.sv: logic SPICLK -uncore/spi_apb.sv: logic SPIOut -uncore/spi_apb.sv: logic SPICS -uncore/spi_apb.sv: logic SckMode -uncore/spi_apb.sv: logic SckDiv +uncore/uncore.sv: logic SDCCmd +uncore/uncore.sv: logic SDCCLK +uncore/uncore.sv: logic SDCIn +uncore/uncore.sv: logic SDCCS +uncore/spi_apb.sv: logic InterruptPending +uncore/spi_apb.sv: logic TransmitFIFOWriteInc +uncore/spi_apb.sv: logic TransmitFIFOEmpty +uncore/spi_apb.sv: logic TransmitFIFOReadInc +uncore/spi_apb.sv: logic TransmitLoad uncore/spi_apb.sv: logic ShiftEdge -uncore/spi_apb.sv: logic TransmitShiftRegLoad -uncore/spi_apb.sv: logic TransmitShiftReg +uncore/spi_apb.sv: logic SampleEdge +uncore/spi_apb.sv: logic ReceiveShiftReg +uncore/spi_apb.sv: logic TransmitReg +uncore/spi_apb.sv: logic ShiftIn +uncore/spi_apb.sv: logic EndOfFrame +uncore/spi_apb.sv: logic TransmitRegLoaded uncore/spi_apb.sv: logic TransmitData -uncore/spi_apb.sv: logic ReceiveData +uncore/spi_apb.sv: logic ReceiveFIFOWriteInc +uncore/spi_apb.sv: logic ReceiveFIFOReadInc uncore/spi_apb.sv: logic ReceiveShiftRegEndian -uncore/spi_apb.sv: logic ASR +uncore/spi_apb.sv: logic ReceiveWatermark +uncore/spi_apb.sv: logic ReceiveReadWatermarkLevel +uncore/spi_apb.sv: logic ReceiveData +uncore/spi_apb.sv: logic ReceiveFIFOFull +uncore/spi_apb.sv: logic ReceiveFIFOEmpty +uncore/spi_controller.sv: logic SCLKenable +uncore/spi_controller.sv: statetype CurrState +uncore/spi_controller.sv: statetype NextState +uncore/spi_controller.sv: logic BitNum +uncore/spi_controller.sv: logic ContinueTransmit +uncore/spi_controller.sv: logic PhaseOneOffset +uncore/spi_controller.sv: logic SPICLK +uncore/spi_fifo.sv: logic rptr +uncore/spi_fifo.sv: logic rptrnext +uncore/spi_fifo.sv: logic raddr +uncore/spi_fifo.sv: logic waddr diff --git a/fpga/src/fpgaTop.sv b/fpga/src/fpgaTop.sv index 2bf6aee5e..7b503e1f1 100644 --- a/fpga/src/fpgaTop.sv +++ b/fpga/src/fpgaTop.sv @@ -216,11 +216,8 @@ module fpgaTop .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK(SDCCLKInternal), .ExternalStall(RVVIStall)); + .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK(SDCCLK), .ExternalStall(RVVIStall)); - // *** these are different for different fpga ugh. - ODDRE1 sdcclkoddr(.Q(SDCCLK), .C(SDCCLKInternal), .D1('0), - .D2(1'b1), .SR('0)); // ahb lite to axi bridge ahbaxibridge ahbaxibridge From 827f986fae34079ac5ccc5ca06a1e7359bffe05b Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 5 Nov 2024 16:01:08 -0600 Subject: [PATCH 002/212] This configuration of the vcu108 actually seems to work. --- fpga/constraints/constraints-vcu108.xdc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/fpga/constraints/constraints-vcu108.xdc b/fpga/constraints/constraints-vcu108.xdc index a25eae2aa..2fb191e6c 100644 --- a/fpga/constraints/constraints-vcu108.xdc +++ b/fpga/constraints/constraints-vcu108.xdc @@ -95,9 +95,8 @@ set_input_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCWP}] set_input_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCWP}] set_output_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCmd}] set_output_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCmd}] -#create_generated_clock -name SPISDCClockOut -multiply_by 1 -source [get_pins sdcclkoddr/C] [get_ports SDCCLK] -set_clock_latency -source -max 3.0 [get_ports SDCCLK] -#set_output_delay -clock [get_clocks SPISDCClock] 0.000 [get_ports SDCCLK] +set_output_delay -clock [get_clocks SPISDCClock] -max 2.000 [get_ports SDCCLK] +set_output_delay -clock [get_clocks SPISDCClock] -min -2.000 [get_ports SDCCLK] set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCS}] From f08414bb6976ee818398251da16a6e3cdb593d07 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 5 Nov 2024 16:10:20 -0600 Subject: [PATCH 003/212] Unfortunately vcu108 spi clock is forced to run at 400KHz for now. --- linux/devicetree/wally-vcu108.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux/devicetree/wally-vcu108.dts b/linux/devicetree/wally-vcu108.dts index 211631345..bb9200822 100644 --- a/linux/devicetree/wally-vcu108.dts +++ b/linux/devicetree/wally-vcu108.dts @@ -102,7 +102,7 @@ mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; - spi-max-frequency = <1000000>; + spi-max-frequency = <400000>; voltage-ranges = <3300 3300>; disable-wp; // gpios = <&gpio0 6 1>; From f824d15c89e692ea33eb0e2f9a1cc44536eabcd9 Mon Sep 17 00:00:00 2001 From: Daniyal-R-A <97160211+Daniyal-R-A@users.noreply.github.com> Date: Sat, 9 Nov 2024 02:54:50 -0800 Subject: [PATCH 004/212] Enabling Zb Instructions --- config/rv32gc/coverage.svh | 8 -------- config/rv64gc/coverage.svh | 9 --------- 2 files changed, 17 deletions(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index eed513f9f..31e0d77a4 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -14,9 +14,6 @@ `include "RV32Zbb_coverage.svh" `include "RV32Zbc_coverage.svh" `include "RV32Zbs_coverage.svh" -`include "RV32Zbkb_coverage.svh" -`include "RV32Zbkc_coverage.svh" -`include "RV32Zbkx_coverage.svh" `include "RV32ZfaF_coverage.svh" `include "RV32ZfaD_coverage.svh" `include "RV32ZfaZfh_coverage.svh" @@ -29,11 +26,6 @@ `include "RV32ZcbZbb_coverage.svh" `include "RV32Zcf_coverage.svh" `include "RV32Zcd_coverage.svh" -`include "RV32Zaamo_coverage.svh" -`include "RV32Zalrsc_coverage.svh" -`include "RV32Zknd_coverage.svh" -`include "RV32Zkne_coverage.svh" -`include "RV32Zknh_coverage.svh" // Privileged extensions `include "ZicsrM_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index a293eb5b1..a9816ce98 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -14,9 +14,6 @@ `include "RV64Zbb_coverage.svh" `include "RV64Zbc_coverage.svh" `include "RV64Zbs_coverage.svh" -`include "RV64Zbkb_coverage.svh" -`include "RV64Zbkc_coverage.svh" -`include "RV64Zbkx_coverage.svh" `include "RV64ZfaF_coverage.svh" `include "RV32ZfaD_coverage.svh" `include "RV32ZfaZfh_coverage.svh" @@ -29,12 +26,6 @@ `include "RV64ZcbZbb_coverage.svh" `include "RV64ZcbZba_coverage.svh" `include "RV64Zcd_coverage.svh" -`include "RV64Zaamo_coverage.svh" -`include "RV64Zalrsc_coverage.svh" -`include "RV64Zknd_coverage.svh" -`include "RV64Zkne_coverage.svh" -`include "RV64Zknh_coverage.svh" - From 3137fd7db207472d09ff44bf455f43c831d10a61 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 11 Nov 2024 14:23:58 -0600 Subject: [PATCH 005/212] Resolved some of the issues with the cache simulator mismatching with Wally. The LRU was incorrectly updating it's state while the cache was stalled causin g the LRU state to be update when it should not be. --- src/cache/cache.sv | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 5855afb03..d6a68d5d1 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -75,9 +75,9 @@ module cache import cvw::*; #(parameter cvw_t P, logic SelAdrData; logic SelAdrTag; logic [1:0] AdrSelMuxSelData; - logic [1:0] AdrSelMuxSelTag; + logic [1:0] AdrSelMuxSelTag, AdrSelMuxSelTag2; logic [SETLEN-1:0] CacheSetData; - logic [SETLEN-1:0] CacheSetTag; + logic [SETLEN-1:0] CacheSetTag, CacheSetTag2; logic [LINELEN-1:0] LineWriteData; logic ClearDirty, SetDirty, SetValid, ClearValid; logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0]; @@ -117,6 +117,10 @@ module cache import cvw::*; #(parameter cvw_t P, mux3 #(SETLEN) AdrSelMuxTag(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr, AdrSelMuxSelTag, CacheSetTag); + assign AdrSelMuxSelTag2 = {FlushCache, ((SelAdrTag | SelHPTW | Stall) & ~((READ_ONLY_CACHE == 1) & FlushStage))}; + mux3 #(SETLEN) AdrSelMuxTag2(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr, + AdrSelMuxSelTag2, CacheSetTag2); + // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(P, PA_BITS, XLEN, NUMSETS, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( .clk, .reset, .CacheEn, .CacheSetData, .CacheSetTag, .PAdr, .LineWriteData, .LineByteMask, .SelVictim, @@ -126,7 +130,7 @@ module cache import cvw::*; #(parameter cvw_t P, // Select victim way for associative caches if(NUMWAYS > 1) begin:vict cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMSETS) cacheLRU( - .clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSetTag, .LRUWriteEn, + .clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSetTag(CacheSetTag2), .LRUWriteEn, .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache); end else assign VictimWay = 1'b1; // one hot. From 0cf7b2e45abf9b242e0406cbdeabb2edfd43f91e Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 11 Nov 2024 16:37:17 -0600 Subject: [PATCH 006/212] Progress on fixing the cache simulator to support cbo instructions. --- bin/CacheSim.py | 23 +++++++++++++++++++---- testbench/common/loggers.sv | 4 ++++ 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/bin/CacheSim.py b/bin/CacheSim.py index d07ded9ea..f66cb95d0 100755 --- a/bin/CacheSim.py +++ b/bin/CacheSim.py @@ -84,6 +84,14 @@ class Cache: for way in self.ways: for line in way: line.dirty = False + + # invalidate this specific line + def cboinvalidate(self, addr): + tag, setnum, _ = self.splitaddr(addr) + for waynum in range(self.numways): + line = self.ways[waynum][setnum] + if line.tag == tag and line.valid: + line.dirty = 0 # invalidates the cache by setting all valid bits to False def invalidate(self): @@ -108,14 +116,15 @@ class Cache: # performs a cache access with the given address. # returns a character representing the outcome: # H/M/E/D - hit, miss, eviction, or eviction with writeback - def cacheaccess(self, addr, write=False): + def cacheaccess(self, addr, write=False, clean=False): tag, setnum, _ = self.splitaddr(addr) # check our ways to see if we have a hit + #print(f"addr is {addr:x} Set is {setnum}") for waynum in range(self.numways): line = self.ways[waynum][setnum] if line.tag == tag and line.valid: - line.dirty = line.dirty or write + line.dirty = 0 if clean else line.dirty or write self.update_pLRU(waynum, setnum) return 'H' @@ -132,6 +141,7 @@ class Cache: # we need to evict. Select a victim and overwrite. victim = self.getvictimway(setnum) + #print(f"addr is {addr:x} Victim is {victim} Set is {setnum}") line = self.ways[victim][setnum] prevdirty = line.dirty line.tag = tag @@ -243,10 +253,15 @@ def main(): cache.invalidate() if args.verbose: print("I") + elif lninfo[1] == 'C' or lninfo[1] == 'L': + cache.cboinvalidate() + if args.verbose: + print("C"); else: addr = int(lninfo[0], 16) - iswrite = lninfo[1] == 'W' or lninfo[1] == 'A' - result = cache.cacheaccess(addr, iswrite) + iswrite = lninfo[1] == 'W' or lninfo[1] == 'A' or lninfo[1] == 'Z' + iscboclean = lninfo[1] == 'C' + result = cache.cacheaccess(addr, iswrite, iscboclean) if args.verbose: tag, setnum, offset = cache.splitaddr(addr) diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index 6b026257a..619cd13d5 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -210,6 +210,10 @@ module loggers import cvw::*; #(parameter cvw_t P, dut.core.lsu.LSUAtomicM[1] ? "A" : dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" : + dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b1000 ? "Z" : // cmo.zero + dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0001 ? "V" : // cmo.inval should just clear the valid and dirty bits + dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0010 ? "C" : // cmo.clean should act like a read in terms of the lru, but clears the dirty bit + dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0100 ? "L" : // cmo.flush should just clear and the valid and drity bits "NULL"; end From 8a4868ac57e79c4b06b083dde0e8f3b854c7422f Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 12 Nov 2024 11:35:29 -0600 Subject: [PATCH 007/212] Resolved a bug in the cache but there are still mismatches with the cache simulator. --- sim/rv64gc_CacheSim.py | 6 ++++-- src/cache/cacheway.sv | 6 +++++- testbench/common/loggers.sv | 2 +- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/sim/rv64gc_CacheSim.py b/sim/rv64gc_CacheSim.py index 60dc092b5..16a7acf90 100755 --- a/sim/rv64gc_CacheSim.py +++ b/sim/rv64gc_CacheSim.py @@ -54,7 +54,8 @@ tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "ar "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"] # arch64i is the most interesting case. Uncomment line below to run just that case -# tests64gc = ["arch64i"] +#tests64gc = ["arch64i"] +tests64gc = ["coverage64gc"] cachetypes = ["ICache", "DCache"] simdir = os.path.expandvars("$WALLY/sim") @@ -63,10 +64,11 @@ def main(): parser = argparse.ArgumentParser(description="Runs the cache simulator on all rv64gc test suites") parser.add_argument('-p', "--perf", action='store_true', help="Report hit/miss ratio") parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations") - parser.add_argument('-s', "--sim", help="Simulator", choices=["questa", "verilator", "vcs"], default="verilator") + parser.add_argument('-s', "--sim", help="Simulator", choices=["questa", "verilator", "vcs"], default="questa") args = parser.parse_args() simargs = "I_CACHE_ADDR_LOGGER=1\\\'b1 D_CACHE_ADDR_LOGGER=1\\\'b1" testcmd = "wsim --sim " + args.sim + " rv64gc {} --params \"" + simargs + "\" > /dev/null" + #cachecmd = "CacheSim.py 64 4 56 44 -f {} --verbose" cachecmd = "CacheSim.py 64 4 56 44 -f {}" mismatches = 0 diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index addf1a019..575934727 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -175,7 +175,11 @@ module cacheway import cvw::*; #(parameter cvw_t P, //if (reset) DirtyBits <= {NUMSETS{1'b0}}; if(CacheEn) begin Dirty <= DirtyBits[CacheSetTag]; - if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) DirtyBits[CacheSetData] <= SetDirtyWay; // exclusion-tag: cache UpdateDirty + if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) begin + DirtyBits[CacheSetData] <= SetDirtyWay; // exclusion-tag: cache UpdateDirty + if (CacheSetData == CacheSetTag) Dirty <= SetDirtyWay; + else Dirty <= DirtyBits[CacheSetTag]; + end end end end else assign Dirty = 1'b0; diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index 619cd13d5..829646fa9 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -217,7 +217,7 @@ module loggers import cvw::*; #(parameter cvw_t P, "NULL"; end - assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn & + assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn | AccessTypeString == "Z" | AccessTypeString == "C" | AccessTypeString == "L") & ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable & dut.core.lsu.bus.dcache.dcache.cachefsm.CacheEn & From 5cc1fd4a85e3c1cdcfc45cf22f0a576e215357e4 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 12 Nov 2024 12:08:14 -0600 Subject: [PATCH 008/212] Getting closer. Oly the wally64priv tests mismatch between the cachesim and wally. --- bin/CacheSim.py | 26 +- sim/questa/wave.do | 637 ++++++++++++++++++------------------ sim/rv64gc_CacheSim.py | 2 +- testbench/common/loggers.sv | 3 +- 4 files changed, 351 insertions(+), 317 deletions(-) diff --git a/bin/CacheSim.py b/bin/CacheSim.py index f66cb95d0..31bdb4d44 100755 --- a/bin/CacheSim.py +++ b/bin/CacheSim.py @@ -88,11 +88,21 @@ class Cache: # invalidate this specific line def cboinvalidate(self, addr): tag, setnum, _ = self.splitaddr(addr) + #print(f"In cboinvalidate addr is {addr:x} Set is {setnum}") for waynum in range(self.numways): line = self.ways[waynum][setnum] if line.tag == tag and line.valid: line.dirty = 0 - + line.valid = 0 + + def cboclean(self, addr): + tag, setnum, _ = self.splitaddr(addr) + #print(f"In cboinvalidate addr is {addr:x} Set is {setnum}") + for waynum in range(self.numways): + line = self.ways[waynum][setnum] + if line.tag == tag and line.valid: + line.dirty = 0 + # invalidates the cache by setting all valid bits to False def invalidate(self): for way in self.ways: @@ -121,6 +131,8 @@ class Cache: # check our ways to see if we have a hit #print(f"addr is {addr:x} Set is {setnum}") + if clean: + print("This was a cbo.clean") for waynum in range(self.numways): line = self.ways[waynum][setnum] if line.tag == tag and line.valid: @@ -253,14 +265,20 @@ def main(): cache.invalidate() if args.verbose: print("I") - elif lninfo[1] == 'C' or lninfo[1] == 'L': - cache.cboinvalidate() + elif lninfo[1] == 'V' or lninfo[1] == 'L': + addr = int(lninfo[0], 16) + cache.cboinvalidate(addr) + if args.verbose: + print(lninfo[1]); + elif lninfo[1] == 'C': + addr = int(lninfo[0], 16) + cache.cboclean(addr) if args.verbose: print("C"); else: addr = int(lninfo[0], 16) iswrite = lninfo[1] == 'W' or lninfo[1] == 'A' or lninfo[1] == 'Z' - iscboclean = lninfo[1] == 'C' + iscboclean = False result = cache.cacheaccess(addr, iswrite, iscboclean) if args.verbose: diff --git a/sim/questa/wave.do b/sim/questa/wave.do index b00abf659..5a1f26ac4 100644 --- a/sim/questa/wave.do +++ b/sim/questa/wave.do @@ -100,72 +100,80 @@ add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbc add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush add wave -noupdate -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/FlushStage -add wave -noupdate -group ifu -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/PCNextF -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/PCPF -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheRW -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheAccess -add wave -noupdate -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay -add wave -noupdate -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF -add wave -noupdate -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr -add wave -noupdate -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay -add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/FlushStage -add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUUpdate -add wave -noupdate -group ifu -group icache -expand -group lru {/testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory[50]} -add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/CurrLRU -add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory -add wave -noupdate -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -group ifu -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits} -add wave -noupdate -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -group ifu -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits} -add wave -noupdate -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay} -add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -group ifu -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits} -add wave -noupdate -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -group ifu -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits} -add wave -noupdate -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/FlushStage +add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheRW +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheAccess +add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay +add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF +add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr +add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay +add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/FlushStage +add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUUpdate +add wave -noupdate -group ifu -expand -group icache -expand -group lru {/testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory[50]} +add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/ReadLRU +add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/NextLRU +add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/ForwardLRU +add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/BypassedLRU +add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/CurrLRU +add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdrTag +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/AdrSelMuxSelTag +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/CacheSetTag +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/PAdr +add wave -noupdate -group ifu -expand -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -group ifu -expand -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -group ifu -expand -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits} +add wave -noupdate -group ifu -expand -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay} +add wave -noupdate -group ifu -expand -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -group ifu -expand -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -group ifu -expand -group icache -group way0 -label tag -expand {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr @@ -204,225 +212,224 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW -add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/IgnoreRequestTLB -add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskM -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskExtendedM -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskSpillM -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataM -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataSpillM -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteData -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/ByteMask -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/BlankByteMask -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/DemuxedByteMask -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/FetchBufferByteSel -add wave -noupdate -group lsu -group alignment {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/LineWriteData} -add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrExtE -add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrExtM -add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/NextSet -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOpM -add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineWay -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineCache -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/TagWay -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/Tag -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ValidWay -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/Hit -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/DirtyWay -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitDirtyWay -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitLineDirty -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/bwe} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/bwe} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/bwe} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ce} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay} -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBHit -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk -add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/TranslationVAdr -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBMissOrUpdateAF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -expand -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskM +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskExtendedM +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskSpillM +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataM +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataSpillM +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteData +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/ByteMask +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/BlankByteMask +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/DemuxedByteMask +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/FetchBufferByteSel +add wave -noupdate -expand -group lsu -group alignment {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/LineWriteData} +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrExtE +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrExtM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/NextSet +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOpM +add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/Hit +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {requesting address} {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheSetTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineWay +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineCache +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/TagWay +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/Tag +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ValidWay +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/Hit +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/DirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitLineDirty +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/bwe} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/bwe} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/bwe} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ce} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay} +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk +add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/TranslationVAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBMissOrUpdateAF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName add wave -noupdate -group {WriteBack stage} /testbench/dut/core/priv/priv/pmd/wfiW @@ -585,31 +592,31 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrs/csrs/STIME add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS -add wave -noupdate -group CSRs -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} -add wave -noupdate -group CSRs -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} -add wave -noupdate -group CSRs -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} -add wave -noupdate -group CSRs -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} -add wave -noupdate -group CSRs -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} -add wave -noupdate -group CSRs -group {Performance Counters} -expand -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} -add wave -noupdate -group CSRs -group {Performance Counters} -expand -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} -add wave -noupdate -group CSRs -group {Performance Counters} -expand -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} -add wave -noupdate -group CSRs -group {Performance Counters} -expand -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} -add wave -noupdate -group CSRs -group {Performance Counters} -expand -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} -add wave -noupdate -group CSRs -group {Performance Counters} -group ICACHE -label {I Cache Access} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]} -add wave -noupdate -group CSRs -group {Performance Counters} -group ICACHE -label {I Cache Miss} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]} -add wave -noupdate -group CSRs -group {Performance Counters} -group ICACHE -label {I Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]} -add wave -noupdate -group CSRs -group {Performance Counters} -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} -add wave -noupdate -group CSRs -group {Performance Counters} -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} -add wave -noupdate -group CSRs -group {Performance Counters} -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} -add wave -noupdate -group CSRs -group {Performance Counters} -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} -add wave -noupdate -group CSRs -group {Performance Counters} -group DCACHE -label {D Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]} -add wave -noupdate -group CSRs -group {Performance Counters} -group Privileged -label {CSR Write} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]} -add wave -noupdate -group CSRs -group {Performance Counters} -group Privileged -label Fence.I {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]} -add wave -noupdate -group CSRs -group {Performance Counters} -group Privileged -label sfence.VMA {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]} -add wave -noupdate -group CSRs -group {Performance Counters} -group Privileged -label Interrupt {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]} -add wave -noupdate -group CSRs -group {Performance Counters} -group Privileged -label Exception {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]} -add wave -noupdate -group CSRs -group {Performance Counters} -label {FDiv or IDiv Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]} -add wave -noupdate -group CSRs -group {Performance Counters} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW +add wave -noupdate -group CSRs -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -group ICACHE -label {I Cache Access} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -group ICACHE -label {I Cache Miss} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -group ICACHE -label {I Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -group DCACHE -label {D Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -group Privileged -label {CSR Write} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -group Privileged -label Fence.I {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -group Privileged -label sfence.VMA {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -group Privileged -label Interrupt {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -group Privileged -label Exception {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} -label {FDiv or IDiv Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]} +add wave -noupdate -group CSRs -expand -group {Performance Counters} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUResult @@ -661,14 +668,22 @@ add wave -noupdate -group spi -expand -group interface /testbench/dut/uncoregen/ add wave -noupdate -group spi -expand -group interface /testbench/dut/uncoregen/uncore/spi/spi/SPIIn add wave -noupdate -group spi /testbench/dut/uncoregen/uncore/spi/spi/ChipSelectMode add wave -noupdate -group spi /testbench/dut/uncoregen/uncore/spi/spi/SckMode -add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitShiftRegLoad add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/ShiftEdge -add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/Active add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitData -add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitShiftReg +add wave -noupdate /testbench/loggers/ICacheLogger/HitMissString +add wave -noupdate /testbench/loggers/ICacheLogger/Enable +add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheEn +add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/cachefsm/FlushStage +add wave -noupdate -expand -group {Dcache logger} /testbench/loggers/DCacheLogger/HitMissString +add wave -noupdate -expand -group {Dcache logger} /testbench/loggers/DCacheLogger/AccessTypeString +add wave -noupdate -expand -group {Dcache logger} /testbench/loggers/DCacheLogger/resetD +add wave -noupdate -expand -group {Dcache logger} /testbench/loggers/DCacheLogger/resetEdge +add wave -noupdate -expand -group {Dcache logger} -color Pink /testbench/loggers/DCacheLogger/Enabled +add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/FlushStage TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {640 ns} 1} {{Cursor 4} {2400 ns} 1} {{Cursor 3} {1197 ns} 0} {{Cursor 4} {223860 ns} 1} -quietly wave cursor active 3 +WaveRestoreCursors {{Cursor 4} {159474 ns} 1} {{Cursor 4} {180834 ns} 1} {{Cursor 3} {37056 ns} 1} {{Cursor 5} {36113 ns} 0} +quietly wave cursor active 4 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 configure wave -justifyvalue left @@ -683,4 +698,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1130 ns} {1230 ns} +WaveRestoreZoom {35840 ns} {36240 ns} diff --git a/sim/rv64gc_CacheSim.py b/sim/rv64gc_CacheSim.py index 16a7acf90..0d2a91b44 100755 --- a/sim/rv64gc_CacheSim.py +++ b/sim/rv64gc_CacheSim.py @@ -55,7 +55,7 @@ tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "ar "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"] # arch64i is the most interesting case. Uncomment line below to run just that case #tests64gc = ["arch64i"] -tests64gc = ["coverage64gc"] +#tests64gc = ["coverage64gc"] cachetypes = ["ICache", "DCache"] simdir = os.path.expandvars("$WALLY/sim") diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index 829646fa9..7a60c7c0d 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -217,7 +217,8 @@ module loggers import cvw::*; #(parameter cvw_t P, "NULL"; end - assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn | AccessTypeString == "Z" | AccessTypeString == "C" | AccessTypeString == "L") & + assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn | AccessTypeString == "Z" | + ((AccessTypeString == "C" | AccessTypeString == "L") & dut.core.lsu.bus.dcache.dcache.cachefsm.CacheStall == 0)) & ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable & dut.core.lsu.bus.dcache.dcache.cachefsm.CacheEn & From b7b7c797265fe789e6875b015b0a2d0309b138de Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 12 Nov 2024 14:16:55 -0600 Subject: [PATCH 009/212] CBO.FLUSH was not clearing the valid bit if the cacheline was clean. --- bin/CacheSim.py | 6 +- sim/questa/wave.do | 200 ++++++++++++++++++------------------ sim/rv64gc_CacheSim.py | 1 + src/cache/cachefsm.sv | 2 +- testbench/common/loggers.sv | 2 +- 5 files changed, 108 insertions(+), 103 deletions(-) diff --git a/bin/CacheSim.py b/bin/CacheSim.py index 31bdb4d44..d5bf1cd5d 100755 --- a/bin/CacheSim.py +++ b/bin/CacheSim.py @@ -97,7 +97,7 @@ class Cache: def cboclean(self, addr): tag, setnum, _ = self.splitaddr(addr) - #print(f"In cboinvalidate addr is {addr:x} Set is {setnum}") + #print(f"In cboclean addr is {addr:x} Set is {setnum}") for waynum in range(self.numways): line = self.ways[waynum][setnum] if line.tag == tag and line.valid: @@ -131,8 +131,8 @@ class Cache: # check our ways to see if we have a hit #print(f"addr is {addr:x} Set is {setnum}") - if clean: - print("This was a cbo.clean") + #if clean: + # print("This was a cbo.clean") for waynum in range(self.numways): line = self.ways[waynum][setnum] if line.tag == tag and line.valid: diff --git a/sim/questa/wave.do b/sim/questa/wave.do index 5a1f26ac4..563cc5c02 100644 --- a/sim/questa/wave.do +++ b/sim/questa/wave.do @@ -288,77 +288,81 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbe add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ce} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheSetData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheSetTag} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/bwe} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/bwe} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/bwe} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ce} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} @@ -406,30 +410,30 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dm add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk -add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/TranslationVAdr -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBMissOrUpdateAF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk +add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/TranslationVAdr +add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBMissOrUpdateAF +add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault +add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName add wave -noupdate -group {WriteBack stage} /testbench/dut/core/priv/priv/pmd/wfiW @@ -682,8 +686,8 @@ add wave -noupdate -expand -group {Dcache logger} -color Pink /testbench/loggers add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/FlushStage TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {159474 ns} 1} {{Cursor 4} {180834 ns} 1} {{Cursor 3} {37056 ns} 1} {{Cursor 5} {36113 ns} 0} -quietly wave cursor active 4 +WaveRestoreCursors {{Cursor 4} {95120 ns} 1} {{Cursor 4} {95125 ns} 0} {{Cursor 3} {11250 ns} 1} {{Cursor 5} {17034 ns} 1} +quietly wave cursor active 2 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 configure wave -justifyvalue left @@ -698,4 +702,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {35840 ns} {36240 ns} +WaveRestoreZoom {95018 ns} {95228 ns} diff --git a/sim/rv64gc_CacheSim.py b/sim/rv64gc_CacheSim.py index 0d2a91b44..6f9d575e1 100755 --- a/sim/rv64gc_CacheSim.py +++ b/sim/rv64gc_CacheSim.py @@ -56,6 +56,7 @@ tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "ar # arch64i is the most interesting case. Uncomment line below to run just that case #tests64gc = ["arch64i"] #tests64gc = ["coverage64gc"] +tests64gc = ["wally64priv"] cachetypes = ["ICache", "DCache"] simdir = os.path.expandvars("$WALLY/sim") diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 1a39ad17a..e1916b6cb 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -155,7 +155,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P, assign SetValid = CurrState == STATE_WRITE_LINE | (CurrState == STATE_ACCESS & CMOZeroNoEviction) | (CurrState == STATE_WRITEBACK & CacheBusAck & CMOpM[3]); - assign ClearValid = (CurrState == STATE_ACCESS & CMOpM[0]) | + assign ClearValid = (CurrState == STATE_ACCESS & (CMOpM[0] | CMOpM[2])) | (CurrState == STATE_WRITEBACK & CMOpM[2] & CacheBusAck); assign LRUWriteEn = (((CurrState == STATE_ACCESS & (AnyHit | CMOZeroNoEviction)) | (CurrState == STATE_WRITE_LINE)) & ~FlushStage) | diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index 7a60c7c0d..0307675d6 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -218,7 +218,7 @@ module loggers import cvw::*; #(parameter cvw_t P, end assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn | AccessTypeString == "Z" | - ((AccessTypeString == "C" | AccessTypeString == "L") & dut.core.lsu.bus.dcache.dcache.cachefsm.CacheStall == 0)) & + ((AccessTypeString == "C" | AccessTypeString == "L" | AccessTypeString == "V") & dut.core.lsu.bus.dcache.dcache.cachefsm.CacheStall == 0)) & ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable & dut.core.lsu.bus.dcache.dcache.cachefsm.CacheEn & From 383fce552227c1201df7fc111bcc237833f8e416 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 12 Nov 2024 14:38:44 -0600 Subject: [PATCH 010/212] Fixed the issue with cbo.clean. --- src/cache/cachefsm.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index e1916b6cb..5f42c7690 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -155,7 +155,8 @@ module cachefsm import cvw::*; #(parameter cvw_t P, assign SetValid = CurrState == STATE_WRITE_LINE | (CurrState == STATE_ACCESS & CMOZeroNoEviction) | (CurrState == STATE_WRITEBACK & CacheBusAck & CMOpM[3]); - assign ClearValid = (CurrState == STATE_ACCESS & (CMOpM[0] | CMOpM[2])) | + assign ClearValid = (CurrState == STATE_ACCESS & (CMOpM[0] | (CMOpM[2] & ~HitLineDirty))) | + //assign ClearValid = (CurrState == STATE_ACCESS & (CMOpM[0])) | (CurrState == STATE_WRITEBACK & CMOpM[2] & CacheBusAck); assign LRUWriteEn = (((CurrState == STATE_ACCESS & (AnyHit | CMOZeroNoEviction)) | (CurrState == STATE_WRITE_LINE)) & ~FlushStage) | From ea2b69e1e7b5bbc70798813633d1724bc0b9d913 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 12 Nov 2024 14:44:09 -0600 Subject: [PATCH 011/212] Updates to wavefile. --- sim/questa/wave.do | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sim/questa/wave.do b/sim/questa/wave.do index 563cc5c02..ee42a7065 100644 --- a/sim/questa/wave.do +++ b/sim/questa/wave.do @@ -686,8 +686,8 @@ add wave -noupdate -expand -group {Dcache logger} -color Pink /testbench/loggers add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/FlushStage TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {95120 ns} 1} {{Cursor 4} {95125 ns} 0} {{Cursor 3} {11250 ns} 1} {{Cursor 5} {17034 ns} 1} -quietly wave cursor active 2 +WaveRestoreCursors {{Cursor 4} {89834 ns} 1} {{Cursor 4} {79055 ns} 1} {{Cursor 3} {89604 ns} 0} +quietly wave cursor active 3 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 configure wave -justifyvalue left @@ -702,4 +702,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {95018 ns} {95228 ns} +WaveRestoreZoom {89564 ns} {89776 ns} From 57fbd354842c60e4b6712cd84c33075dd7a606f2 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 12 Nov 2024 15:03:30 -0600 Subject: [PATCH 012/212] Fixed lint errors in loggers.sv with Kaitlin. --- testbench/common/loggers.sv | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index 6b026257a..89fe59ca8 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -46,11 +46,11 @@ module loggers import cvw::*; #(parameter cvw_t P, // performance counter logging logic BeginSample; logic StartSample, EndSample; - if((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED) begin : HPMCSample + if((PrintHPMCounters || BPRED_LOGGER) && P.ZICNTR_SUPPORTED) begin : HPMCSample integer HPMCindex; logic StartSampleFirst; logic StartSampleDelayed, BeginDelayed; - logic EndSampleFirst, EndSampleDelayed; + logic EndSampleFirst; logic [P.XLEN-1:0] InitialHPMCOUNTERH[P.COUNTERS-1:0]; string HPMCnames[] = '{"Mcycle", @@ -89,9 +89,18 @@ module loggers import cvw::*; #(parameter cvw_t P, EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time"; end else begin StartSampleFirst = reset; - EndSample = DCacheFlushStart & ~DCacheFlushDone; + EndSampleFirst = '0; end + // this code needs to be with embench and coremark but not the else condition + if (TEST == "embench" | TEST == "coremark") begin + logic EndSampleDelayed; + flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); + assign EndSample = EndSampleFirst & ~ EndSampleDelayed; + end else begin + assign EndSample = DCacheFlushStart & ~DCacheFlushDone; + end + /* if(TEST == "embench") begin // embench runs warmup then runs start_trigger @@ -132,8 +141,6 @@ module loggers import cvw::*; #(parameter cvw_t P, flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); assign StartSample = StartSampleFirst & ~StartSampleDelayed; - flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); - assign EndSample = EndSampleFirst & ~ EndSampleDelayed; flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed); // ** is this redundant with StartSampleReg? assign BeginSample = StartSampleFirst & ~BeginDelayed; From d5e8ecbed5dd36c6b02f11a8659fe67e31129e85 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 12 Nov 2024 15:29:05 -0600 Subject: [PATCH 013/212] Simplified the fpgatop SDCCLK logic. --- fpga/src/fpgaTop.sv | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/fpga/src/fpgaTop.sv b/fpga/src/fpgaTop.sv index 7b503e1f1..a1f4849ca 100644 --- a/fpga/src/fpgaTop.sv +++ b/fpga/src/fpgaTop.sv @@ -182,7 +182,6 @@ module fpgaTop logic [511 : 0] dbg_bus; logic CLK208; - logic SDCCLKInternal; assign GPIOIN = {25'b0, SDCCD, SDCWP, 2'b0, GPI}; assign GPO = GPIOOUT[4:0]; @@ -216,7 +215,7 @@ module fpgaTop .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK(SDCCLK), .ExternalStall(RVVIStall)); + .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK, .ExternalStall(RVVIStall)); // ahb lite to axi bridge From 8659d6efdb48e08d0a1f989ac1b03979656df3bb Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 12 Nov 2024 17:24:06 -0600 Subject: [PATCH 014/212] Resolved all CacheSim.py vs Wally mismaches. --- sim/rv64gc_CacheSim.py | 2 +- testbench/common/loggers.sv | 13 +++++++------ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/sim/rv64gc_CacheSim.py b/sim/rv64gc_CacheSim.py index 6f9d575e1..5fe281bb4 100755 --- a/sim/rv64gc_CacheSim.py +++ b/sim/rv64gc_CacheSim.py @@ -56,7 +56,7 @@ tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "ar # arch64i is the most interesting case. Uncomment line below to run just that case #tests64gc = ["arch64i"] #tests64gc = ["coverage64gc"] -tests64gc = ["wally64priv"] +#tests64gc = ["wally64priv"] cachetypes = ["ICache", "DCache"] simdir = os.path.expandvars("$WALLY/sim") diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index 0307675d6..2884081ff 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -210,15 +210,16 @@ module loggers import cvw::*; #(parameter cvw_t P, dut.core.lsu.LSUAtomicM[1] ? "A" : dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" : - dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b1000 ? "Z" : // cmo.zero - dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0001 ? "V" : // cmo.inval should just clear the valid and dirty bits - dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0010 ? "C" : // cmo.clean should act like a read in terms of the lru, but clears the dirty bit - dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0100 ? "L" : // cmo.flush should just clear and the valid and drity bits + dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b1000 ? "Z" : // cbo.zero + dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0001 ? "V" : // cbo.inval should just clear the valid and dirty bits + dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0010 ? "C" : // cbo.clean should act like a read in terms of the lru, but clears the dirty bit + dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0100 ? "L" : // cbo.flush should just clear and the valid and drity bits "NULL"; end - assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn | AccessTypeString == "Z" | - ((AccessTypeString == "C" | AccessTypeString == "L" | AccessTypeString == "V") & dut.core.lsu.bus.dcache.dcache.cachefsm.CacheStall == 0)) & + assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn | + // don't include cbo.zero as it uses LRUWriteEn to update the LRU and would be double counted. + ((AccessTypeString == "C" | AccessTypeString == "L" | AccessTypeString == "V") & ~dut.core.lsu.bus.dcache.dcache.cachefsm.CacheStall)) & ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable & dut.core.lsu.bus.dcache.dcache.cachefsm.CacheEn & From 7868af0f8180fa09d35af785ef199555c85cd498 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 12 Nov 2024 17:43:09 -0600 Subject: [PATCH 015/212] Code cleanup. --- sim/rv64gc_CacheSim.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sim/rv64gc_CacheSim.py b/sim/rv64gc_CacheSim.py index 5fe281bb4..87616edd0 100755 --- a/sim/rv64gc_CacheSim.py +++ b/sim/rv64gc_CacheSim.py @@ -49,8 +49,8 @@ class bcolors: BOLD = '\033[1m' UNDERLINE = '\033[4m' -tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zcb", - "arch64zifencei", "arch64zicond", "arch64a_amo", "wally64a_lrsc", "wally64periph", "wally64priv", +tests64gc = ["coverage64gc", "wally64priv", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zcb", + "arch64zifencei", "arch64zicond", "arch64a_amo", "wally64a_lrsc", "wally64periph", "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"] # arch64i is the most interesting case. Uncomment line below to run just that case From b8cafb51982de21438c11568393bec9ac60ca860 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 12 Nov 2024 17:51:22 -0600 Subject: [PATCH 016/212] More code cleanup. --- bin/CacheSim.py | 26 ++++++++------------------ 1 file changed, 8 insertions(+), 18 deletions(-) diff --git a/bin/CacheSim.py b/bin/CacheSim.py index d5bf1cd5d..5a2499a87 100755 --- a/bin/CacheSim.py +++ b/bin/CacheSim.py @@ -88,20 +88,19 @@ class Cache: # invalidate this specific line def cboinvalidate(self, addr): tag, setnum, _ = self.splitaddr(addr) - #print(f"In cboinvalidate addr is {addr:x} Set is {setnum}") for waynum in range(self.numways): line = self.ways[waynum][setnum] if line.tag == tag and line.valid: line.dirty = 0 line.valid = 0 - def cboclean(self, addr): + def cboclean(self, addr, invalidate): tag, setnum, _ = self.splitaddr(addr) - #print(f"In cboclean addr is {addr:x} Set is {setnum}") for waynum in range(self.numways): line = self.ways[waynum][setnum] if line.tag == tag and line.valid: line.dirty = 0 + if invalidate: line.valid = 0 # invalidates the cache by setting all valid bits to False def invalidate(self): @@ -126,17 +125,14 @@ class Cache: # performs a cache access with the given address. # returns a character representing the outcome: # H/M/E/D - hit, miss, eviction, or eviction with writeback - def cacheaccess(self, addr, write=False, clean=False): + def cacheaccess(self, addr, write=False): tag, setnum, _ = self.splitaddr(addr) # check our ways to see if we have a hit - #print(f"addr is {addr:x} Set is {setnum}") - #if clean: - # print("This was a cbo.clean") for waynum in range(self.numways): line = self.ways[waynum][setnum] if line.tag == tag and line.valid: - line.dirty = 0 if clean else line.dirty or write + line.dirty = line.dirty or write self.update_pLRU(waynum, setnum) return 'H' @@ -153,7 +149,6 @@ class Cache: # we need to evict. Select a victim and overwrite. victim = self.getvictimway(setnum) - #print(f"addr is {addr:x} Victim is {victim} Set is {setnum}") line = self.ways[victim][setnum] prevdirty = line.dirty line.tag = tag @@ -265,21 +260,16 @@ def main(): cache.invalidate() if args.verbose: print("I") - elif lninfo[1] == 'V' or lninfo[1] == 'L': + elif lninfo[1] == 'V' or lninfo[1] == 'L' or lninfo[1] == 'C': addr = int(lninfo[0], 16) - cache.cboinvalidate(addr) + IsCBOClean = lninfo[1] != 'C' + cache.cboclean(addr, IsCBOClean) if args.verbose: print(lninfo[1]); - elif lninfo[1] == 'C': - addr = int(lninfo[0], 16) - cache.cboclean(addr) - if args.verbose: - print("C"); else: addr = int(lninfo[0], 16) iswrite = lninfo[1] == 'W' or lninfo[1] == 'A' or lninfo[1] == 'Z' - iscboclean = False - result = cache.cacheaccess(addr, iswrite, iscboclean) + result = cache.cacheaccess(addr, iswrite) if args.verbose: tag, setnum, offset = cache.splitaddr(addr) From 5346680758eaaba9e4bc473b5a798a0a29ef8551 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 12 Nov 2024 17:52:16 -0600 Subject: [PATCH 017/212] Final code cleanup. --- bin/CacheSim.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/CacheSim.py b/bin/CacheSim.py index 5a2499a87..57a05019f 100755 --- a/bin/CacheSim.py +++ b/bin/CacheSim.py @@ -94,7 +94,7 @@ class Cache: line.dirty = 0 line.valid = 0 - def cboclean(self, addr, invalidate): + def cbo(self, addr, invalidate): tag, setnum, _ = self.splitaddr(addr) for waynum in range(self.numways): line = self.ways[waynum][setnum] @@ -263,7 +263,7 @@ def main(): elif lninfo[1] == 'V' or lninfo[1] == 'L' or lninfo[1] == 'C': addr = int(lninfo[0], 16) IsCBOClean = lninfo[1] != 'C' - cache.cboclean(addr, IsCBOClean) + cache.cbo(addr, IsCBOClean) if args.verbose: print(lninfo[1]); else: From dcaef2080bd2bfeeaad9d96efde1c60d44308713 Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Tue, 12 Nov 2024 19:09:50 -0800 Subject: [PATCH 018/212] Add ZicsrF coverage to fcov --- config/rv32gc/coverage.svh | 1 + config/rv64gc/coverage.svh | 1 + 2 files changed, 2 insertions(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 97496a8b9..5fecf733a 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -25,5 +25,6 @@ // Privileged extensions `include "ZicsrM_coverage.svh" +`include "ZicsrF_coverage.svh" `include "RV32VM_coverage.svh" `include "RV32VM_PMP_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index d54a342dd..c021cddb1 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -26,6 +26,7 @@ // Privileged extensions `include "RV64VM_coverage.svh" `include "ZicsrM_coverage.svh" +`include "ZicsrF_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" From 8993432928a0cdce85281735e926ccb356ef9cb4 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 12 Nov 2024 23:57:30 -0600 Subject: [PATCH 019/212] Resolved issue with questa not liking the TEST +arg as a generate. --- testbench/common/loggers.sv | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index 89fe59ca8..287d02346 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -52,6 +52,7 @@ module loggers import cvw::*; #(parameter cvw_t P, logic StartSampleDelayed, BeginDelayed; logic EndSampleFirst; logic [P.XLEN-1:0] InitialHPMCOUNTERH[P.COUNTERS-1:0]; + logic EndSampleDelayed; string HPMCnames[] = '{"Mcycle", "------", @@ -80,6 +81,7 @@ module loggers import cvw::*; #(parameter cvw_t P, "Divide Cycles" }; + always_comb if (TEST == "embench") begin StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger"; @@ -93,13 +95,21 @@ module loggers import cvw::*; #(parameter cvw_t P, end // this code needs to be with embench and coremark but not the else condition +/* -----\/----- EXCLUDED -----\/----- if (TEST == "embench" | TEST == "coremark") begin - logic EndSampleDelayed; - flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); assign EndSample = EndSampleFirst & ~ EndSampleDelayed; end else begin assign EndSample = DCacheFlushStart & ~DCacheFlushDone; end + -----/\----- EXCLUDED -----/\----- */ + + flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); + always_comb + if (TEST == "embench" | TEST == "coremark") begin + EndSample = EndSampleFirst & ~ EndSampleDelayed; + end else begin + EndSample = DCacheFlushStart & ~DCacheFlushDone; + end /* if(TEST == "embench") begin From 2fe73f8174a5a860ef7e5d89a80b56d7f39c62ac Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 13 Nov 2024 00:02:51 -0600 Subject: [PATCH 020/212] Replaced double | and & with single. We were having issues with these verilator giving a warning about the parameter widths not matching. However the warning is not occuring anymore. --- testbench/common/loggers.sv | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index 287d02346..0bd0f00a7 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -46,7 +46,7 @@ module loggers import cvw::*; #(parameter cvw_t P, // performance counter logging logic BeginSample; logic StartSample, EndSample; - if((PrintHPMCounters || BPRED_LOGGER) && P.ZICNTR_SUPPORTED) begin : HPMCSample + if((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED) begin : HPMCSample integer HPMCindex; logic StartSampleFirst; logic StartSampleDelayed, BeginDelayed; @@ -94,15 +94,6 @@ module loggers import cvw::*; #(parameter cvw_t P, EndSampleFirst = '0; end - // this code needs to be with embench and coremark but not the else condition -/* -----\/----- EXCLUDED -----\/----- - if (TEST == "embench" | TEST == "coremark") begin - assign EndSample = EndSampleFirst & ~ EndSampleDelayed; - end else begin - assign EndSample = DCacheFlushStart & ~DCacheFlushDone; - end - -----/\----- EXCLUDED -----/\----- */ - flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); always_comb if (TEST == "embench" | TEST == "coremark") begin From db3a7d5bbda6705e9b4082c3b17a38f839580ad8 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 13 Nov 2024 10:45:33 -0600 Subject: [PATCH 021/212] More code cleanup for CacheSim.py --- bin/CacheSim.py | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/bin/CacheSim.py b/bin/CacheSim.py index 57a05019f..2ac8b5461 100755 --- a/bin/CacheSim.py +++ b/bin/CacheSim.py @@ -85,15 +85,7 @@ class Cache: for line in way: line.dirty = False - # invalidate this specific line - def cboinvalidate(self, addr): - tag, setnum, _ = self.splitaddr(addr) - for waynum in range(self.numways): - line = self.ways[waynum][setnum] - if line.tag == tag and line.valid: - line.dirty = 0 - line.valid = 0 - + # access a cbo type instruction def cbo(self, addr, invalidate): tag, setnum, _ = self.splitaddr(addr) for waynum in range(self.numways): From e22f30ec14b21f6ccc78a3510bd1121a7e9144e7 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 13 Nov 2024 12:24:35 -0600 Subject: [PATCH 022/212] Better name for CacheSetTag2. --- src/cache/cache.sv | 12 ++++++------ src/cache/cacheLRU.sv | 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index d6a68d5d1..7307c233e 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -75,9 +75,9 @@ module cache import cvw::*; #(parameter cvw_t P, logic SelAdrData; logic SelAdrTag; logic [1:0] AdrSelMuxSelData; - logic [1:0] AdrSelMuxSelTag, AdrSelMuxSelTag2; + logic [1:0] AdrSelMuxSelTag, AdrSelMuxSelLRU; logic [SETLEN-1:0] CacheSetData; - logic [SETLEN-1:0] CacheSetTag, CacheSetTag2; + logic [SETLEN-1:0] CacheSetTag, CacheSetLRU; logic [LINELEN-1:0] LineWriteData; logic ClearDirty, SetDirty, SetValid, ClearValid; logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0]; @@ -117,9 +117,9 @@ module cache import cvw::*; #(parameter cvw_t P, mux3 #(SETLEN) AdrSelMuxTag(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr, AdrSelMuxSelTag, CacheSetTag); - assign AdrSelMuxSelTag2 = {FlushCache, ((SelAdrTag | SelHPTW | Stall) & ~((READ_ONLY_CACHE == 1) & FlushStage))}; - mux3 #(SETLEN) AdrSelMuxTag2(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr, - AdrSelMuxSelTag2, CacheSetTag2); + assign AdrSelMuxSelLRU = {FlushCache, ((SelAdrTag | SelHPTW | Stall) & ~((READ_ONLY_CACHE == 1) & FlushStage))}; + mux3 #(SETLEN) AdrSelMuxLRU(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr, + AdrSelMuxSelLRU, CacheSetLRU); // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(P, PA_BITS, XLEN, NUMSETS, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( @@ -130,7 +130,7 @@ module cache import cvw::*; #(parameter cvw_t P, // Select victim way for associative caches if(NUMWAYS > 1) begin:vict cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMSETS) cacheLRU( - .clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSetTag(CacheSetTag2), .LRUWriteEn, + .clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSetLRU, .LRUWriteEn, .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache); end else assign VictimWay = 1'b1; // one hot. diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 7f1904bbd..a91e7232c 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -36,7 +36,7 @@ module cacheLRU input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant input logic [NUMWAYS-1:0] HitWay, // Which way is valid and matches PAdr's tag input logic [NUMWAYS-1:0] ValidWay, // Which ways for a particular set are valid, ignores tag - input logic [SETLEN-1:0] CacheSetTag, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr + input logic [SETLEN-1:0] CacheSetLRU, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr input logic [SETLEN-1:0] PAdr, // Physical address input logic LRUWriteEn, // Update the LRU state input logic SetValid, // Set the dirty bit in the selected way and set @@ -142,8 +142,8 @@ module cacheLRU else if (CacheEn & LRUWriteEn) LRUMemory[PAdr] <= NextLRU; // LRU read path with write forwarding - assign ReadLRU = LRUMemory[CacheSetTag]; - assign ForwardLRU = LRUWriteEn & (PAdr == CacheSetTag); + assign ReadLRU = LRUMemory[CacheSetLRU]; + assign ForwardLRU = LRUWriteEn & (PAdr == CacheSetLRU); mux2 #(NUMWAYS-1) ReadLRUmux(ReadLRU, NextLRU, ForwardLRU, BypassedLRU); flop #(NUMWAYS-1) CurrLRUReg(clk, BypassedLRU, CurrLRU); endmodule From a7dd2eff016e77ba522623cf22f2734bee340209 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 13 Nov 2024 12:29:02 -0600 Subject: [PATCH 023/212] Switch rv64gc_CacheSim.py to use verilator as the default sim rather than questa. --- sim/rv64gc_CacheSim.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/rv64gc_CacheSim.py b/sim/rv64gc_CacheSim.py index 87616edd0..9de361237 100755 --- a/sim/rv64gc_CacheSim.py +++ b/sim/rv64gc_CacheSim.py @@ -65,7 +65,7 @@ def main(): parser = argparse.ArgumentParser(description="Runs the cache simulator on all rv64gc test suites") parser.add_argument('-p', "--perf", action='store_true', help="Report hit/miss ratio") parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations") - parser.add_argument('-s', "--sim", help="Simulator", choices=["questa", "verilator", "vcs"], default="questa") + parser.add_argument('-s', "--sim", help="Simulator", choices=["questa", "verilator", "vcs"], default="verilator") args = parser.parse_args() simargs = "I_CACHE_ADDR_LOGGER=1\\\'b1 D_CACHE_ADDR_LOGGER=1\\\'b1" testcmd = "wsim --sim " + args.sim + " rv64gc {} --params \"" + simargs + "\" > /dev/null" From 88745e27d31d935b8a77867cdb34257b195d1cde Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 13 Nov 2024 12:57:02 -0600 Subject: [PATCH 024/212] Fixed ila after updates. --- fpga/constraints/big-debug-spi.xdc | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/fpga/constraints/big-debug-spi.xdc b/fpga/constraints/big-debug-spi.xdc index b5318e7d2..4584d7d0d 100644 --- a/fpga/constraints/big-debug-spi.xdc +++ b/fpga/constraints/big-debug-spi.xdc @@ -179,9 +179,9 @@ set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitRegLoaded}]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe31] +set_property port_width 4 [get_debug_ports u_ila_0/probe31] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] -connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/PhaseOneOffset}]] +connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[3]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe32] @@ -254,10 +254,6 @@ set_property port_width 4 [get_debug_ports u_ila_0/probe45] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45] connect_debug_port u_ila_0/probe45 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[3]} ]] -create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe46] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46] -connect_debug_port u_ila_0/probe46 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[3]} ]] From 017b3e987237a35fe5d0fa573a4c8d46769c9217 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 13 Nov 2024 17:01:01 -0800 Subject: [PATCH 025/212] Fix 32 bit CSRs in wallyTracer --- testbench/common/wallyTracer.sv | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 83eeacf5f..991f6719e 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -158,7 +158,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW; - CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrm.MSTATUSH_REGW; CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW; CSRArray[12'h341] = testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW; CSRArray[12'h306] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; @@ -215,7 +214,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); CSRArray[csrid] = CSRArrayOld[csrid]; CSRArray[12'h300] = CSRArrayOld[12'h300]; - CSRArray[12'h310] = CSRArrayOld[12'h310]; CSRArray[12'h305] = CSRArrayOld[12'h305]; CSRArray[12'h341] = CSRArrayOld[12'h341]; CSRArray[12'h306] = CSRArrayOld[12'h306]; @@ -255,6 +253,11 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); CSRArray[12'h001] = CSRArrayOld[12'h001]; CSRArray[12'h002] = CSRArrayOld[12'h002]; CSRArray[12'h003] = CSRArrayOld[12'h003]; + if (P.XLEN == 32) begin + CSRArray[12'h310] = CSRArrayOld[12'h310]; + CSRArray[12'h31A] = CSRArrayOld[12'h31A]; + CSRArray[12'h15D] = CSRArrayOld[12'h15D]; + end end end @@ -347,7 +350,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); integer index4; always_ff @(posedge clk) begin CSRArrayOld[12'h300] = CSRArray[12'h300]; - CSRArrayOld[12'h310] = CSRArray[12'h310]; CSRArrayOld[12'h305] = CSRArray[12'h305]; CSRArrayOld[12'h341] = CSRArray[12'h341]; CSRArrayOld[12'h306] = CSRArray[12'h306]; @@ -387,6 +389,11 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); CSRArrayOld[12'h001] = CSRArray[12'h001]; CSRArrayOld[12'h002] = CSRArray[12'h002]; CSRArrayOld[12'h003] = CSRArray[12'h003]; + if (P.XLEN == 32) begin + CSRArrayOld[12'h310] = CSRArray[12'h310]; + CSRArrayOld[12'h31A] = CSRArray[12'h31A]; + CSRArrayOld[12'h15D] = CSRArray[12'h15D]; + end // PMP CFG 3A0 to 3AF for(index4='h3A0; index4<='h3AF; index4++) @@ -399,7 +406,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); // check for csr value change. assign CSR_W[12'h300] = (CSRArrayOld[12'h300] != CSRArray[12'h300]) ? 1 : 0; - assign CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0; assign CSR_W[12'h305] = (CSRArrayOld[12'h305] != CSRArray[12'h305]) ? 1 : 0; assign CSR_W[12'h341] = (CSRArrayOld[12'h341] != CSRArray[12'h341]) ? 1 : 0; assign CSR_W[12'h306] = (CSRArrayOld[12'h306] != CSRArray[12'h306]) ? 1 : 0; @@ -436,9 +442,13 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0; assign CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0; assign CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0; + if (P.XLEN == 32) begin + assign CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0; + assign CSR_W[12'h31A] = (CSRArrayOld[12'h31A] != CSRArray[12'h31A]) ? 1 : 0; + assign CSR_W[12'h15D] = (CSRArrayOld[12'h15D] != CSRArray[12'h15D]) ? 1 : 0; + end assign rvvi.csr_wb[0][0][12'h300] = CSR_W[12'h300]; - assign rvvi.csr_wb[0][0][12'h310] = CSR_W[12'h310]; assign rvvi.csr_wb[0][0][12'h305] = CSR_W[12'h305]; assign rvvi.csr_wb[0][0][12'h341] = CSR_W[12'h341]; assign rvvi.csr_wb[0][0][12'h306] = CSR_W[12'h306]; @@ -475,9 +485,13 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001]; assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002]; assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003]; + if (P.XLEN == 32) begin + assign rvvi.csr_wb[0][0][12'h310] = CSR_W[12'h310]; + assign rvvi.csr_wb[0][0][12'h31A] = CSR_W[12'h31A]; + assign rvvi.csr_wb[0][0][12'h15D] = CSR_W[12'h15D]; + end assign rvvi.csr[0][0][12'h300] = CSRArray[12'h300]; - assign rvvi.csr[0][0][12'h310] = CSRArray[12'h310]; assign rvvi.csr[0][0][12'h305] = CSRArray[12'h305]; assign rvvi.csr[0][0][12'h341] = CSRArray[12'h341]; assign rvvi.csr[0][0][12'h306] = CSRArray[12'h306]; @@ -514,6 +528,11 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign rvvi.csr[0][0][12'h001] = CSRArray[12'h001]; assign rvvi.csr[0][0][12'h002] = CSRArray[12'h002]; assign rvvi.csr[0][0][12'h003] = CSRArray[12'h003]; + if (P.XLEN == 32) begin + assign rvvi.csr[0][0][12'h310] = CSRArray[12'h310]; + assign rvvi.csr[0][0][12'h31A] = CSRArray[12'h31A]; + assign rvvi.csr[0][0][12'h15D] = CSRArray[12'h15D]; + end // PMP CFG 3A0 to 3AF for(index='h3A0; index<='h3AF; index++) begin From d666a0dd7b1c2faa7b02664049d9200ed9f8bb03 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 13 Nov 2024 18:26:53 -0800 Subject: [PATCH 026/212] Update formatting in an attempt to understand what's happening in this file --- testbench/common/wallyTracer.sv | 388 ++++++++++++++++---------------- 1 file changed, 193 insertions(+), 195 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 991f6719e..b4089f70b 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -35,37 +35,36 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); localparam NUMREGS = P.E_SUPPORTED ? 16 : 32; // wally specific signals - logic reset; - logic clk; - logic InstrValidD, InstrValidE; - logic StallF, StallD; - logic STATUS_SXL, STATUS_UXL; - logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW; - logic [31:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW; - logic InstrValidM, InstrValidW; - logic StallE, StallM, StallW; - logic FlushD, FlushE, FlushM, FlushW; - logic TrapM, TrapW; - logic HaltM, HaltW; - logic [1:0] PrivilegeModeW; - logic [P.XLEN-1:0] rf[NUMREGS]; - logic [NUMREGS-1:0] rf_wb; - logic [4:0] rf_a3; - logic rf_we3; - logic [P.FLEN-1:0] frf[32]; - logic [`NUM_REGS-1:0] frf_wb; - logic [4:0] frf_a4; - logic frf_we4; - logic [P.XLEN-1:0] CSRArray [4095:0]; - logic [P.XLEN-1:0] CSRArrayOld [4095:0]; - logic [`NUM_CSRS-1:0] CSR_W; - logic CSRWriteM, CSRWriteW; - logic [11:0] CSRAdrM, CSRAdrW; - logic wfiM; - logic InterruptM, InterruptW; + logic reset; + logic clk; + logic InstrValidD, InstrValidE; + logic StallF, StallD; + logic STATUS_SXL, STATUS_UXL; + logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW; + logic [31:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW; + logic InstrValidM, InstrValidW; + logic StallE, StallM, StallW; + logic FlushD, FlushE, FlushM, FlushW; + logic TrapM, TrapW; + logic HaltM, HaltW; + logic [1:0] PrivilegeModeW; + logic [P.XLEN-1:0] rf[NUMREGS]; + logic [NUMREGS-1:0] rf_wb; + logic [4:0] rf_a3; + logic rf_we3; + logic [P.FLEN-1:0] frf[32]; + logic [`NUM_REGS-1:0] frf_wb; + logic [4:0] frf_a4; + logic frf_we4; + logic [P.XLEN-1:0] CSRArray [4095:0]; + logic [P.XLEN-1:0] CSRArrayOld [4095:0]; + logic [`NUM_CSRS-1:0] CSR_W; + logic CSRWriteM, CSRWriteW; + logic [11:0] CSRAdrM, CSRAdrW; + logic wfiM; + logic InterruptM, InterruptW; //For VM Verification - logic [(P.XLEN-1):0] VAdrIM,VAdrDM,VAdrIW,VAdrDW; logic [(P.XLEN-1):0] PTE_iM,PTE_dM,PTE_iW,PTE_dW; logic [(P.PA_BITS-1):0] PAIM,PADM,PAIW,PADW; @@ -73,7 +72,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW; logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW; - assign clk = testbench.dut.clk; // assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet assign InstrValidD = testbench.dut.core.ieu.c.InstrValidD; @@ -103,7 +101,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign wfiM = testbench.dut.core.priv.priv.wfiM; assign InterruptM = testbench.dut.core.priv.priv.InterruptM; - //FOr VM Verification + //For VM Verification assign VAdrIM = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr; assign VAdrDM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr; assign PAIM = testbench.dut.core.ifu.immu.immu.PhysicalAddress; @@ -116,21 +114,17 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; - - logic valid; int csrid; always_comb begin - // Since we are detected the CSR change by comparing the old value we need to - // ensure the CSR is detected when the pipeline's Writeback stage is not - // stalled. If it is stalled we want CSRArray to hold the old value. - if(valid) begin - // machine CSRs - // *** missing PMP and performance counters. - + // Since we are detected the CSR change by comparing the old value we need to + // ensure the CSR is detected when the pipeline's Writeback stage is not + // stalled. If it is stalled we want CSRArray to hold the old value. + if(valid) begin + // machine CSRs // PMPCFG space is 0-15 3a0 - 3af - int i, i4, i8, csrid; + int i, i4, i8, csrid; logic [P.XLEN-1:0] pmp; for (i=0; i Date: Wed, 13 Nov 2024 22:12:11 -0800 Subject: [PATCH 027/212] pmps working for RVVI in RV32 --- testbench/common/wallyTracer.sv | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index b4089f70b..b4bf68a36 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -124,11 +124,13 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); if(valid) begin // machine CSRs // PMPCFG space is 0-15 3a0 - 3af + int inc = P.XLEN == 32 ? 4 : 8; int i, i4, i8, csrid; logic [P.XLEN-1:0] pmp; - for (i=0; i Date: Thu, 14 Nov 2024 03:51:27 -0800 Subject: [PATCH 028/212] added handling for OpCode=100 --- src/fpu/fcmp.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/src/fpu/fcmp.sv b/src/fpu/fcmp.sv index d1baac3b8..682e492be 100755 --- a/src/fpu/fcmp.sv +++ b/src/fpu/fcmp.sv @@ -75,6 +75,7 @@ module fcmp import cvw::*; #(parameter cvw_t P) ( 3'b0?1: if (P.ZFA_SUPPORTED) CmpNV = Zfa ? EitherSNaN : EitherNaN; // fltq,fleq / flt,fle perform CompareQuietLess / CompareSignalingLess differing on when to set invalid else CmpNV = EitherNaN; // flt, fle + 3'b100: CmpNV = 1'b0; default: CmpNV = 1'bx; endcase end From eb777d3fa43bfe0dc5e6cb142234dae67134bb85 Mon Sep 17 00:00:00 2001 From: Vikram Krishna Date: Thu, 14 Nov 2024 03:53:26 -0800 Subject: [PATCH 029/212] updated froundnx conditional --- src/fpu/fround.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/fpu/fround.sv b/src/fpu/fround.sv index b5c1b975e..67a3b90f6 100644 --- a/src/fpu/fround.sv +++ b/src/fpu/fround.sv @@ -147,6 +147,6 @@ module fround import cvw::*; #(parameter cvw_t P) ( // Flags assign FRoundNV = XSNaN; // invalid if input is signaling NaN - assign FRoundNX = ZfaFRoundNX & ~EgeNf & (Rp | Tp); // Inexact if Round or Sticky bit set for FRoundNX instruction + assign FRoundNX = ZfaFRoundNX & ~EgeNf & (Rp | Tp) & ~XNaN; // Inexact if Round or Sticky bit set for FRoundNX instruction endmodule From 0c0949e82bd393fc7fb3d9d1e8349dd53c42e705 Mon Sep 17 00:00:00 2001 From: Vikram Krishna Date: Thu, 14 Nov 2024 03:54:32 -0800 Subject: [PATCH 030/212] added explanation --- src/fpu/fround.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/fpu/fround.sv b/src/fpu/fround.sv index 67a3b90f6..2814c766b 100644 --- a/src/fpu/fround.sv +++ b/src/fpu/fround.sv @@ -146,7 +146,8 @@ module fround import cvw::*; #(parameter cvw_t P) ( packoutput #(P) packoutput(W, Fmt, FRound); // pack and NaN-box based on selected format. // Flags - assign FRoundNV = XSNaN; // invalid if input is signaling NaN + assign FRoundNV = XSNaN; // invalid if input is signaling NaN assign FRoundNX = ZfaFRoundNX & ~EgeNf & (Rp | Tp) & ~XNaN; // Inexact if Round or Sticky bit set for FRoundNX instruction + // Note: NX must not be raised if input is invalid endmodule From d41dc8d2def2090b9e6494dad9f1d174f704d319 Mon Sep 17 00:00:00 2001 From: Ahlyssa Santillana Date: Thu, 14 Nov 2024 06:26:28 -0800 Subject: [PATCH 031/212] incorportated Zicsr to run in Imperas --- config/rv32gc/coverage.svh | 1 + config/rv64gc/coverage.svh | 1 + 2 files changed, 2 insertions(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 39e174412..776f8ef9f 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -26,6 +26,7 @@ `include "RV32ZcbZbb_coverage.svh" `include "RV32Zcf_coverage.svh" `include "RV32Zcd_coverage.svh" +`include "RV32Zicsr_coverage.svh" // Privileged extensions `include "ZicsrM_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 0ab6f76a7..b7c83483a 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -26,6 +26,7 @@ `include "RV64ZcbZbb_coverage.svh" `include "RV64ZcbZba_coverage.svh" `include "RV64Zcd_coverage.svh" +`include "RV64Zicsr_coverage.svh" // Privileged extensions `include "RV64VM_coverage.svh" From eacc8c0f072dd0f45860d7b18d9e21ead68b5472 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 14 Nov 2024 08:14:22 -0800 Subject: [PATCH 032/212] Define XLEN32/XLEN64 in coverage configuration --- config/rv32gc/coverage.svh | 3 +++ config/rv64gc/coverage.svh | 3 +++ 2 files changed, 6 insertions(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 97496a8b9..3952b1032 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -5,6 +5,9 @@ // This file is needed in the config subdirectory for each config supporting coverage. // It defines which extensions are enabled for that config. +// Define XLEN, used in covergroups +`define XLEN32 1 + // Unprivileged extensions `include "RV32I_coverage.svh" `include "RV32M_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index d54a342dd..bbc6590c3 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -5,6 +5,9 @@ // This file is needed in the config subdirectory for each config supporting coverage. // It defines which extensions are enabled for that config. +// Define XLEN, used in covergroups +`define XLEN64 1 + // Unprivileged extensions `include "RV64I_coverage.svh" `include "RV64M_coverage.svh" From 054c694a2782ac8b5c3640a7e0ab792c49d2469a Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 14 Nov 2024 08:14:56 -0800 Subject: [PATCH 033/212] Fixed typo of CLINT name --- tests/coverage/WALLY-init-lib.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h index dd29bbab8..28a7510a1 100644 --- a/tests/coverage/WALLY-init-lib.h +++ b/tests/coverage/WALLY-init-lib.h @@ -77,7 +77,7 @@ trap_handler: interrupt: # must be a timer interrupt li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again - li t1, 0x02004000 # MTIMECMP in CLIN + li t1, 0x02004000 # MTIMECMP in CLINT sd t0, 0(t1) csrw stimecmp, t0 # sets stimecmp to big number so it doesnt interrupt li t0, 32 From 4251f0c6a2bf2e532f6a342a63c405e9843e255f Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 14 Nov 2024 10:56:13 -0800 Subject: [PATCH 034/212] Restored to original WALLY-init-lib beause new flavor is moved to cvw-arch-verif and the old is needed for PMP code coverage --- tests/coverage/WALLY-init-lib.h | 65 +++++++++++---------------------- 1 file changed, 22 insertions(+), 43 deletions(-) diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h index 28a7510a1..59245bb2c 100644 --- a/tests/coverage/WALLY-init-lib.h +++ b/tests/coverage/WALLY-init-lib.h @@ -7,20 +7,20 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw -// +// // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You // may obtain a copy of the License at // // https://solderpad.org/licenses/SHL-2.1/ // -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// @@ -28,12 +28,6 @@ // The PMP tests are sensitive to the exact addresses in this code, so unfortunately // modifying anything breaks those tests. -// Provides simple firmware services through ecall. Place argument in a0 and issue ecall: -// 0: change to user mode -// 1: change to supervisor mode -// 3: change to machine mode -// 4: terminate program - .section .text.init .global rvtest_entry_point @@ -47,21 +41,21 @@ rvtest_entry_point: csrw medeleg, zero # Don't delegate exceptions # li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again # li t1, 0x02004000 # MTIMECMP in CLINT -# sd t0, 0(t1) - li t0, 0x80 -# li t0, 0x00 +# sd t0, 0(t1) + li t0, 0x80 +# li t0, 0x00 csrw mie, t0 # Enable machine timer interrupt - la t0, topoftrapstack + la t0, topoftrapstack csrw mscratch, t0 # MSCRATCH holds trap stack pointer csrsi mstatus, 0x8 # Turn on mstatus.MIE global interrupt enable # set up PMP so user and supervisor mode can access full address space csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX - li t0, 0xFFFFFFFF + li t0, 0xFFFFFFFF csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses j main # Call main function in user test program done: - li a0, 4 # argument to finish program + li a0, 4 # argument to finish program ecall # system call to finish program j self_loop # wait forever (not taken) @@ -75,11 +69,11 @@ trap_handler: csrr t1, mtval # And the trap value bgez t0, exception # if msb is clear, it is an exception -interrupt: # must be a timer interrupt +interrupt: # must be a timer interrupt li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again - li t1, 0x02004000 # MTIMECMP in CLINT - sd t0, 0(t1) - csrw stimecmp, t0 # sets stimecmp to big number so it doesnt interrupt + li t1, 0x02004000 # MTIMECMP in CLIN + sd t0, 0(t1) + csrw stimecmp, t0 # sets stimecmp to big number so it doesnt interrupt li t0, 32 csrc sip, t0 # clears stimer interrupt j trap_return # clean up and return @@ -105,7 +99,7 @@ changeprivilege: trap_return: # return from trap handler csrr t0, mepc # get address of instruction that caused exception - li t1, 0x20000 + li t1, 0x20000 csrs mstatus, t1 # set mprv bit to fetch instruction with permission of code that trapped lh t0, 0(t0) # get instruction that caused exception csrc mstatus, t1 # clear mprv bit to restore normal operation @@ -133,20 +127,8 @@ write_tohost: self_loop: j self_loop # wait - -// utility routines - -# put a 1 in msb of a0 (position XLEN-1); works for both RV32 and RV64 -setmsb: - li a0, 0x80000000 # 1 in bit 31 - slli a1, a0, 1 # check if register is wider than 31 bits - beqz a1, setmsbdone # yes, a0 has 1 in bit 31 - slli a0, a0, 16 # no: shift a0 to have 1 inn bit 63 - slli a0, a0, 16 # use two shifts of 16 bits each to be compatible with compiling either RV32 or 64 -setmsbdone: - ret # return to calller - -.section .tohost + +.section .tohost tohost: # write to HTIF .dword 0 fromhost: @@ -154,20 +136,17 @@ fromhost: .EQU XLEN,64 begin_signature: - .fill 6*(XLEN/32),4,0xdeadbeef # + .fill 6*(XLEN/32),4,0xdeadbeef # end_signature: -scratch: - .fill 4,4,0x0 - # Initialize stack with room for 512 bytes .bss .space 512 topofstack: # And another stack for the trap handler -.bss +.bss .space 512 topoftrapstack: .align 4 -.section .text.main +.section .text.main \ No newline at end of file From 872491716d93e17454e1571b2016c384fb3c6318 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 14 Nov 2024 11:57:14 -0800 Subject: [PATCH 035/212] set ZICCLSM_SUPPORTED to 0 so that nocache_rv64gc does not fail assertion tests --- config/derivlist.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/config/derivlist.txt b/config/derivlist.txt index 7e6cd6909..a82339cfc 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -444,6 +444,7 @@ DCACHE_SUPPORTED 0 VIRTMEM_SUPPORTED 0 ZICBOM_SUPPORTED 0 ZICBOZ_SUPPORTED 0 +ZICCLSM_SUPPORTED 0 SVPBMT_SUPPORTED 0 SVNAPOT_SUPPORTED 0 ZAAMO_SUPPORTED 0 @@ -455,6 +456,7 @@ DCACHE_SUPPORTED 0 VIRTMEM_SUPPORTED 0 ZICBOM_SUPPORTED 0 ZICBOZ_SUPPORTED 0 +ZICCLSM_SUPPORTED 0 SVPBMT_SUPPORTED 0 SVNAPOT_SUPPORTED 0 ZAAMO_SUPPORTED 0 From 5e4f4c2072e8fe5258067c70e5a0555919b8b6b3 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 14 Nov 2024 16:14:02 -0600 Subject: [PATCH 036/212] Simple change to ensure Trapped instructions are included with rvvi as valid instructions. Required for functional coverage. --- testbench/common/wallyTracer.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 83eeacf5f..77b1c42d5 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -319,7 +319,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); // Initially connecting the writeback stage signals, but may need to use M stage // and gate on ~FlushW. - assign valid = InstrValidW & ~StallW & ~reset; + assign valid = ((InstrValidW | TrapW) & ~StallW) & ~reset; assign rvvi.clk = clk; assign rvvi.valid[0][0] = valid; assign rvvi.order[0][0] = CSRArray[12'hB02]; // TODO: IMPERAS Should be event order @@ -546,7 +546,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end always_ff @(posedge clk) begin - if(rvvi.valid[0][0]) begin + if(valid) begin if(`STD_LOG) begin $fwrite(file, "%016x, %08x, %s\t\t", rvvi.pc_rdata[0][0], rvvi.insn[0][0], instrWName); for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin From 61c5d035e9cf3f6e6bebb24598867e767a993a2c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 14 Nov 2024 15:03:13 -0800 Subject: [PATCH 037/212] Add mseccfg shell to wallyTracer and reformat CSRs --- testbench/common/wallyTracer.sv | 453 ++++++++++++++++++++------------ 1 file changed, 290 insertions(+), 163 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index b4bf68a36..7f8e43cdd 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -122,8 +122,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); // ensure the CSR is detected when the pipeline's Writeback stage is not // stalled. If it is stalled we want CSRArray to hold the old value. if(valid) begin - // machine CSRs - // PMPCFG space is 0-15 3a0 - 3af + // PMPCFG CSRs (space is 0-15 3a0 - 3af) int inc = P.XLEN == 32 ? 4 : 8; int i, i4, i8, csrid; logic [P.XLEN-1:0] pmp; @@ -145,7 +144,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); CSRArray[csrid] = pmp; end - // PMPADDR space is 0-63 3b0 - 3ef + // PMPADDR CSRs (space is 0-63 3b0 - 3ef) for (i=0; i Date: Thu, 14 Nov 2024 15:31:10 -0800 Subject: [PATCH 038/212] Fix wallyTracer bug --- testbench/common/wallyTracer.sv | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 21c72fec9..e2be8c7df 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -525,6 +525,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end + // M-mode trap CSRs assign rvvi.csr_wb[0][0][12'h300] = CSR_W[12'h300]; assign rvvi.csr_wb[0][0][12'h302] = CSR_W[12'h302]; @@ -593,7 +594,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); - // M-mode trap CSRs assign rvvi.csr[0][0][12'h300] = CSRArray[12'h300]; assign rvvi.csr[0][0][12'h302] = CSRArray[12'h302]; @@ -660,7 +660,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign rvvi.csr[0][0][12'h15D] = CSRArray[12'h15D]; end - + // PMP CFG 3A0 to 3AF for(index='h3A0; index<='h3AF; index++) begin assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0; @@ -735,11 +735,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end end end - end if(HaltW) $finish; end - - - endmodule From b2789f304a2af62c56000520fa270f6b3ce0b964 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Fri, 15 Nov 2024 00:39:16 -0800 Subject: [PATCH 039/212] Removing old code (not in use anymore) --- testbench/testbench.sv | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 5b053c763..b2dda03ab 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -33,12 +33,6 @@ `include "idv/idv.svh" `endif -`ifdef RVVI_COVERAGE - `include "RISCV_trace_data.svh" - `include "rvvicov.svh" - `include "wrapper.sv" -`endif - import cvw::*; module testbench; @@ -973,12 +967,6 @@ test_pmp_coverage #(P) pmp_inst(clk); /* verilator lint_on WIDTHTRUNC */ /* verilator lint_on WIDTHEXPAND */ -`ifdef RVVI_COVERAGE - rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi(); - wallyTracer #(P) wallyTracer(rvvi); - wrapper #(P) wrap(clk); -`endif - endmodule /* verilator lint_on STMTDLY */ From c02a649c3b12ca3020c0f8e3df834f2061cfa66a Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 15 Nov 2024 05:33:16 -0800 Subject: [PATCH 040/212] Fixed warnings related to tracer variables --- testbench/common/wallyTracer.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index e2be8c7df..4dd4fd29d 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -115,21 +115,21 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; logic valid; - int csrid; - + always_comb begin // Since we are detected the CSR change by comparing the old value we need to // ensure the CSR is detected when the pipeline's Writeback stage is not // stalled. If it is stalled we want CSRArray to hold the old value. if(valid) begin // PMPCFG CSRs (space is 0-15 3a0 - 3af) - int inc = P.XLEN == 32 ? 4 : 8; + localparam inc = P.XLEN == 32 ? 4 : 8; int i, i4, i8, csrid; logic [P.XLEN-1:0] pmp; for (i=0; i Date: Fri, 15 Nov 2024 05:58:30 -0800 Subject: [PATCH 041/212] Removed fcovimp support --- .gitignore | 3 --- bin/wsim | 13 ++----------- sim/questa/wally.do | 20 -------------------- 3 files changed, 2 insertions(+), 34 deletions(-) diff --git a/.gitignore b/.gitignore index 31db4f885..64fbbbf23 100644 --- a/.gitignore +++ b/.gitignore @@ -105,9 +105,6 @@ sim/questa/wkdir sim/questa/ucdb sim/questa/cov sim/questa/fcov -sim/questa/fcovrvvi -sim/questa/fcovrvvi_logs -sim/questa/fcovrvvi_ucdb sim/questa/fcov_logs sim/questa/fcov_ucdb sim/questa/riscv.ucdb diff --git a/bin/wsim b/bin/wsim index 72ec81a22..2b3849ecc 100755 --- a/bin/wsim +++ b/bin/wsim @@ -27,7 +27,6 @@ parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilat parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench") parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true") parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true") -parser.add_argument("--fcovimp", "-f2", help="Functional Coverage with Imperas licensed riscvISACOV, implies lockstep", action="store_true") parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true") parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="") parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="") @@ -70,7 +69,7 @@ if(args.lockstep and not args.testsuite.endswith('.elf') and not args.testsuite exit(1) # Validate arguments -if (args.gui or args.ccov or args.fcov or args.fcovimp or args.lockstep or args.lockstepverbose): +if (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose): if args.sim not in ["questa", "vcs"]: print("Option only supported for Questa and VCS") exit(1) @@ -88,7 +87,7 @@ if (args.tb == "testbench_fp"): if(int(args.locksteplog) >= 1): EnableLog = 1 else: EnableLog = 0 prefix = "" -if (args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp): +if (args.lockstep or args.lockstepverbose or args.fcov): if (args.sim == "questa" or args.sim == "vcs"): imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic") if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs @@ -101,12 +100,6 @@ if (args.sim == "questa"): if (args.lockstep or args.lockstepverbose): if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog) else: ImperasPlusArgs = "" - if(args.fcovimp): - CovEnableStr = "1" if int(args.covlog) > 0 else "0" - if(args.covlog >= 1): EnableLog = 1 - else: EnableLog = 0 - ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr - suffix = "" if(args.fcov): CovEnableStr = "1" if int(args.covlog) > 0 else "0"; if(args.covlog >= 1): EnableLog = 1 @@ -130,8 +123,6 @@ if (args.ccov): flags += " --ccov" if (args.fcov): flags += " --fcov" -if (args.fcovimp): - flags += " --fcovimp" # create the output sub-directories. regressionDir = WALLY + '/sim/' diff --git a/sim/questa/wally.do b/sim/questa/wally.do index c692b06e1..6f613c404 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -103,26 +103,6 @@ if {[lcheck lst "--ccov"]} { set CoverageVsimArg "-coverage" } -# if --fcovimp found set flag and remove from list -if {[lcheck lst "--fcovimp"]} { - set FunctCoverage 1 - set FCvlog "+define+INCLUDE_TRACE2COV \ - +define+IDV_INCLUDE_TRACE2COV \ - +define+COVER_BASE_RV64I \ - +define+COVER_LEVEL_DV_PR_EXT \ - +incdir+${IMPERAS_HOME}/ImpProprietary/source/host/riscvISACOV/source" - set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1" - # Uncomment various cover statements below to control which extensions get functional coverage - lappend FCdefineCOVER_EXTS "+define+COVER_RV64I" - #lappend FCdefineCOVER_EXTS "+define+COVER_RV64M" - #lappend FCdefineCOVER_EXTS "+define+COVER_RV64A" - #lappend FCdefineCOVER_EXTS "+define+COVER_RV64F" - #lappend FCdefineCOVER_EXTS "+define+COVER_RV64D" - #lappend FCdefineCOVER_EXTS "+define+COVER_RV64ZICSR" - #lappend FCdefineCOVER_EXTS "+define+COVER_RV64C" - -} - # if --fcov found set flag and remove from list if {[lcheck lst "--fcov"]} { set FunctCoverage 1 From 3596be433c44ba8afff66783eacc4a8d58f2b2b4 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 15 Nov 2024 08:31:19 -0600 Subject: [PATCH 042/212] Fixed the tracer so that traps don't clear the instruction or PC bits. --- testbench/common/wallyTracer.sv | 47 +++++++++++++++++---------------- 1 file changed, 24 insertions(+), 23 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 4dd4fd29d..bdf325b1e 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -24,7 +24,7 @@ `define NUM_CSRS 4096 `define STD_LOG 1 -`define PRINT_PC_INSTR 0 +`define PRINT_PC_INSTR 1 `define PRINT_MOST 0 `define PRINT_ALL 0 `define PRINT_CSRS 0 @@ -325,9 +325,9 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); // pipeline to writeback stage flopenrc #(32) InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE); flopenrc #(32) InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM); - flopenrc #(32) InstrRawWReg (clk, reset, FlushW, ~StallW, InstrRawM, InstrRawW); - flopenrc #(P.XLEN)PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW); - flopenrc #(1) InstrValidMReg (clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW); + flopenrc #(32) InstrRawWReg (clk, reset, FlushW & ~TrapM, ~StallW, InstrRawM, InstrRawW); + flopenrc #(P.XLEN)PCWReg (clk, reset, FlushW & ~TrapM, ~StallW, PCM, PCW); + flopenrc #(1) InstrValidMReg (clk, reset, FlushW & ~TrapM, ~StallW, InstrValidM, InstrValidW); flopenrc #(1) TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW); flopenrc #(1) InterruptWReg (clk, reset, 1'b0, ~StallW, InterruptM, InterruptW); flopenrc #(1) HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW); @@ -346,6 +346,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW); flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~StallW, ReadAccessM, ReadAccessW); flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~StallW, WriteAccessM, WriteAccessW); + // *** what is this used for? flopenrc #(1) ExecuteAccessDReg (clk, reset, FlushE, ~StallE, ExecuteAccessF, ExecuteAccessD); flopenrc #(1) ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE); flopenrc #(1) ExecuteAccessMReg (clk, reset, FlushM, ~StallM, ExecuteAccessE, ExecuteAccessM); @@ -712,26 +713,26 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end end $fwrite(file, "\n"); - end - if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST)) - $display("order = %08d, PC = %08x, insn = %08x", rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0]); - else if(`PRINT_MOST & !`PRINT_ALL) - $display("order = %08d, PC = %010x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %010x, x%02d = %016x, f%02d = %016x, csr%03x = %016x", - rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0], rf_a3, rvvi.x_wdata[0][0][rf_a3], frf_a4, rvvi.f_wdata[0][0][frf_a4], CSRAdrW, rvvi.csr[0][0][CSRAdrW]); - else if(`PRINT_ALL) begin - $display("order = %08d, PC = %08x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x", - rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0]); - for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin - $display("x%02d = %08x", index2, rvvi.x_wdata[0][0][index2]); + if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST)) + $display("order = %08d, PC = %08x, insn = %08x", rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0]); + else if(`PRINT_MOST & !`PRINT_ALL) + $display("order = %08d, PC = %010x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %010x, x%02d = %016x, f%02d = %016x, csr%03x = %016x", + rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0], rf_a3, rvvi.x_wdata[0][0][rf_a3], frf_a4, rvvi.f_wdata[0][0][frf_a4], CSRAdrW, rvvi.csr[0][0][CSRAdrW]); + else if(`PRINT_ALL) begin + $display("order = %08d, PC = %08x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x", + rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0]); + for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin + $display("x%02d = %08x", index2, rvvi.x_wdata[0][0][index2]); + end + for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin + $display("f%02d = %08x", index2, rvvi.f_wdata[0][0][index2]); + end end - for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin - $display("f%02d = %08x", index2, rvvi.f_wdata[0][0][index2]); - end - end - if (`PRINT_CSRS) begin - for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin - if(CSR_W[index2]) begin - $display("%t: CSR %03x = %x", $time(), index2, CSRArray[index2]); + if (`PRINT_CSRS) begin + for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin + if(CSR_W[index2]) begin + $display("%t: CSR %03x = %x", $time(), index2, CSRArray[index2]); + end end end end From fcf4ca1417236b763a80c22400548c30f6326fd0 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 15 Nov 2024 08:32:43 -0600 Subject: [PATCH 043/212] Disabled tracer print. --- testbench/common/wallyTracer.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index bdf325b1e..a32417737 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -24,7 +24,7 @@ `define NUM_CSRS 4096 `define STD_LOG 1 -`define PRINT_PC_INSTR 1 +`define PRINT_PC_INSTR 0 `define PRINT_MOST 0 `define PRINT_ALL 0 `define PRINT_CSRS 0 From 234e47a7c5226bf04c23f7708057d7298687d864 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 15 Nov 2024 15:37:25 -0800 Subject: [PATCH 044/212] MTIMECMP should reset to maximum value for RV32, not just for RV64 --- src/uncore/clint_apb.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv index 76735aaa6..e03745194 100644 --- a/src/uncore/clint_apb.sv +++ b/src/uncore/clint_apb.sv @@ -115,7 +115,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) ( always_ff @(posedge PCLK) if (~PRESETn) begin MSIP <= 1'b0; - MTIMECMP <= '0; + MTIMECMP <= 64'hFFFFFFFFFFFFFFFF; // Spec says MTIMECMP is not reset, but we reset to maximum value to prevent spurious timer interrupts end else if (memwrite) begin if (entry == 16'h0000) MSIP <= PWDATA[0]; if (entry == 16'h4000) From c9267929417926746258ac5f414af751e2f3b3d3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 15 Nov 2024 20:24:03 -0800 Subject: [PATCH 045/212] Update riscv-arch-test --- addins/riscv-arch-test | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 3843c736e..cd94912fe 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 3843c736e427a2b52a0d06e6220b073afa4be401 +Subproject commit cd94912fed2aab75d7d5f115b441da0813fdce8d From 2b57633217b9f1669ee16fff908d0f578803980a Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 15 Nov 2024 22:52:21 -0800 Subject: [PATCH 046/212] Switch to out of tree riscv-arch-test with VM tests + add pmp & vm tests to testbench --- addins/riscv-arch-test | 2 +- testbench/testbench.sv | 3 + testbench/tests.vh | 115 +++++++++++++++++++++ tests/riscof/sail_cSim/riscof_sail_cSim.py | 6 +- tests/riscof/spike/spike_rv32gc_isa.yaml | 2 +- 5 files changed, 122 insertions(+), 6 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index cd94912fe..a079bb263 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit cd94912fed2aab75d7d5f115b441da0813fdce8d +Subproject commit a079bb263b04dde4028efee134f3a4e42799a5ca diff --git a/testbench/testbench.sv b/testbench/testbench.sv index b2dda03ab..69cf926f5 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -175,6 +175,7 @@ module testbench; "arch64zknd": if (P.ZKND_SUPPORTED) tests = arch64zknd; "arch64zkne": if (P.ZKNE_SUPPORTED) tests = arch64zkne; "arch64zknh": if (P.ZKNH_SUPPORTED) tests = arch64zknh; + "arch64pmp": if (P.PMP_ENTRIES > 0) tests = arch64pmp; endcase end else begin // RV32 case (TEST) @@ -217,6 +218,8 @@ module testbench; "arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd; "arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne; "arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh; + "arch32pmp": if (P.PMP_ENTRIES > 0) tests = arch32pmp; + "arch32vm_sv32": if (P.VIRTMEM_SUPPORTED) tests = arch32vm_sv32; endcase end if (tests.size() == 0 & ElfFile == "none") begin diff --git a/testbench/tests.vh b/testbench/tests.vh index 2b8d3a2ec..59cd84437 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -149,6 +149,121 @@ string wally32a_lrsc[] = '{ "rv32i_m/privilege/src/WALLY-lrsc-01.S" }; +string arch32pmp[] = '{ + `RISCVARCHTEST, + "rv32i_m/pmp32/src/pmp-CFG-reg.S", + "rv32i_m/pmp32/src/pmp-CSR-access.S", + "rv32i_m/pmp32/src/pmp-NA4-R-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NA4-R-priority.S", + "rv32i_m/pmp32/src/pmp-NA4-R.S", + "rv32i_m/pmp32/src/pmp-NA4-RW-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NA4-RW-priority.S", + "rv32i_m/pmp32/src/pmp-NA4-RW.S", + "rv32i_m/pmp32/src/pmp-NA4-RWX.S", + "rv32i_m/pmp32/src/pmp-NA4-RX-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NA4-RX-priority.S", + "rv32i_m/pmp32/src/pmp-NA4-RX.S", + "rv32i_m/pmp32/src/pmp-NA4-X-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NA4-X-priority.S", + "rv32i_m/pmp32/src/pmp-NA4-X.S", + "rv32i_m/pmp32/src/pmp-NAPOT-R-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NAPOT-R-priority.S", + "rv32i_m/pmp32/src/pmp-NAPOT-R.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RW-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RW-priority.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RW.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RWX.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RX-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RX-priority.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RX.S", + "rv32i_m/pmp32/src/pmp-NAPOT-X-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NAPOT-X-priority.S", + "rv32i_m/pmp32/src/pmp-NAPOT-X.S", + "rv32i_m/pmp32/src/pmp-TOR-R-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-TOR-R-priority.S", + "rv32i_m/pmp32/src/pmp-TOR-R.S", + "rv32i_m/pmp32/src/pmp-TOR-RW-priority-level-2..S", + "rv32i_m/pmp32/src/pmp-TOR-RW-priority.S", + "rv32i_m/pmp32/src/pmp-TOR-RW.S", + "rv32i_m/pmp32/src/pmp-TOR-RWX.S", + "rv32i_m/pmp32/src/pmp-TOR-RX-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-TOR-RX-priority.S", + "rv32i_m/pmp32/src/pmp-TOR-RX.S", + "rv32i_m/pmp32/src/pmp-TOR-X-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-TOR-X-priority.S", + "rv32i_m/pmp32/src/pmp-TOR-X.S" +}; + +string arch64pmp[] = '{ + `RISCVARCHTEST, + "rv64i_m/pmp64/pmp64-CFG-reg.S", + "rv64i_m/pmp64/pmp64-CSR-access.S", + "rv64i_m/pmp64/pmp64-NA4-R-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NA4-R-priority.S", + "rv64i_m/pmp64/pmp64-NA4-R.S", + "rv64i_m/pmp64/pmp64-NA4-RW-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NA4-RW-priority.S", + "rv64i_m/pmp64/pmp64-NA4-RW.S", + "rv64i_m/pmp64/pmp64-NA4-RWX.S", + "rv64i_m/pmp64/pmp64-NA4-RX-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NA4-RX-priority.S", + "rv64i_m/pmp64/pmp64-NA4-RX.S", + "rv64i_m/pmp64/pmp64-NA4-X-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NA4-X-priority.S", + "rv64i_m/pmp64/pmp64-NA4-X.S", + "rv64i_m/pmp64/pmp64-NAPOT-R-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NAPOT-R-priority.S", + "rv64i_m/pmp64/pmp64-NAPOT-R.S", + "rv64i_m/pmp64/pmp64-NAPOT-RW-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NAPOT-RW-priority.S", + "rv64i_m/pmp64/pmp64-NAPOT-RW.S", + "rv64i_m/pmp64/pmp64-NAPOT-RWX.S", + "rv64i_m/pmp64/pmp64-NAPOT-RX-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NAPOT-RX-priority.S", + "rv64i_m/pmp64/pmp64-NAPOT-RX.S", + "rv64i_m/pmp64/pmp64-NAPOT-X-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NAPOT-X-priority.S", + "rv64i_m/pmp64/pmp64-NAPOT-X.S", + "rv64i_m/pmp64/pmp64-TOR-R-priority-level-2.S", + "rv64i_m/pmp64/pmp64-TOR-R-priority.S", + "rv64i_m/pmp64/pmp64-TOR-R.S", + "rv64i_m/pmp64/pmp64-TOR-RW-priority-level-2..S", + "rv64i_m/pmp64/pmp64-TOR-RW-priority.S", + "rv64i_m/pmp64/pmp64-TOR-RW.S", + "rv64i_m/pmp64/pmp64-TOR-RWX.S", + "rv64i_m/pmp64/pmp64-TOR-RX-priority-level-2.S", + "rv64i_m/pmp64/pmp64-TOR-RX-priority.S", + "rv64i_m/pmp64/pmp64-TOR-RX.S", + "rv64i_m/pmp64/pmp64-TOR-X-priority-level-2.S", + "rv64i_m/pmp64/pmp64-TOR-X-priority.S", + "rv64i_m/pmp64/pmp64-TOR-X.S" +}; + +string arch32vm_sv32[] = '{ + `RISCVARCHTEST, + "rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S", + "rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S", + "rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S", + "rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S", + "rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S", + "rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S", + "rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S", + "rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S", + "rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S", + "rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S", + "rv32i_m/vm_sv32/src/vm_mxr_S_mode.S", + "rv32i_m/vm_sv32/src/vm_mxr_U_mode.S", + "rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S", + "rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S", + "rv32i_m/vm_sv32/src/vm_reserved_pte_S_mode.S", + "rv32i_m/vm_sv32/src/vm_reserved_pte_U_mode.S", + "rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S", + "rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S", + "rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S", + "rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S", + "rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S" +}; + string arch64priv[] = '{ `RISCVARCHTEST, "rv64i_m/privilege/src/ebreak.S", diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py index 9abe67040..557d1af04 100644 --- a/tests/riscof/sail_cSim/riscof_sail_cSim.py +++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py @@ -52,7 +52,7 @@ class sail_cSim(pluginTemplate): ispec = utils.load_yaml(isa_yaml)['hart0'] self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32') self.isa = 'rv' + self.xlen - self.sailargs = ' ' + self.sailargs = ' --pmp-count=16 --pmp-grain=0 ' # Hardcode pmp-count and pmp-grain for now. Make configurable later once Sail has easier configuration self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 ')) if "I" in ispec["ISA"]: self.isa += 'i' @@ -103,7 +103,6 @@ class sail_cSim(pluginTemplate): execute = "@cd "+testentry['work_dir']+";" -# cmd = self.compile_cmd.format(testentry['isa'].lower().replace('zicsr', ' ', 1), self.xlen) + ' ' + test + ' -o ' + elf cmd = self.compile_cmd.format(testentry['isa'].lower(), self.xlen) + ' ' + test + ' -o ' + elf compile_cmd = cmd + ' -D' + " -D".join(testentry['macros']) execute+=compile_cmd+";" @@ -117,8 +116,7 @@ class sail_cSim(pluginTemplate): reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test)) execute += 'cut -c-{0:g} {1} > {2}'.format(8, reference_output, sig_file) #use cut to remove comments when copying else: - execute += self.sail_exe[self.xlen] + ' -z268435455 -i ' + self.sailargs + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) -# execute += self.sail_exe[self.xlen] + ' -z268435455 -i --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) + execute += self.sail_exe[self.xlen] + ' -z268435455 -i --trace=step ' + self.sailargs + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) cov_str = ' ' for label in testentry['coverage_labels']: diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index 3fde70700..0b07212cc 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -26,4 +26,4 @@ hart0: legal: - extensions[25:0] bitmask [0x000112D, 0x0000000] wr_illegal: - - Unchangedcd \ No newline at end of file + - Unchanged \ No newline at end of file From a462b9a2e66dd43effed4f173118b50ba2749cbb Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 15 Nov 2024 23:52:50 -0800 Subject: [PATCH 047/212] Clean up verilator lint off commands and remove unnecessay ones --- config/shared/config-shared.vh | 6 ------ config/shared/parameter-defs.vh | 4 ---- src/fpu/fdivsqrt/fdivsqrtiter.sv | 2 -- src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtstage2.sv | 2 -- src/fpu/fround.sv | 4 ++-- src/generic/prioritythermometer.sv | 2 -- src/lsu/lsu.sv | 2 -- src/mdu/divstep.sv | 4 ---- src/privileged/csrm.sv | 2 ++ src/uncore/spi_apb.sv | 4 ++-- src/uncore/uartPC16550D.sv | 4 ++-- 12 files changed, 9 insertions(+), 29 deletions(-) diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index 91e1d4100..4ccb24bf2 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -122,9 +122,3 @@ localparam FMALEN = 3*NF + 6; localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (FMALEN + 2)); localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ)); // log_2(NORMSHIFTSZ) - -// Disable spurious Verilator warnings - -/* verilator lint_off STMTDLY */ -/* verilator lint_off ASSIGNDLY */ -/* verilator lint_off PINCONNECTEMPTY */ diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index c80b00232..88de34afc 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -95,11 +95,7 @@ localparam cvw_t P = '{ PLIC_SPI_ID : PLIC_SPI_ID, PLIC_SDC_ID : PLIC_SDC_ID, BPRED_SUPPORTED : BPRED_SUPPORTED, - /* verilator lint_off ENUMVALUE */ - // *** definitely need to fix this. - // it thinks we are casting from the enum type to BPRED_TYPE. BPRED_TYPE : BPRED_TYPE, - /* verilator lint_on ENUMVALUE */ BPRED_SIZE : BPRED_SIZE, BPRED_NUM_LHR : BPRED_NUM_LHR, BTB_SIZE : BTB_SIZE, diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv index 39de58855..ff03d29ec 100644 --- a/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -38,7 +38,6 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) ( output logic [P.DIVb+3:0] FirstWS, FirstWC // Q4.DIVb ); - /* verilator lint_off UNOPTFLAT */ logic [P.DIVb+3:0] WSNext[P.DIVCOPIES-1:0]; // Q4.DIVb logic [P.DIVb+3:0] WCNext[P.DIVCOPIES-1:0]; // Q4.DIVb logic [P.DIVb+3:0] WS[P.DIVCOPIES:0]; // Q4.DIVb @@ -56,7 +55,6 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) ( logic [P.DIVb+1:0] NextC; // Q2.DIVb logic [P.DIVb:0] UMux, UMMux; // U1.DIVb logic [P.DIVb:0] initU, initUM; // U1.DIVb - /* verilator lint_on UNOPTFLAT */ // Top Muxes and Registers // When start is asserted, the inputs are loaded into the divider. diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 737d9089a..a399e4a4f 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -136,7 +136,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( // calculate right shift amount RightShiftX to complete in discrete number of steps if (P.RK > 1) begin // more than 1 bit per cycle logic [$clog2(P.RK)-1:0] RightShiftX; - /* verilator lint_offf WIDTH */ + /* verilator lint_off WIDTH */ assign RightShiftX = P.RK - 1 - ((IntResultBitsE - 1) % P.RK); // Right shift amount assign DivXShifted = DivX >> RightShiftX; // shift X by up to R*K-1 to complete in n steps /* verilator lint_on WIDTH */ diff --git a/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv index fa13cadeb..06ac4ec82 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -28,7 +28,6 @@ //////////////////////////////////////////////////////////////////////////////////////////////// -/* verilator lint_off UNOPTFLAT */ module fdivsqrtstage2 import cvw::*; #(parameter cvw_t P) ( input logic [P.DIVb+3:0] D, DBar, // Q4.DIVb input logic [P.DIVb:0] U, UM, // U1.DIVb @@ -40,7 +39,6 @@ module fdivsqrtstage2 import cvw::*; #(parameter cvw_t P) ( output logic [P.DIVb:0] UNext, UMNext, // U1.DIVb output logic [P.DIVb+3:0] WSNext, WCNext // Q4.DIVb ); - /* verilator lint_on UNOPTFLAT */ logic [P.DIVb+3:0] Dsel; // Q4.DIVb logic up, uz; diff --git a/src/fpu/fround.sv b/src/fpu/fround.sv index 2814c766b..519d55096 100644 --- a/src/fpu/fround.sv +++ b/src/fpu/fround.sv @@ -115,9 +115,9 @@ module fround import cvw::*; #(parameter cvw_t P) ( /////////////////////////// // Exact logic - // verilator lint_off WIDTHEXPAND + /* verilator lint_off WIDTHEXPAND */ assign EgeNf = (E >= Nf) & Xe[P.NE-1]; // Check if E >= Nf. Also check that Xe is positive to avoid wraparound problems - // verilator lint_on WIDTHEXPAND + /* verilator lint_on WIDTHEXPAND */ // Rounding logic: determine whether to round up in magnitude always_comb begin diff --git a/src/generic/prioritythermometer.sv b/src/generic/prioritythermometer.sv index 23acfcfb3..ecf37e80e 100644 --- a/src/generic/prioritythermometer.sv +++ b/src/generic/prioritythermometer.sv @@ -39,11 +39,9 @@ module prioritythermometer #(parameter N = 8) ( // Rather than linear. // create thermometer code mask - /* verilator lint_off UNOPTFLAT */ genvar i; assign y[0] = ~a[0]; for (i=1; i= rxfifotail) ? (rxfifohead-rxfifotail) : (rxfifohead + 16 - rxfifotail); - // verilator lint_on WIDTH + /* verilator lint_on WIDTH */ assign rxfifotriggered = rxfifoentries >= rxfifotriggerlevel; assign rxfifotimeout = rxtimeoutcnt == {rxbitsexpected, 6'b0}; // time out after 4 character periods; probably not right yet //assign rxfifotimeout = 0; // disabled pending fix From 2ee4525ba9859fbc1dcd726b0680c7ac4e3cce2b Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Sat, 16 Nov 2024 11:34:31 -0600 Subject: [PATCH 048/212] Made minor changes to the controller to clean up the logic. Still need to simplify the first always block. --- src/uncore/spi_controller.sv | 41 ++++++++++++++---------------------- 1 file changed, 16 insertions(+), 25 deletions(-) diff --git a/src/uncore/spi_controller.sv b/src/uncore/spi_controller.sv index dee3d3c99..0ed8e57be 100644 --- a/src/uncore/spi_controller.sv +++ b/src/uncore/spi_controller.sv @@ -75,6 +75,7 @@ module spi_controller ( logic ShiftEdgePulse; logic SampleEdgePulse; logic EndOfFramePulse; + logic InvertClock; // Frame stuff logic [3:0] BitNum; @@ -107,8 +108,8 @@ module spi_controller ( logic [7:0] DelayCounter; - logic DelayIsNext; - logic DelayState; + logic DelayState; + // Convenient Delay Reg Names assign cssck = Delay0[7:0]; assign sckcs = Delay0[15:8]; @@ -130,10 +131,6 @@ module spi_controller ( assign EndOfDelay = EndOfCSSCK | EndOfSCKCS | EndOfINTERCS | EndOfINTERXFR; // Clock Signal Stuff ----------------------------------------------- - // I'm going to handle all clock stuff here, including ShiftEdge and - // SampleEdge. This makes sure that SPICLK is an output of a register - // and it properly synchronizes signals. - // SPI enable generation, where SCLK = PCLK/(2*(SckDiv + 1)) // Asserts SCLKenable at the rising and falling edge of SCLK by counting from 0 to SckDiv // Active at 2x SCLK frequency to account for implicit half cycle delays and actions on both clock edges depending on phase @@ -166,12 +163,14 @@ module spi_controller ( end // SPICLK Logic - + // We only want to trigger the clock during Transmission. + // If Phase == 1, then we want to trigger as soon as NextState == TRANSMIT + // Otherwise, only trigger the clock when the CurrState is TRANSMIT. + // We never want to trigger the clock if the NextState is NOT TRANSMIT if (TransmitStart & ~DelayState) begin SPICLK <= SckMode[1]; - end else if (SCLKenable) begin - if (Phase & (NextState == TRANSMIT)) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1]; - else if (Transmitting) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1]; + end else if (SCLKenable) begin + SPICLK <= (NextState == TRANSMIT) & (~Phase & Transmitting | Phase) ? ~SPICLK : SckMode[1]; end // Reset divider @@ -201,32 +200,25 @@ module spi_controller ( // Possible pulses for all edge types. Combined with SPICLK to get // edges for different phase and polarity modes. assign ShiftEdgePulse = EdgePulse & ~LastBit; - assign SampleEdgePulse = EdgePulse & ~DelayIsNext; + assign SampleEdgePulse = EdgePulse & (NextState == TRANSMIT); assign EndOfFramePulse = EdgePulse & LastBit; // Delay ShiftEdge and SampleEdge by a half PCLK period // Aligned EXACTLY ON THE MIDDLE of the leading and trailing edges. // Sweeeeeeeeeet... + assign InvertClock = ^SckMode; always_ff @(posedge ~PCLK) begin if (~PRESETn | TransmitStart) begin ShiftEdge <= 0; SampleEdge <= 0; EndOfFrame <= 0; - end else if (^SckMode) begin - ShiftEdge <= ~SPICLK & ShiftEdgePulse; - SampleEdge <= SPICLK & SampleEdgePulse; - EndOfFrame <= ~SPICLK & EndOfFramePulse; - end else begin - ShiftEdge <= SPICLK & ShiftEdgePulse; - SampleEdge <= ~SPICLK & SampleEdgePulse; - EndOfFrame <= SPICLK & EndOfFramePulse; - end + end else begin + ShiftEdge <= (InvertClock ^ SPICLK) & ShiftEdgePulse; + SampleEdge <= (InvertClock ^ ~SPICLK) & SampleEdgePulse; + EndOfFrame <= (InvertClock ^ SPICLK) & EndOfFramePulse; end + end - // Logic for continuing to transmit through Delay states after end of frame - assign NextEndDelay = NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR; - assign CurrentEndDelay = CurrState == SCKCS | CurrState == INTERCS | CurrState == INTERXFR; - always_ff @(posedge PCLK) begin if (~PRESETn) begin CurrState <= INACTIVE; @@ -305,7 +297,6 @@ module spi_controller ( end assign Transmitting = CurrState == TRANSMIT; - assign DelayIsNext = (NextState == CSSCK | NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR); assign DelayState = (CurrState == CSSCK | CurrState == SCKCS | CurrState == INTERCS | CurrState == INTERXFR); assign InactiveState = CurrState == INACTIVE | CurrState == INTERCS; From 98f2ec6d6629dbd51c02ef7244f46003695e28e3 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 16 Nov 2024 09:58:04 -0800 Subject: [PATCH 049/212] Updated regression-wally --fcov to run privileged tests in lockstep --- bin/regression-wally | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index cc0588bf6..f4c3cc023 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -301,7 +301,8 @@ def addLockstepTestsByDir(dir, config, sim, fcovMode): for dirpath, dirnames, filenames in os.walk(os.path.abspath(dir)): for file in filenames: # fcov lockstep only runs on WALLY-COV-ALL.elf files; other lockstep runs on all files - if (file.endswith(".elf") and fcovMode == 0 or file.endswith("ALL.elf") and fcovMode == 1): + if ((file.endswith(".elf") and (fcovMode == 0 or "tests/priv" in dir)) or + (file.endswith("ALL.elf") and fcovMode == 1)): fullfile = os.path.join(dirpath, file) fields = fullfile.rsplit('/', 3) if (fields[2] == "ref"): @@ -419,9 +420,11 @@ if (args.ccov): # only run RV64GC tests on Questa in code coverage mode addTests(tests64gc_nofp, coveragesim) if (args.fp): addTests(tests64gc_fp, coveragesim) -elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode +elif (args.fcov): # run tests in lockstep in functional coverage mode addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1) addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1) + addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv32/", "rv32gc", coveragesim, 1) + addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim, 1) #addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0) else: From 45f6cb055dd9723d79c300bd5a833e8a391057c0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 16 Nov 2024 11:47:45 -0800 Subject: [PATCH 050/212] Changed reservation set size to one word to fix RV32GC lrsc privileged test failure Issue #1092 --- config/rv32gc/imperas.ic | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic index 46d0d31c3..2ba3c1280 100644 --- a/config/rv32gc/imperas.ic +++ b/config/rv32gc/imperas.ic @@ -36,7 +36,7 @@ --override cpu/Zicboz=T --override cmomp_bytes=64 # Zic64b --override cmoz_bytes=64 # Zic64b ---override lr_sc_grain=8 # Za64rs requires <=64; we use native word size +--override lr_sc_grain=4 # Za64rs requires <=64; we use native word size # 64 KiB continuous huge pages supported #--override cpu/Svpbmt=F From 1675e4cb7d10827515ffb42c772f216ca5c8a067 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 16 Nov 2024 11:53:05 -0800 Subject: [PATCH 051/212] Add rv32 wally-riscv-arch-test lockstep to nightly --- bin/regression-wally | 1 + 1 file changed, 1 insertion(+) diff --git a/bin/regression-wally b/bin/regression-wally index f4c3cc023..2a2466dfa 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -439,6 +439,7 @@ else: if (args.nightly): addLockstepTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, 0) addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, 0) + addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, 0) addTests(derivconfigtests, defaultsim) # addTests(bpredtests, defaultsim) # This is currently broken in regression due to something related to the new wsim script. From dda3cd6beaf474d1c8ab4594d06f207615d35344 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Sat, 16 Nov 2024 14:29:58 -0600 Subject: [PATCH 052/212] Removed unnecessary separate if statement. --- src/uncore/spi_apb.sv | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv index 9b15839e7..04c3d3c97 100644 --- a/src/uncore/spi_apb.sv +++ b/src/uncore/spi_apb.sv @@ -174,16 +174,12 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( SPI_CSMODE: ChipSelectMode <= Din[1:0]; SPI_DELAY0: Delay0 <= {Din[23:16], Din[7:0]}; SPI_DELAY1: Delay1 <= {Din[23:16], Din[7:0]}; - SPI_FMT: Format <= {Din[19:16], Din[2]}; + SPI_FMT: Format <= {Din[19:16], Din[2]}; + SPI_TXDATA: if (~TransmitFIFOFull) TransmitData[7:0] <= Din[7:0]; SPI_TXMARK: TransmitWatermark <= Din[2:0]; SPI_RXMARK: ReceiveWatermark <= Din[2:0]; SPI_IE: InterruptEnable <= Din[1:0]; endcase - - if (Memwrite) - case(Entry) - SPI_TXDATA: if (~TransmitFIFOFull) TransmitData[7:0] <= Din[7:0]; - endcase /* verilator lint_off CASEINCOMPLETE */ // According to FU540 spec: Once interrupt is pending, it will remain set until number From f6b0805fd4fe2697f292802db62f2709bf16b2c2 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 16 Nov 2024 12:35:37 -0800 Subject: [PATCH 053/212] More lint cleanup: remove unused params --- bin/lint-wally | 2 +- src/cache/cache.sv | 18 +++++------------- src/cache/cacheLRU.sv | 2 +- src/cache/cachefsm.sv | 3 +-- src/cache/cacheway.sv | 9 +-------- src/hazard/hazard.sv | 2 +- src/ifu/ifu.sv | 2 +- src/lsu/lsu.sv | 2 +- src/privileged/csrs.sv | 2 -- src/uncore/ram_ahb.sv | 2 +- src/uncore/rom_ahb.sv | 2 +- src/uncore/uncore.sv | 4 ++-- src/wally/wallypipelinedcore.sv | 2 +- 13 files changed, 17 insertions(+), 35 deletions(-) diff --git a/bin/lint-wally b/bin/lint-wally index d4fcd8767..ef79a6a00 100755 --- a/bin/lint-wally +++ b/bin/lint-wally @@ -30,7 +30,7 @@ for config in ${configs[@]}; do if !($verilator --lint-only --quiet --top-module wallywrapper \ "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" \ $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv \ - -Wall -Wno-UNUSEDSIGNAL -Wno-UNUSEDPARAM -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY); then + -Wall -Wno-UNUSEDSIGNAL -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY); then if [ "$1" == "-nightly" ]; then echo -e "${RED}$config failed lint${NC}" fails=$((fails+1)) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 7307c233e..b74ecdcff 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -29,7 +29,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module cache import cvw::*; #(parameter cvw_t P, - parameter PA_BITS, XLEN, LINELEN, NUMSETS, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) ( + parameter PA_BITS, LINELEN, NUMSETS, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) ( input logic clk, input logic reset, input logic Stall, // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY @@ -66,11 +66,7 @@ module cache import cvw::*; #(parameter cvw_t P, localparam SETLEN = $clog2(NUMSETS); // Number of set bits localparam SETTOP = SETLEN+OFFSETLEN; // Number of set plus offset bits localparam TAGLEN = PA_BITS - SETTOP; // Number of tag bits - localparam CACHEWORDSPERLINE = LINELEN/WORDLEN;// Number of words in cache line - localparam LOGCWPL = $clog2(CACHEWORDSPERLINE);// Log2 of ^ localparam FLUSHADRTHRESHOLD = NUMSETS - 1; // Used to determine when flush is complete - localparam LOGLLENBYTES = $clog2(WORDLEN/8); // Number of bits to address a word - logic SelAdrData; logic SelAdrTag; @@ -122,14 +118,14 @@ module cache import cvw::*; #(parameter cvw_t P, AdrSelMuxSelLRU, CacheSetLRU); // Array of cache ways, along with victim, hit, dirty, and read merging logic - cacheway #(P, PA_BITS, XLEN, NUMSETS, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( + cacheway #(P, PA_BITS, NUMSETS, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( .clk, .reset, .CacheEn, .CacheSetData, .CacheSetTag, .PAdr, .LineWriteData, .LineByteMask, .SelVictim, .SetValid, .ClearValid, .SetDirty, .ClearDirty, .VictimWay, .FlushWay, .FlushCache, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .HitDirtyWay, .TagWay, .FlushStage, .InvalidateCache); // Select victim way for associative caches if(NUMWAYS > 1) begin:vict - cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMSETS) cacheLRU( + cacheLRU #(NUMWAYS, SETLEN, NUMSETS) cacheLRU( .clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSetLRU, .LRUWriteEn, .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache); end else @@ -172,11 +168,7 @@ module cache import cvw::*; #(parameter cvw_t P, if(!READ_ONLY_CACHE) begin:WriteSelLogic logic [LINELEN/8-1:0] DemuxedByteMask, FetchBufferByteSel; - // Adjust byte mask from word to cache line - - localparam CACHEMUXINVERALPERLINE = LINELEN/MUXINTERVAL;// Number of words in cache line - localparam LOGMIPL = $clog2(CACHEMUXINVERALPERLINE);// Log2 of ^ - + // Adjust byte mask from word to cache line logic [LINELEN/8-1:0] BlankByteMask; assign BlankByteMask[WORDLEN/8-1:0] = ByteMask; assign BlankByteMask[LINELEN/8-1:WORDLEN/8] = 0; @@ -231,7 +223,7 @@ module cache import cvw::*; #(parameter cvw_t P, // Cache FSM ///////////////////////////////////////////////////////////////////////////////////////////// - cachefsm #(P, READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, + cachefsm #(READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, .FlushStage, .CacheRW, .Stall, .Hit, .LineDirty, .HitLineDirty, .CacheStall, .CacheCommitted, .CacheMiss, .CacheAccess, .SelAdrData, .SelAdrTag, .SelVictim, diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index a91e7232c..2ab3bac8d 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -29,7 +29,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module cacheLRU - #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMSETS = 128) ( + #(parameter NUMWAYS = 4, SETLEN = 9, NUMSETS = 128) ( input logic clk, input logic reset, input logic FlushStage, diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 5f42c7690..91aa5c97b 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -28,8 +28,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module cachefsm import cvw::*; #(parameter cvw_t P, - parameter READ_ONLY_CACHE = 0) ( +module cachefsm #(parameter READ_ONLY_CACHE = 0) ( input logic clk, input logic reset, // hazard and privilege unit diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 575934727..e2db5a46c 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -29,7 +29,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module cacheway import cvw::*; #(parameter cvw_t P, - parameter PA_BITS, XLEN, NUMSETS=512, LINELEN = 256, TAGLEN = 26, + parameter PA_BITS, NUMSETS=512, LINELEN = 256, TAGLEN = 26, OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) ( input logic clk, input logic reset, @@ -57,12 +57,6 @@ module cacheway import cvw::*; #(parameter cvw_t P, output logic DirtyWay , // The selected way is dirty output logic [TAGLEN-1:0] TagWay); // This way's tag if valid - localparam WORDSPERLINE = LINELEN/XLEN; - localparam BYTESPERLINE = LINELEN/8; - localparam LOGWPL = $clog2(WORDSPERLINE); - localparam LOGXLENBYTES = $clog2(XLEN/8); - localparam BYTESPERWORD = XLEN/8; - logic [NUMSETS-1:0] ValidBits; logic [NUMSETS-1:0] DirtyBits; logic [LINELEN-1:0] ReadDataLine; @@ -131,7 +125,6 @@ module cacheway import cvw::*; #(parameter cvw_t P, localparam NUMSRAM = LINELEN/P.CACHE_SRAMLEN; localparam SRAMLENINBYTES = P.CACHE_SRAMLEN/8; - localparam LOGNUMSRAM = $clog2(NUMSRAM); for(words = 0; words < NUMSRAM; words++) begin: word if (READ_ONLY_CACHE) begin:wordram // no byte-enable needed for i$. diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index 895a6e92f..63b31001c 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -27,7 +27,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module hazard import cvw::*; #(parameter cvw_t P) ( +module hazard ( input logic BPWrongE, CSRWriteFenceM, RetM, TrapM, input logic StructuralStallD, input logic LSUStallM, IFUStallF, diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 695603758..a90483533 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -236,7 +236,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0; assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0; - cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS), + cache #(.P(P), .PA_BITS(P.PA_BITS), .LINELEN(P.ICACHE_LINELENINBITS), .NUMSETS(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS), .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(AHBWLOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1)) icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD), diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 9f5d460f7..f6a215a27 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -324,7 +324,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign CacheRWM = (CacheableM & ~SelDTIM) ? LSURWM : '0; assign FlushDCache = FlushDCacheM & ~(SelHPTW); - cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN), + cache #(.P(P), .PA_BITS(P.PA_BITS), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache( .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(LSUFlushW), .CacheRW(CacheRWM), diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index a2a21c2ee..c30f78e14 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -67,8 +67,6 @@ module csrs import cvw::*; #(parameter cvw_t P) ( localparam STIMECMPH = 12'h15D; localparam SATP = 12'h180; // Constants - localparam ZERO = {(P.XLEN){1'b0}}; - localparam SEDELEG_MASK = ~(ZERO | {{P.XLEN-3{1'b0}}, 3'b111} << 9); logic WriteSTVECM; logic WriteSSCRATCHM, WriteSEPCM; diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index 0b4e777e4..60c870138 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -28,7 +28,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module ram_ahb import cvw::*; #(parameter cvw_t P, - parameter BASE=0, RANGE = 65535, PRELOAD = 0) ( + parameter RANGE = 65535, PRELOAD = 0) ( input logic HCLK, HRESETn, input logic HSELRam, input logic [P.PA_BITS-1:0] HADDR, diff --git a/src/uncore/rom_ahb.sv b/src/uncore/rom_ahb.sv index d20ef64da..63f6e9716 100644 --- a/src/uncore/rom_ahb.sv +++ b/src/uncore/rom_ahb.sv @@ -28,7 +28,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module rom_ahb import cvw::*; #(parameter cvw_t P, - parameter BASE=0, RANGE = 65535, PRELOAD = 0) ( + parameter RANGE = 65535, PRELOAD = 0) ( input logic HCLK, HRESETn, input logic HSELRom, input logic [P.PA_BITS-1:0] HADDR, diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 21dd956ed..f17fc67fe 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -109,13 +109,13 @@ module uncore import cvw::*; #(parameter cvw_t P)( // on-chip RAM if (P.UNCORE_RAM_SUPPORTED) begin : ram - ram_ahb #(.P(P), .BASE(P.UNCORE_RAM_BASE), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram ( + ram_ahb #(.P(P), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram ( .HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY, .HTRANS, .HWDATA, .HWSTRB, .HREADRam, .HRESPRam, .HREADYRam); end else assign {HREADRam, HRESPRam, HREADYRam} = '0; if (P.BOOTROM_SUPPORTED) begin : bootrom - rom_ahb #(.P(P), .BASE(P.BOOTROM_BASE), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD)) + rom_ahb #(.P(P), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD)) bootrom(.HCLK, .HRESETn, .HSELRom(HSELBootRom), .HADDR, .HREADY, .HTRANS, .HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom)); end else assign {HREADBootRom, HRESPBootRom, HREADYBootRom} = '0; diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 8158a1cfb..b5a80a24b 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -271,7 +271,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( end // global stall and flush control - hazard #(P) hzu( + hazard hzu( .BPWrongE, .CSRWriteFenceM, .RetM, .TrapM, .StructuralStallD, .LSUStallM, .IFUStallF, From 00d02e5656f92fd8888b5ce9245834440b96479e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 16 Nov 2024 12:53:10 -0800 Subject: [PATCH 054/212] fix testbench --- testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index b2dda03ab..7c28ebfe6 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -564,7 +564,7 @@ module testbench; assign SPIIn = 1'b0; if(P.EXT_MEM_SUPPORTED) begin - ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) + ram_ahb #(.P(P), .RANGE(P.EXT_MEM_RANGE)) ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB); end else begin From def3b46afacf3a1142462a37b383240e7c618cad Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Sat, 16 Nov 2024 14:13:54 -0800 Subject: [PATCH 055/212] Add ZicsrU to fcov --- config/rv32gc/coverage.svh | 1 + config/rv64gc/coverage.svh | 1 + 2 files changed, 2 insertions(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index ba876f6b7..afd34306e 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -33,5 +33,6 @@ // Privileged extensions `include "ZicsrM_coverage.svh" `include "ZicsrF_coverage.svh" +`include "ZicsrU_coverage.svh" `include "RV32VM_coverage.svh" `include "RV32VM_PMP_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 901616311..6108376f9 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -34,6 +34,7 @@ `include "RV64VM_coverage.svh" `include "ZicsrM_coverage.svh" `include "ZicsrF_coverage.svh" +`include "ZicsrU_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" From 205db4348c1e362eaf55b4608cf38d89129213ff Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 16 Nov 2024 18:31:02 -0800 Subject: [PATCH 056/212] Fixed cause_m_time_interrupt most significant byte --- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 2 +- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index 654c13568..f34ca6363 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -133,8 +133,8 @@ cause_m_time_interrupt: add t3, t2, t3 // add desired offset to the current time bgtu t3, t2, nowrap_m // check new time exceeds current time (no wraparound) addi t6, t6, 1 // if wrap, increment most significant word - sw t6,4(t4) // store into most significant word of MTIMECMP nowrap_m: + sw t6,4(t4) // store into most significant word of MTIMECMP sw t3, 0(t4) // store into least significant word of MTIMECMP time_loop_m: addi a3, a3, -1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index d939c130e..5f6d14ecd 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -136,8 +136,8 @@ cause_m_time_interrupt: add t3, t2, t3 // add desired offset to the current time bgtu t3, t2, nowrap_m // check new time exceeds current time (no wraparound) addi t6, t6, 1 // if wrap, increment most significant word - sw t6,4(t4) // store into most significant word of MTIMECMP nowrap_m: + sw t6,4(t4) // store into most significant word of MTIMECMP sw t3, 0(t4) // store into least significant word of MTIMECMP time_loop_m: addi a3, a3, -1 From 99e5b295fb07880ebd2e50c6bf74c872a134f96f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 16 Nov 2024 21:08:03 -0800 Subject: [PATCH 057/212] Update regression-wally fcov to work with new Makefile --- bin/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index cc0588bf6..c5b9c8f33 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -552,7 +552,7 @@ def main(): if args.ccov: os.system('make QuestaCodeCoverage') if args.fcov: - os.system('make -f '+WALLY+'/addins/cvw-arch-verif/Makefile merge') + os.system('make -C '+WALLY+'/addins/cvw-arch-verif merge') # Count the number of failures if num_fail: print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail) From 147f62d9a589fa54037c9b19347e24f28527036c Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 17 Nov 2024 06:43:13 -0800 Subject: [PATCH 058/212] Fixed timer offset in RV32 WALLY-wfi; simplified in RV64 WALLY-wfi --- .../rv32i_m/privilege/src/WALLY-wfi-01.S | 22 ++++++------ .../rv64i_m/privilege/src/WALLY-wfi-01.S | 36 ++++++++----------- 2 files changed, 26 insertions(+), 32 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S index 61d73a4f7..65f564a1e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S @@ -36,20 +36,20 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // Code copied from test library to cause m time interrupt, with time loop replaced with wfi. -/* Note: the following line might cause problems in the future. If more than 0x50 cycles are needed before the wfi +/* Note: the following line might cause problems in the future. If more than 0x100 cycles are needed before the wfi instruction begins, then the program might fall into a loop and run forever*/ -li x28, 0x50 // Desired offset from the present time -mv a3, x28 // copy value in to know to stop waiting for interrupt after this many cycles -la x29, 0x02004000 // MTIMECMP register in CLINT -la x30, 0x0200BFF8 // MTIME register in CLINT -lw x7, 0(x30) // low word of MTIME -lw x31, 4(x30) // high word of MTIME -add x28, x7, x28 // add desired offset to the current time -bgtu x28, x7, nowrap // check new time exceeds current time (no wraparound) -addi x31, x31, 1 // if wrap, increment most significant word -sw x31,4(x29) // store into most significant word of MTIMECMP + li x28, 0x100 // Desired offset from the present time + mv a3, x28 // copy value in to know to stop waiting for interrupt after this many cycles + la x29, 0x02004000 // MTIMECMP register in CLINT + la x30, 0x0200BFF8 // MTIME register in CLINT + lw x7, 0(x30) // low word of MTIME + lw x31, 4(x30) // high word of MTIME + add x28, x7, x28 // add desired offset to the current time + bgtu x28, x7, nowrap // check new time exceeds current time (no wraparound) + addi x31, x31, 1 // if wrap, increment most significant word nowrap: + sw x31,4(x29) // store into most significant word of MTIMECMP sw x28, 0(x29) // store into least significant word of MTIMECMP auipc ra, 0x0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S index 6430f2078..3611f99ef 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S @@ -35,30 +35,24 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // Code copied from test library to cause m time interrupt, with time loop replaced with wfi. -li x28, 0x60 // Desired offset from the present time -mv a3, x28 // copy value in to know to stop waiting for interrupt after this many cycles -la x29, 0x02004000 // MTIMECMP register in CLINT -la x30, 0x0200BFF8 // MTIME register in CLINT -lw x7, 0(x30) // low word of MTIME -lw x31, 4(x30) // high word of MTIME -add x28, x7, x28 // add desired offset to the current time -bgtu x28, x7, nowrap // check new time exceeds current time (no wraparound) -addi x31, x31, 1 // if wrap, increment most significant word -sw x31,4(x29) // store into most significant word of MTIMECMP + li x28, 0x60 // Desired offset from the present time + mv a3, x28 // copy value in to know to stop waiting for interrupt after this many cycles + la x29, 0x02004000 // MTIMECMP register in CLINT + la x30, 0x0200BFF8 // MTIME register in CLINT + ld x7, 0(x30) // read MTIME + add x28, x7, x28 // add offset + sw x28, 0(x29) // MTIMECMP = MTIME + offset -nowrap: - sw x28, 0(x29) // store into least significant word of MTIMECMP + auipc ra, 0x0 + addi ra, ra, 0xC // load address after wfi into ra so we return to the right place after handling the time interrupt -auipc ra, 0x0 -addi ra, ra, 0xC // load address after wfi into ra so we return to the right place after handling the time interrupt + wfi // test wfi until trap goes off -wfi // test wfi until trap goes off - -li x28, 0x600d111 // magic number "good 111" to write to output after interrupt goes off. -// this tests whether wfi is a nop or not since we should get the output for the interrupt before this one -sd x28, 0(x6) -addi x6, x6, 8 -addi x16, x16, 8 + li x28, 0x600d111 // magic number "good 111" to write to output after interrupt goes off. + // this tests whether wfi is a nop or not since we should get the output for the interrupt before this one + sd x28, 0(x6) + addi x6, x6, 8 + addi x16, x16, 8 END_TESTS From 405ce4e6523bc1e264651030a02129b07328e680 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 17 Nov 2024 07:12:32 -0800 Subject: [PATCH 059/212] Updated IMPERAS_HOME to reflect their distribution --- site-setup.csh | 2 +- site-setup.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/site-setup.csh b/site-setup.csh index 867485a8d..63f1260be 100644 --- a/site-setup.csh +++ b/site-setup.csh @@ -49,7 +49,7 @@ setenv SPIKE_PATH $RISCV/bin # Change this for your path to riscv-isa-s setenv IDV $RISCV/ImperasDV-OpenHW if ($?IDV) then # echo "Imperas exists" - setenv IMPERAS_HOME $IDV/Imperas + setenv IMPERAS_HOME $IDV setenv IMPERAS_PERSONALITY CPUMAN_DV_ASYNC setenv ROOTDIR ~/ source ${IMPERAS_HOME}/bin/setup.sh diff --git a/site-setup.sh b/site-setup.sh index 8c03a2a36..34fe1eb42 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -66,7 +66,7 @@ export SPIKE_PATH=$RISCV/bin # Copy this as it is export IDV=$RISCV/ImperasDV-OpenHW if [ -e "$IDV" ]; then # echo "Imperas exists" - export IMPERAS_HOME=$IDV/Imperas + export IMPERAS_HOME=$IDV export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC export ROOTDIR=~/ source "${IMPERAS_HOME}"/bin/setup.sh From 6f45dcd22c921fcfc5d07d88ec905a4291a63fa5 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Sun, 17 Nov 2024 13:01:06 -0800 Subject: [PATCH 060/212] Updated nightly instructions in readme to use curl --- README.md | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 40dc08d51..e302e33f6 100644 --- a/README.md +++ b/README.md @@ -196,12 +196,13 @@ Startups can expect to spend more than $1 million on CAD tools to get a chip to # Adding Cron Job for nightly builds If you want to add a cronjob you can do the following: -1) Set up the email client `mutt` for your distribution +1) Set up the email client `mutt` to send emails through the command line 2) Enter `crontab -e` into a terminal -3) add this code to test building CVW and then running `regression-wally --nightly` at 9:30 PM each day +3) add this code to test cloning CVW, making CVW's tests, then running `regression-wally --nightly --buildroot` every day at 21:30 in your local time ```bash -30 21 * * * bash -l -c "source ~/PATH/TO/CVW/setup.sh; PATH_TO_CVW/cvw/bin/wrapper_nightly_runs.sh --path {PATH_TO_TEST_LOCATION} --target all --tests nightly --send_email harris@hmc.edu,kaitlin.verilog@gmail.com" +30 21 * * * curl -L https://raw.githubusercontent.com/openhwgroup/cvw/refs/heads/main/bin/nightly_build.py | python - --path {PATH_FOR_NIGHTLY_RUNS} --target all --tests all --send_email harris@hmc.edu,rose@rosethompson.net ``` +This utility will take up approximately 100 GB on your hard drive. You can also run the script directly from `bin/nightly_build.py`. # Example wsim commands From 028ffe9f4acb05693fbbfa00ac4da497e341dd38 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 20 Nov 2024 07:23:51 -0800 Subject: [PATCH 061/212] Removing obsolete *** --- config/rv32e/config.vh | 1 - config/rv32gc/config.vh | 1 - config/rv32i/config.vh | 1 - config/rv32imc/config.vh | 1 - config/rv64gc/config.vh | 1 - config/rv64i/config.vh | 1 - examples/fp/fpcalc/fpcalc.c | 2 +- testbench/common/functionName.sv | 2 +- .../WALLY-csr-permission-s-01.reference_output | 9 +++++++++ .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 11 +++++------ .../rv32i_m/privilege/src/WALLY-csr-permission-s-01.S | 9 +++------ .../rv32i_m/privilege/src/WALLY-pma-01.S | 2 +- 12 files changed, 20 insertions(+), 21 deletions(-) diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 4ec0123d1..db0838550 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -147,7 +147,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16; // Peripheral Physical Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? localparam logic DTIM_SUPPORTED = 0; localparam logic [63:0] DTIM_BASE = 64'h80000000; localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index c861759d9..af2032937 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -147,7 +147,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16; // Peripheral Physical Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? localparam logic DTIM_SUPPORTED = 0; localparam logic [63:0] DTIM_BASE = 64'h80000000; localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 01818afc2..ede534f0b 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -147,7 +147,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16; // Peripheral Physical Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? localparam logic DTIM_SUPPORTED = 1; localparam logic [63:0] DTIM_BASE = 64'h80000000; localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index 05a8fd242..e9f986a07 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -147,7 +147,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16; // Peripheral Physical Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? localparam logic DTIM_SUPPORTED = 1; localparam logic [63:0] DTIM_BASE = 64'h80000000; localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index b8ed8dc47..4f833178a 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -147,7 +147,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16; // Peripheral Physical Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? localparam logic DTIM_SUPPORTED = 0; localparam logic [63:0] DTIM_BASE = 64'h80000000; localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 94360877f..3a8bae1bc 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -147,7 +147,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16; // Peripheral Physical Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? localparam logic DTIM_SUPPORTED = 1; localparam logic [63:0] DTIM_BASE = 64'h80000000; localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; diff --git a/examples/fp/fpcalc/fpcalc.c b/examples/fp/fpcalc/fpcalc.c index 16dcce225..e4638a64b 100644 --- a/examples/fp/fpcalc/fpcalc.c +++ b/examples/fp/fpcalc/fpcalc.c @@ -237,7 +237,7 @@ __uint128_t parseNum(char *num) { if (strlen(num) < 8) size = 2; else if (strlen(num) < 16) size = 4; else if (strlen(num) < 32) size = 8; - else if (strlen(num) < 35) size = 16; // *** will need to increase + else if (strlen(num) < 35) size = 16; else { printf("Error: only half, single, double, or quad precision supported"); exit(1); diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index 5a14c84a4..2d257ce32 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -70,7 +70,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( begin if ( pc == 0 ) begin - // *** want to keep the old value for mid and minval + // want to keep the old value for mid and minval mid = 0; return; end diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-s-01.reference_output index 0a35f7ca0..71ecd9fd2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-s-01.reference_output @@ -1,4 +1,13 @@ 0000000b # Test 5.2.3.6: ecall from going to S mode from M mode +00000002 # S mode write to mstatush with illegal instruction +00000002 # S mode read from mstatush with illegal instruction +00000bad +00000002 # S mode write to menvcfgh with illegal instruction +00000002 # S mode read from menvcfgh with illegal instruction +00000bad +00000002 # S mode write to mseccfgh with illegal instruction +00000002 # S mode read from mseccfgh with illegal instruction +00000bad 00000002 # S mode write to pmpcfg1 with illegal instruction 00000002 # S mode read from pmpcfg1 with illegal instruction 00000bad diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index f34ca6363..6f7fc8a47 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -117,7 +117,7 @@ cause_store_acc: ret cause_ecall: - // *** ASSUMES you have already gone to the mode you need to call this from. + // ASSUMES you have already gone to the mode you need to call this from. ecall ret @@ -319,7 +319,7 @@ end_trap_triggers: .align 6 trap_handler_\MODE\(): j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler - // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented + // ASSUMES that a cause value of 0 for an interrupt is unimplemented // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way j s_soft_vector_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table. @@ -337,7 +337,7 @@ trap_handler_\MODE\(): trap_unvectored_\MODE\(): csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. - // *** NOTE: this means that nested traps will be screwed up but they shouldn't happen in any of these tests + // NOTE: this means that nested traps will be screwed up but they shouldn't happen in any of these tests trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since we already switch sp and scratch there // save registers on stack before using @@ -707,7 +707,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a .endm .macro READ32 ADDR - // Attempt read at ADDR. Write the value read out to the output *** Consider adding specific test for reading a non known value + // Attempt read at ADDR. Write the value read out to the output. Consider adding specific test for reading a non known value // Success outputs: // value read out from ADDR // Fault outputs: @@ -751,7 +751,6 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a // 0x9: test called from S mode // 0xB: test called from M mode // they generally do not fault or cause issues as long as these modes are enabled -// *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not? .macro GOTO_M_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0 li a0, 2 // determine trap handler behavior (go to machine mode) @@ -807,7 +806,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a // value read back out from CSR after writing // Fault outputs: // The previous CSR value before write attempt - // *** Most likely 0x2, the mcause for illegal instruction if we don't have write or read access + // Most likely 0x2, the mcause for illegal instruction if we don't have write or read access li t5, 0xbad // load bad value to be overwritten by csrr li t4, \VAL csrw \CSR\(), t4 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S index 7194b59a4..af7f6252c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S @@ -32,18 +32,15 @@ TRAP_HANDLER m # Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode. -# *** several of these appear not to be implemented in the assembler? -# I get "assembler messages: error: unkown CSR" with many of them. - GOTO_S_MODE 0x0, 0x0 # Attempt to write 0x111 to each of these CSRs and read the value back # should result in an illegal instruction for the write and read, respectively # High-bit versions storing the upper 32 bits of some CSRs for RV32 -# WRITE_READ_CSR mstatush 0x111 # *** these appear not to be implemented in GCC -# WRITE_READ_CSR menvcfgh 0x111 -# WRITE_READ_CSR mseccfgh 0x111 +WRITE_READ_CSR mstatush 0x111 # not supported in rv32 +WRITE_READ_CSR menvcfgh 0x111 +WRITE_READ_CSR mseccfgh 0x111 WRITE_READ_CSR pmpcfg1 0x111 WRITE_READ_CSR pmpcfg3 0x111 WRITE_READ_CSR mcycleh 0x111 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S index 0c1c7bbb2..2c58b0db8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S @@ -66,7 +66,7 @@ test_cases: # --------------------------------------------------------------------------------------------- # =========== test 12.3.2.1 PMAs: Memory Access Size, Type protection test =========== -# Tests memory load, store, and execute permissions based on table 12.3 in the *** riscv book, copied below +# Tests memory load, store, and execute permissions # | Region | Base Address | Read widths | R | W | X | Cacheable | Idempotent | Atomic | # | ROM | 0x1000 | Any | YES | NO | YES | YES | NO | NO | From 123fdd29cfcbd9a5eb9f3f09a617abad0d75cd31 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 20 Nov 2024 16:30:49 -0800 Subject: [PATCH 062/212] Updated tool portion of README --- README.md | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 40dc08d51..0a060f510 100644 --- a/README.md +++ b/README.md @@ -135,11 +135,17 @@ export VCS_HOME=.. # Change this for your path to Synopsys VCS Electronic Design Automation (EDA) tools are vital to implementations of System on Chip architectures as well as validating different designs. Open-source and commercial tools exist for multiple strategies and although the one can spend a lifetime using combinations of different tools, only a small subset of tools is utilized for this text. The tools are chosen because of their ease in access as well as their repeatability for accomplishing many of the tasks utilized to design Wally. It is anticipated that additional tools may be documented later after this is text is published to improve use and access. -Siemens Questa is the primary tool utilized for simulating and validating Wally. For logic synthesis, you will need Synopsys Design Compiler. Questa and Design Compiler are commercial tools that require an educational or commercial license. +Verilator is an open-source Verilog simulator. It is fast and free. Run Wally on the riscv-arch-test suite using Verilator with: + +``` +regression-wally +``` + +Running code or functional coverage simulations or lock-step presently require commercial tools. Siemens Questa is the primary tool utilized for simulating and validating Wally. Synopsys VCS also can run regression-wally and lock-step simulation. For logic synthesis, you will need Synopsys Design Compiler. Questa and Design Compiler are commercial tools that require an educational or commercial license. Note: Some EDA tools utilize `LM_LICENSE_FILE` for their environmental variable to point to their license server. Some operating systems may also utilize `MGLS_LICENSE_FILE` instead, therefore, it is important to read the user manual on the preferred environmental variable required to point to a user’s license file. Although there are different mechanisms to allow licenses to work, many companies commonly utilize the FlexLM (i.e., Flex-enabled) license server manager that runs off a node locked license. -Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors. Both Red Hat Enterprise Linux and SUSE Linux products typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration. Questa can also be installed on Microsoft Windows as well as Mac OS with a Virtual Machine such as Parallels. +Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors. Red Hat Enterprise Linux (and its free Rocky clone) typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration. ### Siemens Questa From 38acf24d831571eebc421d27399950cc3b979e95 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 20 Nov 2024 19:06:41 -0800 Subject: [PATCH 063/212] Reset code coverage when running regression --- bin/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index 9a2d29201..6f609ffa0 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -519,7 +519,7 @@ def main(): pass if args.ccov: TIMEOUT_DUR = 20*60 # seconds - os.system('rm -f questa/cov/*.ucdb') + os.system('rm -f questa/ucdb/* questa/cov/*') elif args.fcov: TIMEOUT_DUR = 8*60 os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*') From fb59d8e32fc1c173f8cdff7a0a8fb6816205f194 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 20 Nov 2024 19:23:46 -0800 Subject: [PATCH 064/212] More imperas lics --- bin/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index 6f609ffa0..f53940d89 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -536,7 +536,7 @@ def main(): # max out at a limited number of concurrent processes to not overwhelm the system # right now fcov, ccov, nightly all use Imperas if (args.ccov or args.fcov or args.nightly): - ImperasDVLicenseCount = 8 # limit number of concurrent processes to avoid overloading ImperasDV licenses + ImperasDVLicenseCount = 16 # limit number of concurrent processes to avoid overloading ImperasDV licenses else: ImperasDVLicenseCount = 10000 # effectively no license limit for non-lockstep tests with Pool(processes=min(len(configs),multiprocessing.cpu_count(), ImperasDVLicenseCount)) as pool: From 0923fb918f2f79c92fe8aa9e7b999d44bb38acb4 Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Wed, 20 Nov 2024 23:51:29 -0800 Subject: [PATCH 065/212] Add Endian covergroups to fcov --- config/rv32gc/coverage.svh | 3 +++ config/rv64gc/coverage.svh | 3 +++ 2 files changed, 6 insertions(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 93be70707..614cd5c3d 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -37,3 +37,6 @@ `include "ZicsrU_coverage.svh" `include "RV32VM_coverage.svh" `include "RV32VM_PMP_coverage.svh" +`include "EndianU_coverage.svh" +`include "EndianM_coverage.svh" +`include "EndianS_coverage.svh" \ No newline at end of file diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 057e79898..07561b1de 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -36,6 +36,9 @@ `include "ZicsrM_coverage.svh" `include "ZicsrF_coverage.svh" `include "ZicsrU_coverage.svh" +`include "EndianU_coverage.svh" +`include "EndianM_coverage.svh" +`include "EndianS_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" From 6ce4a030f22e34660e205852a9c758f8ff7b6951 Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Thu, 21 Nov 2024 03:20:13 -0800 Subject: [PATCH 066/212] Add ExceptionM to fcov --- config/rv32gc/coverage.svh | 5 +++++ config/rv64gc/coverage.svh | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 93be70707..4b23573e1 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -8,6 +8,10 @@ // Define XLEN, used in covergroups `define XLEN32 1 +// Define relevant addresses +`define CLINT_BASE 64'h02000000 +`define ACCESS_FAULT_ADDRESS 32'h0000 + // Unprivileged extensions `include "RV32I_coverage.svh" `include "RV32M_coverage.svh" @@ -37,3 +41,4 @@ `include "ZicsrU_coverage.svh" `include "RV32VM_coverage.svh" `include "RV32VM_PMP_coverage.svh" +`include "ExceptionM_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 057e79898..1756ec6a4 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -8,6 +8,10 @@ // Define XLEN, used in covergroups `define XLEN64 1 +// Define relevant addresses +`define CLINT_BASE 64'h02000000 +`define ACCESS_FAULT_ADDRESS 64'h00000000 + // Unprivileged extensions `include "RV64I_coverage.svh" `include "RV64M_coverage.svh" @@ -36,6 +40,7 @@ `include "ZicsrM_coverage.svh" `include "ZicsrF_coverage.svh" `include "ZicsrU_coverage.svh" +`include "ExceptionM_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" From 34063f9fb66ae08a57974b52c767ced8d0b570c1 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Thu, 21 Nov 2024 07:01:31 -0800 Subject: [PATCH 067/212] Revert "Add ExceptionM to fcov" --- config/rv32gc/coverage.svh | 5 ----- config/rv64gc/coverage.svh | 5 ----- 2 files changed, 10 deletions(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 4b23573e1..93be70707 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -8,10 +8,6 @@ // Define XLEN, used in covergroups `define XLEN32 1 -// Define relevant addresses -`define CLINT_BASE 64'h02000000 -`define ACCESS_FAULT_ADDRESS 32'h0000 - // Unprivileged extensions `include "RV32I_coverage.svh" `include "RV32M_coverage.svh" @@ -41,4 +37,3 @@ `include "ZicsrU_coverage.svh" `include "RV32VM_coverage.svh" `include "RV32VM_PMP_coverage.svh" -`include "ExceptionM_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 1756ec6a4..057e79898 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -8,10 +8,6 @@ // Define XLEN, used in covergroups `define XLEN64 1 -// Define relevant addresses -`define CLINT_BASE 64'h02000000 -`define ACCESS_FAULT_ADDRESS 64'h00000000 - // Unprivileged extensions `include "RV64I_coverage.svh" `include "RV64M_coverage.svh" @@ -40,7 +36,6 @@ `include "ZicsrM_coverage.svh" `include "ZicsrF_coverage.svh" `include "ZicsrU_coverage.svh" -`include "ExceptionM_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" From 75ce5c8c99bae25dad53929095ebb8010001ca75 Mon Sep 17 00:00:00 2001 From: Georgia Tai Date: Thu, 21 Nov 2024 16:18:44 -0800 Subject: [PATCH 068/212] Code Coverage on Decompress unit --- tests/coverage/ifu.S | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S index eaceb71ce..054f4f336 100644 --- a/tests/coverage/ifu.S +++ b/tests/coverage/ifu.S @@ -50,6 +50,11 @@ main: c.sb s1, 0(s0) // exercise c.sb c.sh s1, 0(s0) // exercise c.sh + .hword 0x2005 // line 110 + .hword 0x6101 // line 114 + .hword 0x6201 // line 115 + .hword 0x0202 // Illegal compressed instruction with op = 10, Instr[15:13] = 000, c.slli x4, 0. Line 151 illegal instruction + .hword 0x4002 // Illegal compressed instruction with op = 10, Instr[15:13] = 010, c.lwsp zero, 0. Line 158 illegal instruction .hword 0x8C44 // Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction .hword 0x9C00 // Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction From cb09ff6bb6d4ab9c0f011a3eb1fc42fb4d9f7794 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 22 Nov 2024 11:32:56 -0800 Subject: [PATCH 069/212] Fix crt0 --- tests/custom/crt0/pre_main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/custom/crt0/pre_main.c b/tests/custom/crt0/pre_main.c index fce61ffdf..3a5166558 100644 --- a/tests/custom/crt0/pre_main.c +++ b/tests/custom/crt0/pre_main.c @@ -2,6 +2,8 @@ #include "pcnt_driver.h" +extern int main(int argc, char *argv[]); + int pre_main(int argc, char *argv[]) { long int bpmp0, brcnt0, bpmp1, brcnt1; long int bpmp_diff, brcnt_diff; From c6bd7bbefcdf74d7c48b8360805a6bb399c3b06a Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 23 Nov 2024 18:36:49 -0800 Subject: [PATCH 070/212] Update distro check print formatting --- bin/wally-distro-check.sh | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/bin/wally-distro-check.sh b/bin/wally-distro-check.sh index 92d284b05..8f4af6958 100755 --- a/bin/wally-distro-check.sh +++ b/bin/wally-distro-check.sh @@ -41,32 +41,36 @@ ENDC='\033[0m' # Reset to default color # Print section header section_header() { if tput cols > /dev/null 2>&1; then - printf "${SECTION_COLOR}%$(tput cols)s" | tr ' ' '#' - printf "%$(tput cols)s" | tr ' ' '#' - echo -e "$1" - printf "%$(tput cols)s" | tr ' ' '#' - printf "%$(tput cols)s${ENDC}" | tr ' ' '#' + printf "${SECTION_COLOR}%$(tput cols)s\n" | tr ' ' '#' + printf "%$(tput cols)s\n" | tr ' ' '#' + printf "%s\n" "$1" + printf "%$(tput cols)s\n" | tr ' ' '#' + printf "%$(tput cols)s${ENDC}\n" | tr ' ' '#' else - echo -e "${SECTION_COLOR}$1${ENDC}" + printf "${SECTION_COLOR}%s\n${ENDC}" "$1" fi } section_header "Checking System Requirements and Configuring Installation" # Get distribution information -test -e /etc/os-release && os_release="/etc/os-release" || os_release="/usr/lib/os-release" -source "$os_release" +if [ -f /etc/os-release ]; then + source /etc/os-release +else + printf "${FAIL_COLOR}%s\n${ENDC}" "/etc/os-release file not found. Distribution unknown." + PRETTY_NAME=UNKNOWN +fi # Check for compatible distro if [[ "$ID" == rhel || "$ID_LIKE" == *rhel* ]]; then export FAMILY=rhel if [ "$ID" != rhel ] && [ "$ID" != rocky ] && [ "$ID" != almalinux ]; then - printf "${WARNING_COLOR}%s\n${ENDC}" "For Red Hat family distros, the Wally install script has only been tested on RHEL, Rocky Linux," \ + printf "${WARNING_COLOR}%s%s\n${ENDC}" "For Red Hat family distros, the Wally install script has only been tested on RHEL, Rocky Linux," \ " and AlmaLinux. Your distro is $PRETTY_NAME. The regular Red Hat install will be attempted, but there may be issues." fi export RHEL_VERSION="${VERSION_ID:0:1}" if (( RHEL_VERSION < 8 )); then - echo "${FAIL_COLOR}The Wally install script is only compatible with versions 8 and 9 of RHEL, Rocky Linux, and AlmaLinux. You have version $VERSION.${ENDC}" + printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally install script is only compatible with versions 8 and 9 of RHEL, Rocky Linux, and AlmaLinux. You have version $VERSION." exit 1 fi elif [[ "$ID" == ubuntu || "$ID_LIKE" == *ubuntu* ]]; then @@ -77,16 +81,16 @@ elif [[ "$ID" == ubuntu || "$ID_LIKE" == *ubuntu* ]]; then fi export UBUNTU_VERSION="${VERSION_ID:0:2}" if (( UBUNTU_VERSION < 20 )); then - echo "${FAIL_COLOR}The Wally install script has only been tested with versions 20.04 LTS, 22.04 LTS, and 24.04 LTS of Ubuntu. You have version $VERSION.${ENDC}" + printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally install script has only been tested with Ubuntu versions 20.04 LTS, 22.04 LTS, and 24.04 LTS. You have version $VERSION." exit 1 fi else - printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally install script is currently only compatible with Ubuntu and Red Hat family " \ + printf "${FAIL_COLOR}%s%s%s\n${ENDC}" "The Wally install script is currently only compatible with Ubuntu and Red Hat family " \ "(RHEL, Rocky Linux, or AlmaLinux) distros. Your detected distro is $PRETTY_NAME. You may try manually running the " \ "commands in this script, but it is likely that some will need to be altered." exit 1 fi -echo -e "${OK_COLOR}${UNDERLINE}Detected information${ENDC}" +printf "${OK_COLOR}${UNDERLINE}%s\n${ENDC}" "Detected information" echo "Distribution: $PRETTY_NAME" echo "Version: $VERSION" From 4ff7289803c9cd66eb11d92f9e2ddfb4bf3d5b0f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 23 Nov 2024 19:27:07 -0800 Subject: [PATCH 071/212] Fix installation comments --- bin/wally-tool-chain-install.sh | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 8fe418272..1ba69ca16 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -118,7 +118,7 @@ if [ "$1" == "--clean" ] || [ "$2" == "--clean" ]; then shift fi -# Check for clean flag +# Check for no-buildroot flag if [ "$1" == "--no-buildroot" ] || [ "$2" == "--no-buildroot" ]; then no_buidroot=true shift @@ -269,11 +269,10 @@ fi # and the GNU Debugger Project (gdb). It is a collection of tools used to compile RISC-V programs. # To install GCC from source can take hours to compile. # This configuration enables multilib to target many flavors of RISC-V. -# This book is tested with GCC 13.2.0 +# This book is tested with GCC 13.2.0 and 14.2.0. section_header "Installing/Updating RISC-V GNU Toolchain" STATUS="riscv-gnu-toolchain" cd "$RISCV" -# Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension. if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2"; then cd "$RISCV"/riscv-gnu-toolchain git reset --hard && git clean -f && git checkout master && git pull && git submodule update From f11799385e56272647dc8aa02951e7563c3de555 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 23 Nov 2024 20:04:39 -0800 Subject: [PATCH 072/212] Add support for debian 12 to install script --- bin/wally-distro-check.sh | 11 +++++++++++ bin/wally-package-install.sh | 7 +++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/bin/wally-distro-check.sh b/bin/wally-distro-check.sh index 8f4af6958..bd4de121b 100755 --- a/bin/wally-distro-check.sh +++ b/bin/wally-distro-check.sh @@ -84,6 +84,17 @@ elif [[ "$ID" == ubuntu || "$ID_LIKE" == *ubuntu* ]]; then printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally install script has only been tested with Ubuntu versions 20.04 LTS, 22.04 LTS, and 24.04 LTS. You have version $VERSION." exit 1 fi +elif [[ "$ID" == debian || "$ID_LIKE" == *debian* ]]; then + export FAMILY=debian + if [ "$ID" != debian ]; then + printf "${WARNING_COLOR}%s\n${ENDC}" "For Debian family distros, the Wally install script has only been tested on standard Debian (and Ubuntu). Your distro " \ + "is $PRETTY_NAME. The regular Debian install will be attempted, but there may be issues." + fi + export DEBIAN_VERSION="$VERSION_ID" + if (( DEBIAN_VERSION < 12 )); then + printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally install script has only been tested with Debian version 12. You have version $VERSION." + exit 1 + fi else printf "${FAIL_COLOR}%s%s%s\n${ENDC}" "The Wally install script is currently only compatible with Ubuntu and Red Hat family " \ "(RHEL, Rocky Linux, or AlmaLinux) distros. Your detected distro is $PRETTY_NAME. You may try manually running the " \ diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index 1fc003189..aadfed2b0 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -61,7 +61,7 @@ if [ "$FAMILY" == rhel ]; then fi # A newer version of gcc is required for qemu OTHER_PACKAGES=(gcc-toolset-13) -elif [ "$FAMILY" == ubuntu ]; then +elif [[ "$FAMILY" == ubuntu || "$FAMILY" == debian ]]; then if (( UBUNTU_VERSION >= 24 )); then PYTHON_VERSION=python3.12 VERILATOR_PACKAGES+=(mold) # Not availale in Ubuntu 20.04, nice for Verilator @@ -71,11 +71,14 @@ elif [ "$FAMILY" == ubuntu ]; then elif (( UBUNTU_VERSION >= 20 )); then PYTHON_VERSION=python3.9 OTHER_PACKAGES+=(gcc-10 g++-10 cpp-10) # Newer version of gcc needed for Verilator + elif (( DEBIAN_VERSION >= 12 )); then + PYTHON_VERSION=python3.11 + VERILATOR_PACKAGES+=(mold) # Not availale in Ubuntu 20.04, nice for Verilator fi PACKAGE_MANAGER="DEBIAN_FRONTEND=noninteractive apt-get" UPDATE_COMMAND="sudo $PACKAGE_MANAGER update -y && sudo $PACKAGE_MANAGER upgrade -y --with-new-pkgs" GENERAL_PACKAGES+=(rsync git make cmake "$PYTHON_VERSION" python3-pip "$PYTHON_VERSION"-venv curl wget tar pkg-config dialog mutt ssmtp) - GNU_PACKAGES+=(autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev) + GNU_PACKAGES+=(autoconf automake autotools-dev libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev) QEMU_PACKAGES+=(libfdt-dev libpixman-1-dev) SPIKE_PACKAGES+=(device-tree-compiler libboost-regex-dev libboost-system-dev) VERILATOR_PACKAGES+=(help2man perl g++ clang ccache libunwind-dev libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g) From 3e9d5a48df8fbf35505eeefe42e0ffb017d6c681 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 23 Nov 2024 20:15:25 -0800 Subject: [PATCH 073/212] Add debian 12 to installation CI and update matrix formation --- .github/workflows/install.yml | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index b065cd924..c78b6b195 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -38,25 +38,37 @@ jobs: - name: ubuntu-20.04 os: ubuntu-20.04 container: null + regresssionFail: true - name: ubuntu-22.04 os: ubuntu-22.04 container: null - name: ubuntu-24.04 os: ubuntu-24.04 container: null + # Debian Installations + - name: debian-12 + os: ubuntu-latest + image: debian:12 + imageFamily: debian # Red Hat Installations - name: rocky-8 os: ubuntu-latest image: rockylinux:8 + imageFamily: redhat + regressionFail: true - name: rocky-9 os: ubuntu-latest image: rockylinux:9 + imageFamily: redhat - name: almalinux-8 os: ubuntu-latest image: almalinux:8 + imageFamily: redhat + regressionFail: true - name: almalinux-9 os: ubuntu-latest image: almalinux:9 + imageFamily: redhat # User level installation - name: user-install os: ubuntu-latest @@ -82,11 +94,16 @@ jobs: steps: # Docker images need git installed or the checkout action fails - - name: Install Dependencies for Red Hat + - name: Install Dependencies for Container Image if: ${{ matrix.image != null }} run: | - dnf install -y sudo git - dnf install curl -y --allowerasing || true + if [ ${{ matrix.imageFamily }} == "debian" ]; then + apt-get update + apt-get install -y sudo git + elif [ ${{ matrix.imageFamily }} == "redhat" ]; then + dnf install -y sudo git + dnf install curl -y --allowerasing || true + fi # Only clone submodules needed for standard tests/regression to save space - uses: actions/checkout@v4 - name: Clone Necessary Submodules @@ -140,12 +157,12 @@ jobs: df -h # Run standard regression, skipping distros that are known to be broken with Verilator - name: Regression - if: ${{ matrix.name != 'ubuntu-20.04' && matrix.name != 'rocky-8' && matrix.name != 'almalinux-8'}} + if: ${{ matrix.regressionFail != true }} run: | source setup.sh regression-wally - name: Lint + wsim Test Only (for distros with broken Verilator sim) - if: ${{ matrix.name == 'ubuntu-20.04' || matrix.name == 'rocky-8' || matrix.name == 'almalinux-8'}} + if: ${{ matrix.regressionFail == true }} run: | source setup.sh mkdir -p $WALLY/sim/verilator/logs/ From 4f5db12b2cb441a444eb09e996db77c4870dca57 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 23 Nov 2024 21:32:42 -0800 Subject: [PATCH 074/212] Download binary for mold on Ubuntu 20.04 --- bin/wally-package-install.sh | 5 ++--- bin/wally-tool-chain-install.sh | 9 +++++++++ 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index aadfed2b0..e780298bd 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -64,16 +64,15 @@ if [ "$FAMILY" == rhel ]; then elif [[ "$FAMILY" == ubuntu || "$FAMILY" == debian ]]; then if (( UBUNTU_VERSION >= 24 )); then PYTHON_VERSION=python3.12 - VERILATOR_PACKAGES+=(mold) # Not availale in Ubuntu 20.04, nice for Verilator elif (( UBUNTU_VERSION >= 22 )); then PYTHON_VERSION=python3.11 - VERILATOR_PACKAGES+=(mold) # Not availale in Ubuntu 20.04, nice for Verilator elif (( UBUNTU_VERSION >= 20 )); then PYTHON_VERSION=python3.9 OTHER_PACKAGES+=(gcc-10 g++-10 cpp-10) # Newer version of gcc needed for Verilator elif (( DEBIAN_VERSION >= 12 )); then PYTHON_VERSION=python3.11 - VERILATOR_PACKAGES+=(mold) # Not availale in Ubuntu 20.04, nice for Verilator + if (( UBUNTU_VERSION != 20 )); then + VERILATOR_PACKAGES+=(mold) # Not availale in Ubuntu 20.04, binary will be downloaded instead fi PACKAGE_MANAGER="DEBIAN_FRONTEND=noninteractive apt-get" UPDATE_COMMAND="sudo $PACKAGE_MANAGER update -y && sudo $PACKAGE_MANAGER upgrade -y --with-new-pkgs" diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 1ba69ca16..c22aed822 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -263,6 +263,15 @@ if (( RHEL_VERSION == 8 )); then fi fi +# Mold needed for Verilator +if (( UBUNTU_VERSION == 20 )); then + STATUS="mold" + if [ ! -e "$RISCV"/bin/mold ]; then + section_header "Installing mold" + cd "$RISCV" + wget -nv --retry-connrefused $retry_on_host_error https://github.com/rui314/mold/releases/download/v2.34.1/mold-2.34.1-x86_64-linux.tar.gz + fi +fi # RISC-V GNU Toolchain (https://github.com/riscv-collab/riscv-gnu-toolchain) # The RISC-V GNU Toolchain includes the GNU Compiler Collection (gcc), GNU Binutils, Newlib, From 6e680ae5613bd5d24ea7b71fb1527d821b99be25 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 23 Nov 2024 21:51:57 -0800 Subject: [PATCH 075/212] Add support for Debian 11 to installation script --- bin/wally-distro-check.sh | 4 ++-- bin/wally-package-install.sh | 8 ++++++-- bin/wally-tool-chain-install.sh | 2 +- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/bin/wally-distro-check.sh b/bin/wally-distro-check.sh index bd4de121b..5dfbf015e 100755 --- a/bin/wally-distro-check.sh +++ b/bin/wally-distro-check.sh @@ -91,8 +91,8 @@ elif [[ "$ID" == debian || "$ID_LIKE" == *debian* ]]; then "is $PRETTY_NAME. The regular Debian install will be attempted, but there may be issues." fi export DEBIAN_VERSION="$VERSION_ID" - if (( DEBIAN_VERSION < 12 )); then - printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally install script has only been tested with Debian version 12. You have version $VERSION." + if (( DEBIAN_VERSION < 11 )); then + printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally install script has only been tested with Debian versions 11 and 12. You have version $VERSION." exit 1 fi else diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index e780298bd..fe3c9bf1c 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -71,8 +71,12 @@ elif [[ "$FAMILY" == ubuntu || "$FAMILY" == debian ]]; then OTHER_PACKAGES+=(gcc-10 g++-10 cpp-10) # Newer version of gcc needed for Verilator elif (( DEBIAN_VERSION >= 12 )); then PYTHON_VERSION=python3.11 - if (( UBUNTU_VERSION != 20 )); then - VERILATOR_PACKAGES+=(mold) # Not availale in Ubuntu 20.04, binary will be downloaded instead + elif (( DEBIAN_VERSION >= 11 )); then + PYTHON_VERSION=python3.9 + fi + # Mold not available in older distros for Verilator, will download binary instead + if (( UBUNTU_VERSION != 20 && DEBIAN_VERSION != 11 )); then + VERILATOR_PACKAGES+=(mold) fi PACKAGE_MANAGER="DEBIAN_FRONTEND=noninteractive apt-get" UPDATE_COMMAND="sudo $PACKAGE_MANAGER update -y && sudo $PACKAGE_MANAGER upgrade -y --with-new-pkgs" diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index c22aed822..10c4276c7 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -264,7 +264,7 @@ if (( RHEL_VERSION == 8 )); then fi # Mold needed for Verilator -if (( UBUNTU_VERSION == 20 )); then +if (( UBUNTU_VERSION == 20 || DEBIAN_VERSION == 11 )); then STATUS="mold" if [ ! -e "$RISCV"/bin/mold ]; then section_header "Installing mold" From 5382b481e8338b06ac330dc1fdb8858a138a9a4e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 23 Nov 2024 22:01:48 -0800 Subject: [PATCH 076/212] Fix mold install --- bin/wally-tool-chain-install.sh | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 10c4276c7..4bfa2c9a3 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -269,7 +269,12 @@ if (( UBUNTU_VERSION == 20 || DEBIAN_VERSION == 11 )); then if [ ! -e "$RISCV"/bin/mold ]; then section_header "Installing mold" cd "$RISCV" - wget -nv --retry-connrefused $retry_on_host_error https://github.com/rui314/mold/releases/download/v2.34.1/mold-2.34.1-x86_64-linux.tar.gz + wget -nv --retry-connrefused $retry_on_host_error --output-document=mold.tar.gz https://github.com/rui314/mold/releases/download/v2.34.1/mold-2.34.1-x86_64-linux.tar.gz + tar xz --directory="$RISCV" --strip-components=1 -f mold.tar.gz + rm -f mold.tar.gz + echo -e "${SUCCESS_COLOR}Mold successfully installed/updated!${ENDC}" + else + echo -e "${SUCCESS_COLOR}Mold already installed.${ENDC}" fi fi From 242611c8ea392efb5eb60e9e703fd96504ca5f0d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 23 Nov 2024 22:08:29 -0800 Subject: [PATCH 077/212] Debian images don't have unzip installed by default; used by Buildroot --- bin/wally-package-install.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index fe3c9bf1c..69dccbc6c 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -80,7 +80,7 @@ elif [[ "$FAMILY" == ubuntu || "$FAMILY" == debian ]]; then fi PACKAGE_MANAGER="DEBIAN_FRONTEND=noninteractive apt-get" UPDATE_COMMAND="sudo $PACKAGE_MANAGER update -y && sudo $PACKAGE_MANAGER upgrade -y --with-new-pkgs" - GENERAL_PACKAGES+=(rsync git make cmake "$PYTHON_VERSION" python3-pip "$PYTHON_VERSION"-venv curl wget tar pkg-config dialog mutt ssmtp) + GENERAL_PACKAGES+=(rsync git make cmake "$PYTHON_VERSION" python3-pip "$PYTHON_VERSION"-venv curl wget tar unzip pkg-config dialog mutt ssmtp) GNU_PACKAGES+=(autoconf automake autotools-dev libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev) QEMU_PACKAGES+=(libfdt-dev libpixman-1-dev) SPIKE_PACKAGES+=(device-tree-compiler libboost-regex-dev libboost-system-dev) From 459b86b22ad63bd253528d3f90987bd73f244904 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 23 Nov 2024 22:09:38 -0800 Subject: [PATCH 078/212] Add Debian 11 to build matrix --- .github/workflows/install.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index c78b6b195..c7c9bd9e1 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -50,6 +50,10 @@ jobs: os: ubuntu-latest image: debian:12 imageFamily: debian + - name: debian-11 + os: ubuntu-latest + image: debian:11 + imageFamily: debian # Red Hat Installations - name: rocky-8 os: ubuntu-latest From 42bf426e1c0e8f362cc8ffd46fbfc19965e3a921 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 24 Nov 2024 01:32:20 -0800 Subject: [PATCH 079/212] Fix typo --- .github/workflows/install.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index c7c9bd9e1..ff0e93181 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -38,7 +38,7 @@ jobs: - name: ubuntu-20.04 os: ubuntu-20.04 container: null - regresssionFail: true + regressionFail: true - name: ubuntu-22.04 os: ubuntu-22.04 container: null From 48ac38fb35e90aa70d6af835fdf3e948f2ec08c8 Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Sun, 24 Nov 2024 03:43:57 -0800 Subject: [PATCH 080/212] Add exceptionsM to fcov --- config/rv32gc/coverage.svh | 7 ++++++- config/rv64gc/coverage.svh | 5 +++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 614cd5c3d..d3953b916 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -8,6 +8,10 @@ // Define XLEN, used in covergroups `define XLEN32 1 +// Define relevant addresses +`define CLINT_BASE 64'h02000000 +`define ACCESS_FAULT_ADDRESS 32'h0000 + // Unprivileged extensions `include "RV32I_coverage.svh" `include "RV32M_coverage.svh" @@ -39,4 +43,5 @@ `include "RV32VM_PMP_coverage.svh" `include "EndianU_coverage.svh" `include "EndianM_coverage.svh" -`include "EndianS_coverage.svh" \ No newline at end of file +`include "EndianS_coverage.svh" +`include "ExceptionsM_coverage.svh" \ No newline at end of file diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 07561b1de..3974d7f96 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -8,6 +8,10 @@ // Define XLEN, used in covergroups `define XLEN64 1 +// Define relevant addresses +`define CLINT_BASE 64'h02000000 +`define ACCESS_FAULT_ADDRESS 64'h00000000 + // Unprivileged extensions `include "RV64I_coverage.svh" `include "RV64M_coverage.svh" @@ -39,6 +43,7 @@ `include "EndianU_coverage.svh" `include "EndianM_coverage.svh" `include "EndianS_coverage.svh" +`include "ExceptionsM_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" From 26d635c0ac6e9fe63da5ed9438ff50f17e325fc9 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 24 Nov 2024 12:57:03 -0800 Subject: [PATCH 081/212] Factor out packags that are common across distros for easier maintenance --- bin/wally-package-install.sh | 36 +++++++++++++++++++++--------------- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index 69dccbc6c..dad2f9746 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -43,18 +43,24 @@ if [ -z "$FAMILY" ]; then fi -# Generate list of packages to install and package manager commands based on distro # Packages are grouped by which tool requires them. If multiple tools need a package, it is included in the first tool only +# Packages that are constant across distros +GENERAL_PACKAGES+=(rsync git make cmake curl wget tar unzip bzip2 dialog mutt ssmtp) +GNU_PACKAGES+=(autoconf automake gawk bison flex texinfo gperf libtool ninja-build patchutils bc gcc) +VERILATOR_PACKAGES+=(help2man perl clang ccache numactl) +BUILDROOT_PACKAGES+=(ncurses-base cpio) + +# Distro specific packages and package manager if [ "$FAMILY" == rhel ]; then PYTHON_VERSION=python3.12 - PACKAGE_MANAGER="dnf" - UPDATE_COMMAND="sudo $PACKAGE_MANAGER update -y" - GENERAL_PACKAGES+=(which rsync git make cmake "$PYTHON_VERSION" "$PYTHON_VERSION"-pip curl wget tar pkgconf-pkg-config dialog mutt ssmtp) - GNU_PACKAGES+=(autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel) - QEMU_PACKAGES+=(glib2-devel libfdt-devel pixman-devel bzip2 ninja-build) + PACKAGE_MANAGER="dnf -y" + UPDATE_COMMAND="sudo $PACKAGE_MANAGER update" + GENERAL_PACKAGES+=(which "$PYTHON_VERSION" "$PYTHON_VERSION"-pip pkgconf-pkg-config gcc-c++) + GNU_PACKAGES+=(libmpc-devel mpfr-devel gmp-devel zlib-devel expat-devel libslirp-devel) + QEMU_PACKAGES+=(glib2-devel libfdt-devel pixman-devel) SPIKE_PACKAGES+=(dtc boost-regex boost-system) - VERILATOR_PACKAGES+=(help2man perl clang ccache gperftools numactl mold) - BUILDROOT_PACKAGES+=(ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran cpio) # gcc-gfortran is only needed for compiling spec benchmarks on buildroot linux + VVERILATOR_PACKAGES+=(gperftools mold) + BUILDROOT_PACKAGES+=(ncurses ncurses-libs ncurses-devel gcc-gfortran) # gcc-gfortran is only needed for compiling spec benchmarks on buildroot linux # Extra packages not availale in rhel8, nice for Verilator if (( RHEL_VERSION >= 9 )); then VERILATOR_PACKAGES+=(perl-doc) @@ -78,14 +84,14 @@ elif [[ "$FAMILY" == ubuntu || "$FAMILY" == debian ]]; then if (( UBUNTU_VERSION != 20 && DEBIAN_VERSION != 11 )); then VERILATOR_PACKAGES+=(mold) fi - PACKAGE_MANAGER="DEBIAN_FRONTEND=noninteractive apt-get" - UPDATE_COMMAND="sudo $PACKAGE_MANAGER update -y && sudo $PACKAGE_MANAGER upgrade -y --with-new-pkgs" - GENERAL_PACKAGES+=(rsync git make cmake "$PYTHON_VERSION" python3-pip "$PYTHON_VERSION"-venv curl wget tar unzip pkg-config dialog mutt ssmtp) - GNU_PACKAGES+=(autoconf automake autotools-dev libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev) + PACKAGE_MANAGER="DEBIAN_FRONTEND=noninteractive apt-get -y" + UPDATE_COMMAND="sudo $PACKAGE_MANAGER update && sudo $PACKAGE_MANAGER upgrade --with-new-pkgs" + GENERAL_PACKAGES+=("$PYTHON_VERSION" python3-pip "$PYTHON_VERSION"-venv pkg-config g++) + GNU_PACKAGES+=(autotools-dev libmpc-dev libmpfr-dev libgmp-dev build-essential zlib1g-dev libexpat1-dev libglib2.0-dev libslirp-dev) QEMU_PACKAGES+=(libfdt-dev libpixman-1-dev) SPIKE_PACKAGES+=(device-tree-compiler libboost-regex-dev libboost-system-dev) - VERILATOR_PACKAGES+=(help2man perl g++ clang ccache libunwind-dev libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g) - BUILDROOT_PACKAGES+=(ncurses-base ncurses-bin libncurses-dev gfortran cpio) # gfortran is only needed for compiling spec benchmarks on buildroot linux + VERILATOR_PACKAGES+=(libunwind-dev libgoogle-perftools-dev perl-doc libfl2 libfl-dev zlib1g) + BUILDROOT_PACKAGES+=(ncurses-bin libncurses-dev gfortran) # gfortran is only needed for compiling spec benchmarks on buildroot linux VIVADO_PACKAGES+=(libncurses*) # Vivado hangs on the third stage of installation without this fi @@ -128,7 +134,7 @@ else # Update and Upgrade tools eval "$UPDATE_COMMAND" # Install packages listed above using appropriate package manager - sudo $PACKAGE_MANAGER install -y "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}" "${VIVADO_PACKAGES[@]}" + sudo $PACKAGE_MANAGER install "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}" "${VIVADO_PACKAGES[@]}" # Post install steps # Vivado looks for ncurses5 libraries, but Ubuntu 24.04 only has ncurses6 From 1eac4af940521b7a8466712a0934c3fdb33ae071 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 24 Nov 2024 13:03:59 -0800 Subject: [PATCH 082/212] Fix installation failure message to include Debian --- bin/wally-distro-check.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/wally-distro-check.sh b/bin/wally-distro-check.sh index 5dfbf015e..399ee2071 100755 --- a/bin/wally-distro-check.sh +++ b/bin/wally-distro-check.sh @@ -96,7 +96,7 @@ elif [[ "$ID" == debian || "$ID_LIKE" == *debian* ]]; then exit 1 fi else - printf "${FAIL_COLOR}%s%s%s\n${ENDC}" "The Wally install script is currently only compatible with Ubuntu and Red Hat family " \ + printf "${FAIL_COLOR}%s%s%s\n${ENDC}" "The Wally install script is currently only compatible with Ubuntu, Debian, and Red Hat family " \ "(RHEL, Rocky Linux, or AlmaLinux) distros. Your detected distro is $PRETTY_NAME. You may try manually running the " \ "commands in this script, but it is likely that some will need to be altered." exit 1 From 99047ae8c41be44d2225ac38345e7029ff7cf589 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 24 Nov 2024 13:10:33 -0800 Subject: [PATCH 083/212] Add Debian support to README --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index e302e33f6..e26454b1a 100644 --- a/README.md +++ b/README.md @@ -71,7 +71,7 @@ Then fork and clone the repo, source setup, make the tests and run regression > This section describes the open source toolchain installation. ### Compatibility -The current version of the toolchain has been tested on Ubuntu (versions 20.04 LTS, 22.04 LTS, and 24.04 LTS) and on Red Hat/Rocky/AlmaLinux (versions 8 and 9). +The current version of the toolchain has been tested on Ubuntu (versions 20.04 LTS, 22.04 LTS, and 24.04 LTS), Debian (versions 11 and 12), and Red Hat/Rocky/AlmaLinux (versions 8 and 9). Only the latest minor release of each major version is tested. > [!WARNING] > - Ubuntu 22.04LTS is incompatible with Synopsys Design Compiler. From 064d9fda9191144d919c92220cde955d157f0cf2 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 24 Nov 2024 15:48:34 -0800 Subject: [PATCH 084/212] Add debian to package check --- bin/wally-package-install.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index dad2f9746..318cb51ac 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -103,7 +103,7 @@ if [ "${1}" == "--check" ]; then for pack in "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}"; do rpm -q "$pack" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first.${ENDC}" && exit 1) done - elif [ "$FAMILY" == ubuntu ]; then + elif [[ "$FAMILY" == ubuntu || "$FAMILY" == debian ]]; then for pack in "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}"; do dpkg -l "$pack" | grep "ii" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first." && exit 1) done From 81f036088d1e62df281baa18847b40266fd64185 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 24 Nov 2024 15:51:57 -0800 Subject: [PATCH 085/212] Fix installation messages --- bin/wally-distro-check.sh | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/bin/wally-distro-check.sh b/bin/wally-distro-check.sh index 399ee2071..db0699fd2 100755 --- a/bin/wally-distro-check.sh +++ b/bin/wally-distro-check.sh @@ -65,38 +65,38 @@ fi if [[ "$ID" == rhel || "$ID_LIKE" == *rhel* ]]; then export FAMILY=rhel if [ "$ID" != rhel ] && [ "$ID" != rocky ] && [ "$ID" != almalinux ]; then - printf "${WARNING_COLOR}%s%s\n${ENDC}" "For Red Hat family distros, the Wally install script has only been tested on RHEL, Rocky Linux," \ + printf "${WARNING_COLOR}%s%s\n${ENDC}" "For Red Hat family distros, the Wally installation script has only been tested on RHEL, Rocky Linux," \ " and AlmaLinux. Your distro is $PRETTY_NAME. The regular Red Hat install will be attempted, but there may be issues." fi export RHEL_VERSION="${VERSION_ID:0:1}" if (( RHEL_VERSION < 8 )); then - printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally install script is only compatible with versions 8 and 9 of RHEL, Rocky Linux, and AlmaLinux. You have version $VERSION." + printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally installation script is only compatible with versions 8 and 9 of RHEL, Rocky Linux, and AlmaLinux. You have version $VERSION." exit 1 fi elif [[ "$ID" == ubuntu || "$ID_LIKE" == *ubuntu* ]]; then export FAMILY=ubuntu if [ "$ID" != ubuntu ]; then - printf "${WARNING_COLOR}%s\n${ENDC}" "For Ubuntu family distros, the Wally install script has only been tested on standard Ubuntu. Your distro " \ + printf "${WARNING_COLOR}%s%s\n${ENDC}" "For Ubuntu family distros, the Wally installation script has only been tested on standard Ubuntu. Your distro " \ "is $PRETTY_NAME. The regular Ubuntu install will be attempted, but there may be issues." fi export UBUNTU_VERSION="${VERSION_ID:0:2}" if (( UBUNTU_VERSION < 20 )); then - printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally install script has only been tested with Ubuntu versions 20.04 LTS, 22.04 LTS, and 24.04 LTS. You have version $VERSION." + printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally installation script has only been tested with Ubuntu versions 20.04 LTS, 22.04 LTS, and 24.04 LTS. You have version $VERSION." exit 1 fi elif [[ "$ID" == debian || "$ID_LIKE" == *debian* ]]; then export FAMILY=debian if [ "$ID" != debian ]; then - printf "${WARNING_COLOR}%s\n${ENDC}" "For Debian family distros, the Wally install script has only been tested on standard Debian (and Ubuntu). Your distro " \ + printf "${WARNING_COLOR}%s%s\n${ENDC}" "For Debian family distros, the Wally installation script has only been tested on standard Debian (and Ubuntu). Your distro " \ "is $PRETTY_NAME. The regular Debian install will be attempted, but there may be issues." fi export DEBIAN_VERSION="$VERSION_ID" if (( DEBIAN_VERSION < 11 )); then - printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally install script has only been tested with Debian versions 11 and 12. You have version $VERSION." + printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally installation script has only been tested with Debian versions 11 and 12. You have version $VERSION." exit 1 fi else - printf "${FAIL_COLOR}%s%s%s\n${ENDC}" "The Wally install script is currently only compatible with Ubuntu, Debian, and Red Hat family " \ + printf "${FAIL_COLOR}%s%s%s\n${ENDC}" "The Wally installation script is currently only compatible with Ubuntu, Debian, and Red Hat family " \ "(RHEL, Rocky Linux, or AlmaLinux) distros. Your detected distro is $PRETTY_NAME. You may try manually running the " \ "commands in this script, but it is likely that some will need to be altered." exit 1 From cb73b927ace272df7dc8d3fc4f53b34fa5afbce5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 24 Nov 2024 15:52:22 -0800 Subject: [PATCH 086/212] Add SUSE detection --- bin/wally-distro-check.sh | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/bin/wally-distro-check.sh b/bin/wally-distro-check.sh index db0699fd2..c7a540c34 100755 --- a/bin/wally-distro-check.sh +++ b/bin/wally-distro-check.sh @@ -95,6 +95,17 @@ elif [[ "$ID" == debian || "$ID_LIKE" == *debian* ]]; then printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally installation script has only been tested with Debian versions 11 and 12. You have version $VERSION." exit 1 fi +elif [[ "$ID" == opensuse-leap || "$ID" == sles || "$ID_LIKE" == *suse* ]]; then + export FAMILY=suse + if [[ "$ID" != opensuse-leap && "$ID" != sles ]]; then + printf "${WARNING_COLOR}%s%s\n${ENDC}" "For SUSE family distros, the Wally installation script has only been tested on OpenSUSE Leap and SLES. Your distro " \ + "is $PRETTY_NAME. The regular SUSE install will be attempted, but there may be issues. If you are using OpenSUSE Tumbleweed, the version check will fail." + fi + export SUSE_VERSION="${VERSION_ID//.}" + if (( SUSE_VERSION < 156 )); then + printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally installation script has only been tested with SUSE version 15.6. You have version $VERSION." + exit 1 + fi else printf "${FAIL_COLOR}%s%s%s\n${ENDC}" "The Wally installation script is currently only compatible with Ubuntu, Debian, and Red Hat family " \ "(RHEL, Rocky Linux, or AlmaLinux) distros. Your detected distro is $PRETTY_NAME. You may try manually running the " \ From 9724bb64c58e3bee2048731f00621e1ccf635e9f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 24 Nov 2024 15:52:55 -0800 Subject: [PATCH 087/212] Add suse packages --- bin/wally-package-install.sh | 108 ++++++++++++++++++-------------- bin/wally-tool-chain-install.sh | 8 ++- site-setup.sh | 2 + 3 files changed, 71 insertions(+), 47 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index 318cb51ac..836a5625f 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -45,61 +45,77 @@ fi # Packages are grouped by which tool requires them. If multiple tools need a package, it is included in the first tool only # Packages that are constant across distros -GENERAL_PACKAGES+=(rsync git make cmake curl wget tar unzip bzip2 dialog mutt ssmtp) -GNU_PACKAGES+=(autoconf automake gawk bison flex texinfo gperf libtool ninja-build patchutils bc gcc) +GENERAL_PACKAGES+=(rsync git make cmake curl wget tar unzip bzip2 dialog mutt) +GNU_PACKAGES+=(autoconf automake gawk bison flex texinfo gperf libtool patchutils bc gcc) VERILATOR_PACKAGES+=(help2man perl clang ccache numactl) -BUILDROOT_PACKAGES+=(ncurses-base cpio) +BUILDROOT_PACKAGES+=(cpio) # Distro specific packages and package manager -if [ "$FAMILY" == rhel ]; then - PYTHON_VERSION=python3.12 - PACKAGE_MANAGER="dnf -y" - UPDATE_COMMAND="sudo $PACKAGE_MANAGER update" - GENERAL_PACKAGES+=(which "$PYTHON_VERSION" "$PYTHON_VERSION"-pip pkgconf-pkg-config gcc-c++) - GNU_PACKAGES+=(libmpc-devel mpfr-devel gmp-devel zlib-devel expat-devel libslirp-devel) - QEMU_PACKAGES+=(glib2-devel libfdt-devel pixman-devel) - SPIKE_PACKAGES+=(dtc boost-regex boost-system) - VVERILATOR_PACKAGES+=(gperftools mold) - BUILDROOT_PACKAGES+=(ncurses ncurses-libs ncurses-devel gcc-gfortran) # gcc-gfortran is only needed for compiling spec benchmarks on buildroot linux - # Extra packages not availale in rhel8, nice for Verilator - if (( RHEL_VERSION >= 9 )); then - VERILATOR_PACKAGES+=(perl-doc) - fi - # A newer version of gcc is required for qemu - OTHER_PACKAGES=(gcc-toolset-13) -elif [[ "$FAMILY" == ubuntu || "$FAMILY" == debian ]]; then - if (( UBUNTU_VERSION >= 24 )); then +case "$FAMILY" in + rhel) PYTHON_VERSION=python3.12 - elif (( UBUNTU_VERSION >= 22 )); then - PYTHON_VERSION=python3.11 - elif (( UBUNTU_VERSION >= 20 )); then - PYTHON_VERSION=python3.9 - OTHER_PACKAGES+=(gcc-10 g++-10 cpp-10) # Newer version of gcc needed for Verilator - elif (( DEBIAN_VERSION >= 12 )); then - PYTHON_VERSION=python3.11 - elif (( DEBIAN_VERSION >= 11 )); then - PYTHON_VERSION=python3.9 - fi - # Mold not available in older distros for Verilator, will download binary instead - if (( UBUNTU_VERSION != 20 && DEBIAN_VERSION != 11 )); then - VERILATOR_PACKAGES+=(mold) - fi - PACKAGE_MANAGER="DEBIAN_FRONTEND=noninteractive apt-get -y" - UPDATE_COMMAND="sudo $PACKAGE_MANAGER update && sudo $PACKAGE_MANAGER upgrade --with-new-pkgs" - GENERAL_PACKAGES+=("$PYTHON_VERSION" python3-pip "$PYTHON_VERSION"-venv pkg-config g++) - GNU_PACKAGES+=(autotools-dev libmpc-dev libmpfr-dev libgmp-dev build-essential zlib1g-dev libexpat1-dev libglib2.0-dev libslirp-dev) - QEMU_PACKAGES+=(libfdt-dev libpixman-1-dev) - SPIKE_PACKAGES+=(device-tree-compiler libboost-regex-dev libboost-system-dev) - VERILATOR_PACKAGES+=(libunwind-dev libgoogle-perftools-dev perl-doc libfl2 libfl-dev zlib1g) - BUILDROOT_PACKAGES+=(ncurses-bin libncurses-dev gfortran) # gfortran is only needed for compiling spec benchmarks on buildroot linux - VIVADO_PACKAGES+=(libncurses*) # Vivado hangs on the third stage of installation without this -fi + PACKAGE_MANAGER="dnf -y" + UPDATE_COMMAND="sudo $PACKAGE_MANAGER update" + GENERAL_PACKAGES+=(which "$PYTHON_VERSION" "$PYTHON_VERSION"-pip pkgconf-pkg-config gcc-c++ ssmtp) + GNU_PACKAGES+=(libmpc-devel mpfr-devel gmp-devel zlib-devel expat-devel libslirp-devel ninja-build) + QEMU_PACKAGES+=(glib2-devel libfdt-devel pixman-devel) + SPIKE_PACKAGES+=(dtc boost-regex boost-system) + VERILATOR_PACKAGES+=(gperftools mold) + BUILDROOT_PACKAGES+=(ncurses ncurses-base ncurses-libs ncurses-devel gcc-gfortran) # gcc-gfortran is only needed for compiling spec benchmarks on buildroot linux + # Extra packages not availale in rhel8, nice for Verilator + if (( RHEL_VERSION >= 9 )); then + VERILATOR_PACKAGES+=(perl-doc) + fi + # A newer version of gcc is required for qemu + OTHER_PACKAGES+=(gcc-toolset-13) + ;; + ubuntu | debian) + if (( UBUNTU_VERSION >= 24 )); then + PYTHON_VERSION=python3.12 + elif (( UBUNTU_VERSION >= 22 )); then + PYTHON_VERSION=python3.11 + elif (( UBUNTU_VERSION >= 20 )); then + PYTHON_VERSION=python3.9 + OTHER_PACKAGES+=(gcc-10 g++-10 cpp-10) # Newer version of gcc needed for Verilator + elif (( DEBIAN_VERSION >= 12 )); then + PYTHON_VERSION=python3.11 + elif (( DEBIAN_VERSION >= 11 )); then + PYTHON_VERSION=python3.9 + fi + # Mold not available in older distros for Verilator, will download binary instead + if (( UBUNTU_VERSION != 20 && DEBIAN_VERSION != 11 )); then + VERILATOR_PACKAGES+=(mold) + fi + PACKAGE_MANAGER="DEBIAN_FRONTEND=noninteractive apt-get -y" + UPDATE_COMMAND="sudo $PACKAGE_MANAGER update && sudo $PACKAGE_MANAGER upgrade --with-new-pkgs" + GENERAL_PACKAGES+=("$PYTHON_VERSION" python3-pip "$PYTHON_VERSION"-venv pkg-config g++ ssmtp) + GNU_PACKAGES+=(autotools-dev libmpc-dev libmpfr-dev libgmp-dev build-essential ninja-build zlib1g-dev libexpat1-dev libglib2.0-dev libslirp-dev) + QEMU_PACKAGES+=(libfdt-dev libpixman-1-dev) + SPIKE_PACKAGES+=(device-tree-compiler libboost-regex-dev libboost-system-dev) + VERILATOR_PACKAGES+=(libunwind-dev libgoogle-perftools-dev perl-doc libfl2 libfl-dev zlib1g) + BUILDROOT_PACKAGES+=(ncurses-base ncurses-bin libncurses-dev gfortran) # gfortran is only needed for compiling spec benchmarks on buildroot linux + VIVADO_PACKAGES+=(libncurses*) # Vivado hangs on the third stage of installation without this + ;; + suse) + PYTHON_VERSION=python3.12 + PYTHON_VERSION_PACKAGE=python312 + PACKAGE_MANAGER="zypper -n" + UPDATE_COMMAND="sudo $PACKAGE_MANAGER update" + GENERAL_PACKAGES+=("$PYTHON_VERSION_PACKAGE" "$PYTHON_VERSION_PACKAGE"-pip pkg-config) + GNU_PACKAGES+=(mpc-devel mpfr-devel gmp-devel zlib-devel libexpat-devel libslirp-devel ninja) + QEMU_PACKAGES+=(glib2-devel libpixman-1-0-devel) # maybe also need qemu itself? + SPIKE_PACKAGES+=(dtc libboost_regex1_75_0-devel libboost_system1_75_0-devel) + VERILATOR_PACKAGES+=(gperftools perl-doc) + BUILDROOT_PACKAGES+=(ncurses-utils ncurses-devel ncurses5-devel gcc-fortran) # gcc-fortran is only needed for compiling spec benchmarks on buildroot linux + OTHER_PACKAGES+=(gcc14 gcc14-c++ cpp14) # Newer version of gcc needed for many tools. Default is gcc7 + ;; +esac # Check if required packages are installed or install/update them depending on passed flag. if [ "${1}" == "--check" ]; then section_header "Checking Dependencies from Package Manager" - if [ "$FAMILY" == rhel ]; then + if [[ "$FAMILY" == rhel || "$FAMILY" == suse ]]; then for pack in "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}"; do rpm -q "$pack" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first.${ENDC}" && exit 1) done diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 4bfa2c9a3..77895261c 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -191,6 +191,12 @@ fi # Enable newer version of gcc for older distros (required for QEMU/Verilator) if [ "$FAMILY" == rhel ]; then source /opt/rh/gcc-toolset-13/enable +elif [ "$FAMILY" == suse ]; then + mkdir -p "$RISCV"/gcc-14/bin + for f in gcc cpp g++ gcc-ar gcc-nm gcc-ranlib gcov gcov-dump gcov-tool lto-dump; do + ln -vsf /usr/bin/$f-14 "$RISCV"/gcc-14/bin/$f + done + export PATH="$RISCV"/gcc-14/bin:$PATH elif (( UBUNTU_VERSION == 20 )); then mkdir -p "$RISCV"/gcc-10/bin for f in gcc cpp g++ gcc-ar gcc-nm gcc-ranlib gcov gcov-dump gcov-tool lto-dump; do @@ -264,7 +270,7 @@ if (( RHEL_VERSION == 8 )); then fi # Mold needed for Verilator -if (( UBUNTU_VERSION == 20 || DEBIAN_VERSION == 11 )); then +if (( UBUNTU_VERSION == 20 || DEBIAN_VERSION == 11 )) || [ "$FAMILY" == suse ]; then STATUS="mold" if [ ! -e "$RISCV"/bin/mold ]; then section_header "Installing mold" diff --git a/site-setup.sh b/site-setup.sh index 34fe1eb42..8df82503a 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -77,6 +77,8 @@ fi # Use newer gcc version for older distros if [ -e /opt/rh/gcc-toolset-13/enable ]; then source /opt/rh/gcc-toolset-13/enable # Red Hat Family +elif [ -e $RISCV/gcc-14 ]; then + export PATH=$RISCV/gcc-14/bin:$PATH # SUSE Family elif [ -e $RISCV/gcc-10 ]; then export PATH=$RISCV/gcc-10/bin:$PATH # Ubuntu 20.04 LTS fi From 165c4d6ba40dbe847a58971c49637b9911458fd3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 24 Nov 2024 15:57:42 -0800 Subject: [PATCH 088/212] Add suse to installation CI --- .github/workflows/install.yml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index ff0e93181..0c0b398c3 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -73,6 +73,11 @@ jobs: os: ubuntu-latest image: almalinux:9 imageFamily: redhat + # SUSE Installations + - name: opensuse-15.6 + os: ubuntu-latest + image: opensuse/leap:15.6 + imageFamily: suse # User level installation - name: user-install os: ubuntu-latest @@ -107,6 +112,8 @@ jobs: elif [ ${{ matrix.imageFamily }} == "redhat" ]; then dnf install -y sudo git dnf install curl -y --allowerasing || true + elif [ ${{ matrix.imageFamily }} == "suse" ]; then + zypper install -y sudo git fi # Only clone submodules needed for standard tests/regression to save space - uses: actions/checkout@v4 From 034624523397179fc4ce5c85daff0979cfb8e7ce Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Sun, 24 Nov 2024 16:36:59 -0800 Subject: [PATCH 089/212] removed unused and redundant clint base variable --- config/rv32gc/coverage.svh | 1 - config/rv64gc/coverage.svh | 1 - 2 files changed, 2 deletions(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index d3953b916..b05362f8d 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -9,7 +9,6 @@ `define XLEN32 1 // Define relevant addresses -`define CLINT_BASE 64'h02000000 `define ACCESS_FAULT_ADDRESS 32'h0000 // Unprivileged extensions diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 3974d7f96..85abee104 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -9,7 +9,6 @@ `define XLEN64 1 // Define relevant addresses -`define CLINT_BASE 64'h02000000 `define ACCESS_FAULT_ADDRESS 64'h00000000 // Unprivileged extensions From c105c4c720e945570311ca2f804219346cdc5826 Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Sun, 24 Nov 2024 17:04:12 -0800 Subject: [PATCH 090/212] restored clint base for interrupt tests --- config/rv32gc/coverage.svh | 1 + config/rv64gc/coverage.svh | 1 + 2 files changed, 2 insertions(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index b05362f8d..0403b7e4b 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -10,6 +10,7 @@ // Define relevant addresses `define ACCESS_FAULT_ADDRESS 32'h0000 +`define CLINT_BASE 64'h02000000 // Unprivileged extensions `include "RV32I_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 85abee104..e7c574020 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -10,6 +10,7 @@ // Define relevant addresses `define ACCESS_FAULT_ADDRESS 64'h00000000 +`define CLINT_BASE 64'h02000000 // Unprivileged extensions `include "RV64I_coverage.svh" From 7be6311f51807104317d81705603a4f21de2c826 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 25 Nov 2024 08:11:50 -0800 Subject: [PATCH 091/212] Update cvw-arch-verif submodule --- addins/cvw-arch-verif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index 6d658b7b4..812f30af7 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit 6d658b7b42c83fd584008d72964cc75d0876b769 +Subproject commit 812f30af765c0a692c506e42493f494278c00fe0 From 55fb7e07b3dca67557d6131c62eeae87cc8c5163 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 25 Nov 2024 08:12:52 -0800 Subject: [PATCH 092/212] Add cvw-arch-verif to main Makefile --- Makefile | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 323b18b1d..52513a812 100644 --- a/Makefile +++ b/Makefile @@ -6,9 +6,9 @@ MAKEFLAGS += --output-sync --no-print-directory SIM = ${WALLY}/sim -.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage clean +.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage cvw-arch-verif clean -all: riscof testfloat combined_IF_vectors zsbl coverage # benchmarks +all: riscof testfloat combined_IF_vectors zsbl coverage cvw-arch-verif # benchmarks # riscof builds the riscv-arch-test and wally-riscv-arch-test suites riscof: @@ -36,6 +36,10 @@ embench: coverage: $(MAKE) -C tests/coverage +cvw-arch-verif: + $(MAKE) -C ${WALLY}/addins/cvw-arch-verif + clean: $(MAKE) clean -C sim $(MAKE) clean -C ${WALLY}/tests/fp + $(MAKE) clean -C ${WALLY}/addins/cvw-arch-verif From 53fe1c2598ff186c3b413ea0e0343807f4ac9118 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 17 Nov 2024 00:00:40 -0800 Subject: [PATCH 093/212] Add dependabot file --- .github/dependabot.yml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 .github/dependabot.yml diff --git a/.github/dependabot.yml b/.github/dependabot.yml new file mode 100644 index 000000000..a91ebaf1d --- /dev/null +++ b/.github/dependabot.yml @@ -0,0 +1,17 @@ +# To get started with Dependabot version updates, you'll need to specify which +# package ecosystems to update and where the package manifests are located. +# Please see the documentation for all configuration options: +# https://docs.github.com/code-security/dependabot/dependabot-version-updates/configuration-options-for-the-dependabot.yml-file + +version: 2 +updates: + # Update git submodules to latest version + - package-ecosystem: "gitsubmodule" + directory: "/" + schedule: + interval: "weekly" + # Update actions in the GitHub Actions workflow files + - package-ecosystem: "github-actions" + directory: "/" + schedule: + interval: "weekly" From aa72ed1c19d49db60420322857884416ffc6073e Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 25 Nov 2024 16:36:14 +0000 Subject: [PATCH 094/212] Bump addins/verilog-ethernet from `c180b22` to `6f5ea41` Bumps [addins/verilog-ethernet](https://github.com/rosethompson/verilog-ethernet) from `c180b22` to `6f5ea41`. - [Commits](https://github.com/rosethompson/verilog-ethernet/compare/c180b22ed5f4112d0ef35b2c5ac1acc45f9ebb5d...6f5ea41584c49543e63415e37356ebb24b07d89d) --- updated-dependencies: - dependency-name: addins/verilog-ethernet dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- addins/verilog-ethernet | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/verilog-ethernet b/addins/verilog-ethernet index c180b22ed..6f5ea4158 160000 --- a/addins/verilog-ethernet +++ b/addins/verilog-ethernet @@ -1 +1 @@ -Subproject commit c180b22ed5f4112d0ef35b2c5ac1acc45f9ebb5d +Subproject commit 6f5ea41584c49543e63415e37356ebb24b07d89d From 7d80a8992a535710eed2702106ce8359b5a45aa0 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 25 Nov 2024 08:55:46 -0800 Subject: [PATCH 095/212] Remove FreeRTOS --- .gitmodules | 3 --- addins/FreeRTOS-Kernel | 1 - 2 files changed, 4 deletions(-) delete mode 160000 addins/FreeRTOS-Kernel diff --git a/.gitmodules b/.gitmodules index 34a374174..5a1e8d4dc 100644 --- a/.gitmodules +++ b/.gitmodules @@ -8,9 +8,6 @@ [submodule "addins/coremark"] path = addins/coremark url = https://github.com/eembc/coremark -[submodule "addins/FreeRTOS-Kernel"] - path = addins/FreeRTOS-Kernel - url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git [submodule "addins/vivado-boards"] path = addins/vivado-boards url = https://github.com/Digilent/vivado-boards/ diff --git a/addins/FreeRTOS-Kernel b/addins/FreeRTOS-Kernel deleted file mode 160000 index 17a46c252..000000000 --- a/addins/FreeRTOS-Kernel +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 17a46c252f2f237e03a6768c5d15731215322f31 From 015b3f0d680f94a93720abf2434962d6b87c49d7 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 25 Nov 2024 16:59:13 +0000 Subject: [PATCH 096/212] Bump addins/vivado-boards from `e5f0728` to `8ed4f99` Bumps [addins/vivado-boards](https://github.com/Digilent/vivado-boards) from `e5f0728` to `8ed4f99`. - [Commits](https://github.com/Digilent/vivado-boards/compare/e5f0728cd284d10080ae8eb03fc86e7b5eafcb72...8ed4f9981da1d80badb0b1f65e250b2dbf7a564d) --- updated-dependencies: - dependency-name: addins/vivado-boards dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- addins/vivado-boards | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/vivado-boards b/addins/vivado-boards index e5f0728cd..8ed4f9981 160000 --- a/addins/vivado-boards +++ b/addins/vivado-boards @@ -1 +1 @@ -Subproject commit e5f0728cd284d10080ae8eb03fc86e7b5eafcb72 +Subproject commit 8ed4f9981da1d80badb0b1f65e250b2dbf7a564d From 7358c1fe67208bbd3e2284b6ebcc01e1020afd34 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 25 Nov 2024 15:50:29 -0600 Subject: [PATCH 097/212] Fixed sublte bug in the spi_fifo which allows for spurious write to fifo. Fixed fpga zsbl so that is uses read fifo interrupt pending (IP) rather than transmit fifo IP. Resolves issue with stalled load reading the wrong fifo status. --- fpga/zsbl/spi.c | 2 +- fpga/zsbl/spi.h | 2 +- src/uncore/spi_fifo.sv | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/fpga/zsbl/spi.c b/fpga/zsbl/spi.c index 04d609648..4e75086ad 100644 --- a/fpga/zsbl/spi.c +++ b/fpga/zsbl/spi.c @@ -31,7 +31,7 @@ uint8_t spi_txrx(uint8_t byte) { spi_sendbyte(byte); - waittx(); + waitrx(); return spi_readbyte(); } diff --git a/fpga/zsbl/spi.h b/fpga/zsbl/spi.h index f9e88fa6d..5a472142f 100644 --- a/fpga/zsbl/spi.h +++ b/fpga/zsbl/spi.h @@ -106,7 +106,7 @@ static inline void waittx() { } static inline void waitrx() { - while(read_reg(SPI_IP) & 2) {} + while(!(read_reg(SPI_IP) & 2)) {} } static inline uint8_t spi_readbyte() { diff --git a/src/uncore/spi_fifo.sv b/src/uncore/spi_fifo.sv index 1e4910faf..514e9df7b 100644 --- a/src/uncore/spi_fifo.sv +++ b/src/uncore/spi_fifo.sv @@ -26,7 +26,7 @@ module spi_fifo #(parameter M=3, N=8)( // 2^M entries of N bits assign rdata = mem[raddr]; always_ff @(posedge PCLK) - if (winc & ~wfull) mem[waddr] <= wdata; + if (winc & wen & ~wfull) mem[waddr] <= wdata; // write and read are enabled always_ff @(posedge PCLK) From 58628ed37001437f36e238cfefc2913f901ef5f1 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 25 Nov 2024 15:43:11 -0800 Subject: [PATCH 098/212] Remove riscvISACOV submodule --- .gitmodules | 3 --- addins/riscvISACOV | 1 - 2 files changed, 4 deletions(-) delete mode 160000 addins/riscvISACOV diff --git a/.gitmodules b/.gitmodules index 5a1e8d4dc..672ec445f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -26,9 +26,6 @@ path = addins/cvw-arch-verif url = https://github.com/openhwgroup/cvw-arch-verif ignore = dirty -[submodule "addins/riscvISACOV"] - path = addins/riscvISACOV - url = https://github.com/riscv-verification/riscvISACOV.git [submodule "addins/berkeley-softfloat-3"] path = addins/berkeley-softfloat-3 url = https://github.com/ucb-bar/berkeley-softfloat-3.git diff --git a/addins/riscvISACOV b/addins/riscvISACOV deleted file mode 160000 index ac9fa2d38..000000000 --- a/addins/riscvISACOV +++ /dev/null @@ -1 +0,0 @@ -Subproject commit ac9fa2d386c0cb2f44e1e1e83a555d585034dfa3 From 6e1d2efc002457e6a361c2efc16f024cad92fd9b Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 25 Nov 2024 20:29:55 -0800 Subject: [PATCH 099/212] Update wally.do to use new isacov location --- sim/questa/wally.do | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 6f613c404..f42bf4930 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -110,9 +110,8 @@ if {[lcheck lst "--fcov"]} { set FCvlog "+define+INCLUDE_TRACE2COV \ +define+IDV_INCLUDE_TRACE2COV \ +define+COVER_BASE_RV32I \ - +incdir+$env(WALLY)/addins/riscvISACOV/source \ + +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source \ " - set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1" } From 6b792f876038fabc159368555d1c28300a12e932 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 25 Nov 2024 20:33:36 -0800 Subject: [PATCH 100/212] Update cvw-arch-verif to version with isacov --- addins/cvw-arch-verif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index 812f30af7..d6bae481c 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit 812f30af765c0a692c506e42493f494278c00fe0 +Subproject commit d6bae481c784461a2d2be14325041ea284319098 From 0c338c590ad0bc4b735859a93bd6f26b3d831656 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 24 Nov 2024 19:35:04 -0800 Subject: [PATCH 101/212] Buildroot fails with gcc14 --- bin/wally-package-install.sh | 2 +- bin/wally-tool-chain-install.sh | 6 +++--- site-setup.sh | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index 836a5625f..de8c0ebc1 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -107,7 +107,7 @@ case "$FAMILY" in SPIKE_PACKAGES+=(dtc libboost_regex1_75_0-devel libboost_system1_75_0-devel) VERILATOR_PACKAGES+=(gperftools perl-doc) BUILDROOT_PACKAGES+=(ncurses-utils ncurses-devel ncurses5-devel gcc-fortran) # gcc-fortran is only needed for compiling spec benchmarks on buildroot linux - OTHER_PACKAGES+=(gcc14 gcc14-c++ cpp14) # Newer version of gcc needed for many tools. Default is gcc7 + OTHER_PACKAGES+=(gcc13 gcc13-c++ cpp13) # Newer version of gcc needed for many tools. Default is gcc7 ;; esac diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 77895261c..35578d008 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -192,11 +192,11 @@ fi if [ "$FAMILY" == rhel ]; then source /opt/rh/gcc-toolset-13/enable elif [ "$FAMILY" == suse ]; then - mkdir -p "$RISCV"/gcc-14/bin + mkdir -p "$RISCV"/gcc-13/bin for f in gcc cpp g++ gcc-ar gcc-nm gcc-ranlib gcov gcov-dump gcov-tool lto-dump; do - ln -vsf /usr/bin/$f-14 "$RISCV"/gcc-14/bin/$f + ln -vsf /usr/bin/$f-13 "$RISCV"/gcc-13/bin/$f done - export PATH="$RISCV"/gcc-14/bin:$PATH + export PATH="$RISCV"/gcc-13/bin:$PATH elif (( UBUNTU_VERSION == 20 )); then mkdir -p "$RISCV"/gcc-10/bin for f in gcc cpp g++ gcc-ar gcc-nm gcc-ranlib gcov gcov-dump gcov-tool lto-dump; do diff --git a/site-setup.sh b/site-setup.sh index 8df82503a..4699ff348 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -77,8 +77,8 @@ fi # Use newer gcc version for older distros if [ -e /opt/rh/gcc-toolset-13/enable ]; then source /opt/rh/gcc-toolset-13/enable # Red Hat Family -elif [ -e $RISCV/gcc-14 ]; then - export PATH=$RISCV/gcc-14/bin:$PATH # SUSE Family +elif [ -e $RISCV/gcc-13 ]; then + export PATH=$RISCV/gcc-13/bin:$PATH # SUSE Family elif [ -e $RISCV/gcc-10 ]; then export PATH=$RISCV/gcc-10/bin:$PATH # Ubuntu 20.04 LTS fi From 23364617cd2c356d824ebd1205c5fec3f197a979 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 25 Nov 2024 21:17:04 -0800 Subject: [PATCH 102/212] Add SUSE to readme --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index e26454b1a..70d74eb52 100644 --- a/README.md +++ b/README.md @@ -71,7 +71,7 @@ Then fork and clone the repo, source setup, make the tests and run regression > This section describes the open source toolchain installation. ### Compatibility -The current version of the toolchain has been tested on Ubuntu (versions 20.04 LTS, 22.04 LTS, and 24.04 LTS), Debian (versions 11 and 12), and Red Hat/Rocky/AlmaLinux (versions 8 and 9). Only the latest minor release of each major version is tested. +The current version of the toolchain has been tested on Ubuntu (versions 20.04 LTS, 22.04 LTS, and 24.04 LTS), Debian (versions 11 and 12), Red Hat/Rocky/AlmaLinux (versions 8 and 9), and OpenSUSE (version 15.6). Only the latest minor release of each major version is tested. > [!WARNING] > - Ubuntu 22.04LTS is incompatible with Synopsys Design Compiler. From daddbed8e67e0eaafbf60ca142886fa190f7ad21 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 26 Nov 2024 08:15:36 -0800 Subject: [PATCH 103/212] Revert "Bump addins/verilog-ethernet from `c180b22` to `6f5ea41`" --- addins/verilog-ethernet | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/verilog-ethernet b/addins/verilog-ethernet index 6f5ea4158..c180b22ed 160000 --- a/addins/verilog-ethernet +++ b/addins/verilog-ethernet @@ -1 +1 @@ -Subproject commit 6f5ea41584c49543e63415e37356ebb24b07d89d +Subproject commit c180b22ed5f4112d0ef35b2c5ac1acc45f9ebb5d From 05189d102ac5de8fa778ecd2836b1c00c8035e7c Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 26 Nov 2024 22:09:11 -0800 Subject: [PATCH 104/212] Modifying tracer toward being able to run non-gc configurations in lockstep --- testbench/common/wallyTracer.sv | 355 +++++++++++++++++--------------- testbench/testbench.sv | 14 +- 2 files changed, 195 insertions(+), 174 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index a32417737..51f0d302a 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -95,11 +95,19 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign FlushW = testbench.dut.core.FlushW; assign TrapM = testbench.dut.core.TrapM; assign HaltM = testbench.DCacheFlushStart; - assign PrivilegeModeW = testbench.dut.core.priv.priv.privmode.PrivilegeModeW; - assign STATUS_SXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL; - assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL; - assign wfiM = testbench.dut.core.priv.priv.wfiM; - assign InterruptM = testbench.dut.core.priv.priv.InterruptM; + if (P.ZICSR_SUPPORTED) begin + assign PrivilegeModeW = testbench.dut.core.priv.priv.privmode.PrivilegeModeW; + assign STATUS_SXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL; + assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL; + assign wfiM = testbench.dut.core.priv.priv.wfiM; + assign InterruptM = testbench.dut.core.priv.priv.InterruptM; + end else begin + assign PrivilegeModeW = 2'b11; + assign STATUS_SXL = 0; + assign STATUS_UXL = 0; + assign wfiM = 0; + assign InterruptM = 0; + end //For VM Verification assign VAdrIM = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr; @@ -116,181 +124,185 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic valid; - always_comb begin - // Since we are detected the CSR change by comparing the old value we need to - // ensure the CSR is detected when the pipeline's Writeback stage is not - // stalled. If it is stalled we want CSRArray to hold the old value. - if(valid) begin - // PMPCFG CSRs (space is 0-15 3a0 - 3af) - localparam inc = P.XLEN == 32 ? 4 : 8; - int i, i4, i8, csrid; - logic [P.XLEN-1:0] pmp; + if (P.ZICSR_SUPPORTED) begin + always_comb begin + // Since we are detected the CSR change by comparing the old value we need to + // ensure the CSR is detected when the pipeline's Writeback stage is not + // stalled. If it is stalled we want CSRArray to hold the old value. + if(valid) begin + // PMPCFG CSRs (space is 0-15 3a0 - 3af) + localparam inc = P.XLEN == 32 ? 4 : 8; + int i, i4, i8, csrid; + logic [P.XLEN-1:0] pmp; - for (i=0; i Date: Tue, 26 Nov 2024 22:10:18 -0800 Subject: [PATCH 105/212] Adding ExceptionsInstr coverage --- config/rv32gc/coverage.svh | 3 ++- config/rv64gc/coverage.svh | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 0403b7e4b..ee996e11c 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -44,4 +44,5 @@ `include "EndianU_coverage.svh" `include "EndianM_coverage.svh" `include "EndianS_coverage.svh" -`include "ExceptionsM_coverage.svh" \ No newline at end of file +`include "ExceptionsM_coverage.svh" +`include "ExceptionsInstr_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index e7c574020..a2d691e4e 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -44,6 +44,7 @@ `include "EndianM_coverage.svh" `include "EndianS_coverage.svh" `include "ExceptionsM_coverage.svh" +`include "ExceptionsInstr_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" From 8a910aabf4a0cecea1f783a1458672fcc2eb5096 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 27 Nov 2024 05:42:39 -0800 Subject: [PATCH 106/212] Documentation and comment fixes --- README.md | 5 +++-- bin/wally-distro-check.sh | 2 +- .../rv32i_m/privilege/src/WALLY-csr-permission-s-01.S | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 2a23f66d2..0f560f63a 100644 --- a/README.md +++ b/README.md @@ -71,7 +71,8 @@ Then fork and clone the repo, source setup, make the tests and run regression > This section describes the open source toolchain installation. ### Compatibility -The current version of the toolchain has been tested on Ubuntu (versions 20.04 LTS, 22.04 LTS, and 24.04 LTS), Debian (versions 11 and 12), and Red Hat/Rocky/AlmaLinux (versions 8 and 9). Only the latest minor release of each major version is tested. +The current version of the toolchain has been tested on Ubuntu (versions 20.04 LTS, 22.04 LTS, and 24.04 LTS), Debian (versions 11 and 12), Red Hat/Rocky/AlmaLinux (versions 8 and 9), +and SUSE version 15.6. Only the latest minor release of each major version is tested. > [!WARNING] > - Ubuntu 22.04LTS is incompatible with Synopsys Design Compiler. @@ -145,7 +146,7 @@ Running code or functional coverage simulations or lock-step presently require c Note: Some EDA tools utilize `LM_LICENSE_FILE` for their environmental variable to point to their license server. Some operating systems may also utilize `MGLS_LICENSE_FILE` instead, therefore, it is important to read the user manual on the preferred environmental variable required to point to a user’s license file. Although there are different mechanisms to allow licenses to work, many companies commonly utilize the FlexLM (i.e., Flex-enabled) license server manager that runs off a node locked license. -Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors. Red Hat Enterprise Linux (and its free Rocky clone) typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration. +Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors. Red Hat Enterprise Linux (and its free Rocky clone) and SUSE Linux products typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration. ### Siemens Questa diff --git a/bin/wally-distro-check.sh b/bin/wally-distro-check.sh index db0699fd2..f08f5e2e2 100755 --- a/bin/wally-distro-check.sh +++ b/bin/wally-distro-check.sh @@ -96,7 +96,7 @@ elif [[ "$ID" == debian || "$ID_LIKE" == *debian* ]]; then exit 1 fi else - printf "${FAIL_COLOR}%s%s%s\n${ENDC}" "The Wally installation script is currently only compatible with Ubuntu, Debian, and Red Hat family " \ + printf "${FAIL_COLOR}%s%s%s\n${ENDC}" "The Wally installation script is currently only compatible with Ubuntu, Debian, SUSE, and Red Hat family " \ "(RHEL, Rocky Linux, or AlmaLinux) distros. Your detected distro is $PRETTY_NAME. You may try manually running the " \ "commands in this script, but it is likely that some will need to be altered." exit 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S index af7f6252c..a222a37a5 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S @@ -38,7 +38,7 @@ GOTO_S_MODE 0x0, 0x0 # should result in an illegal instruction for the write and read, respectively # High-bit versions storing the upper 32 bits of some CSRs for RV32 -WRITE_READ_CSR mstatush 0x111 # not supported in rv32 +WRITE_READ_CSR mstatush 0x111 WRITE_READ_CSR menvcfgh 0x111 WRITE_READ_CSR mseccfgh 0x111 WRITE_READ_CSR pmpcfg1 0x111 From 2ad039aadc6f1ab8d0fa0e1a5a1d4bea1074ff06 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 27 Nov 2024 06:21:37 -0800 Subject: [PATCH 107/212] Reversed adding exceptionsInstr; using exceptionsM instead --- config/rv32gc/coverage.svh | 1 - config/rv64gc/coverage.svh | 1 - 2 files changed, 2 deletions(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index ee996e11c..115dbd5f1 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -45,4 +45,3 @@ `include "EndianM_coverage.svh" `include "EndianS_coverage.svh" `include "ExceptionsM_coverage.svh" -`include "ExceptionsInstr_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index a2d691e4e..e7c574020 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -44,7 +44,6 @@ `include "EndianM_coverage.svh" `include "EndianS_coverage.svh" `include "ExceptionsM_coverage.svh" -`include "ExceptionsInstr_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" From 37c68798056f652a99dcea69e1b8f1e851cc3404 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 27 Nov 2024 15:12:11 -0800 Subject: [PATCH 108/212] Fixed decoder bug that doesn't throw illegal instruction exception for RV32 immediate shifts by more than 31 --- src/ieu/bmu/bmuctrl.sv | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index d4a8afe23..e55c24faa 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -152,12 +152,13 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( endcase end if (P.ZBB_SUPPORTED | P.ZBS_SUPPORTED) // rv32i/64i shift instructions need BMU ALUSelect when BMU shifter is used - casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sra, srl, sll - 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // srai, srli, slli - 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sraw, srlw, sllw - 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // sraiw, srliw, slliw - endcase + if (P.XLEN == 64 | !Funct7D[0]) // rv32i shifts cannot shift by more than 31 + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sra, srl, sll + 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // srai, srli, slli + 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sraw, srlw, sllw + 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // sraiw, srliw, slliw + endcase if (P.ZBKB_SUPPORTED) begin // ZBKB Bitmanip casez({OpD,Funct7D, Funct3D}) From 9116ffa45d52e627a656c4b90f145ad7a18b4e62 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 28 Nov 2024 13:36:31 -0800 Subject: [PATCH 109/212] Fixed Issue #1147 that w-type shifts do not throw illegal instruction trap in RV32GC --- src/ieu/bmu/bmuctrl.sv | 15 ++++++++++----- src/ieu/controller.sv | 1 - 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index e55c24faa..f9c524ec9 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -152,12 +152,17 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( endcase end if (P.ZBB_SUPPORTED | P.ZBS_SUPPORTED) // rv32i/64i shift instructions need BMU ALUSelect when BMU shifter is used - if (P.XLEN == 64 | !Funct7D[0]) // rv32i shifts cannot shift by more than 31 + if (P.XLEN == 64 | !Funct7D[0]) casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sra, srl, sll - 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // srai, srli, slli - 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sraw, srlw, sllw - 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // sraiw, srliw, slliw + // rv32i shifts cannot shift by more than 31. w-type shifts only supported in RV64 + 17'b0110011_000000?_001: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sll + 17'b0110011_0?0000?_101: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sra, srl + 17'b0010011_000000?_001: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // slli + 17'b0010011_0?0000?_101: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // srai, srli + 17'b0111011_0000000_001: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sllw + 17'b0111011_0?00000_101: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sraw, srlw + 17'b0011011_0000000_001: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // slliw + 17'b0011011_0?00000_101: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // sraiw, srliw endcase if (P.ZBKB_SUPPORTED) begin // ZBKB Bitmanip diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 19f96c98d..4f1f778c1 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -300,7 +300,6 @@ module controller import cvw::*; #(parameter cvw_t P) ( // Squash control signals if coming from an illegal compressed instruction // On RV32E, can't write to upper 16 registers. Checking reads to upper 16 is more costly so disregard them. assign IllegalERegAdrD = P.E_SUPPORTED & P.ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; - //assign IllegalBaseInstrD = 1'b0; assign {BaseRegWriteD, PreImmSrcD, ALUSrcAD, BaseALUSrcBD, MemRWD, ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD, PrivilegedD, FenceXD, MDUD, AtomicD, CMOD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD; From f1072e46e118d76b8fc40f577cd7b3cd9f994ed9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 28 Nov 2024 14:40:09 -0800 Subject: [PATCH 110/212] fcvt to/fron long only allowed in RV64 --- src/fpu/fctrl.sv | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index d04fc45fa..cd2f2d5d7 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -196,54 +196,54 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( 7'b1101000: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.s.w w->s 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.s.wu wu->s - 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.s.l l->s - 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.s.lu lu->s + 5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.s.l l->s + 5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.s.lu lu->s endcase 7'b1100000: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.s s->w 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.s s->wu - 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.s s->l - 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.s s->lu + 5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.s s->l + 5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.s s->lu endcase 7'b1101001: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.d.w w->d 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.d.wu wu->d - 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.d.l l->d - 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.d.lu lu->d + 5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.d.l l->d + 5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.d.lu lu->d endcase 7'b1100001: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.d d->w 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.d d->wu - 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.d d->l - 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.d d->lu + 5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.d d->l + 5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.d d->lu 5'b01000: if (P.ZFA_SUPPORTED & P.D_SUPPORTED & Funct3D == 3'b001) ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_1_0; // fcvtmod.w.d (Zfa) endcase 7'b1101010: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.h.w w->h 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.h.wu wu->h - 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.h.l l->h - 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.h.lu lu->h + 5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.h.l l->h + 5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.h.lu lu->h endcase 7'b1100010: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.h h->w 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.h h->wu - 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.h h->l - 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.h h->lu + 5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.h h->l + 5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.h h->lu endcase // Not covered in testing because rv64gc does not support quad precision // coverage off 7'b1101011: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.q.w w->q 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.q.wu wu->q - 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.q.l l->q - 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.q.lu lu->q + 5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.q.l l->q + 5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.q.lu lu->q endcase 7'b1100011: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.q q->w 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.q q->wu - 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.q q->l - 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.q q->lu + 5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.q q->l + 5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.q q->lu endcase // coverage off // Not covered in testing because rv64gc is not RV64Q or RV32D From 3f6611dd3a7503e0757112667a0ddd60cc73c4dd Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 28 Nov 2024 14:47:58 -0800 Subject: [PATCH 111/212] Fixed fmv.d.x / fmv.x.d only on RV64 --- src/fpu/fctrl.sv | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index cd2f2d5d7..2b8dbc411 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -153,18 +153,20 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( endcase 7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000) ControlsD = `FCTRLW'b0_1_10_00_000_0_0_0_0_0; // fclass - else if (Funct3D == 3'b000 & Rs2D == 5'b00000) - ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_0_0; // fmv.x.w/d/h/q fp to int register - else if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct7D[1:0] == 2'b01 & Funct3D == 3'b000 & Rs2D == 5'b00001) - ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.d (Zfa) + else if (Funct3D == 3'b000 & Rs2D == 5'b00000) begin + if (Fmt[1:0] == 2'b00 | Fmt[1:0] == 2'b10 | (P.XLEN == 64 & Fmt[1:0] == 2'b01)) + ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_0_0; // fmv.x.w/d/h fp to int register (double only in RV64) + end else if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct7D[1:0] == 2'b01 & Funct3D == 3'b000 & Rs2D == 5'b00001) + ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.d (Zfa) // Q not supported in RV64GC // coverage off else if (P.ZFA_SUPPORTED & P.XLEN == 64 & P.Q_SUPPORTED & Funct7D[1:0] == 2'b11 & Funct3D == 3'b000 & Rs2D == 5'b00001) - ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.q (Zfa) + ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.q (Zfa) // coverage on - 7'b11110??: if (Funct3D == 3'b000 & Rs2D == 5'b00000) - ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0_0_0; // fmv.w/d/h/q.x int to fp reg - else if (P.ZFA_SUPPORTED & Funct3D == 3'b000 & Rs2D == 5'b00001) + 7'b11110??: if (Funct3D == 3'b000 & Rs2D == 5'b00000) begin + if (Fmt[1:0] == 2'b00 | Fmt[1:0] == 2'b10 | (P.XLEN == 64 & Fmt[1:0] == 2'b01)) + ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0_0_0; // fmv.w/d/h.x int to fp reg (double only in RV64) + end else if (P.ZFA_SUPPORTED & Funct3D == 3'b000 & Rs2D == 5'b00001) ControlsD = `FCTRLW'b1_0_00_00_111_0_0_0_1_0; // fli (Zfa) 7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00) ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0_0_0; // fcvt.s.(d/q/h) From 722dc9bfdaa446470879c8172a292a65a87364e2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 28 Nov 2024 16:34:43 -0800 Subject: [PATCH 112/212] Throw illegal instruction for RV64 W-type shifts with amounts > 31 --- src/ieu/controller.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 4f1f778c1..75dbf2b6a 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -181,8 +181,8 @@ module controller import cvw::*; #(parameter cvw_t P) ( assign Funct7ZeroD = (Funct7D == 7'b0000000); // most R-type instructions assign Funct7b5D = (Funct7D == 7'b0100000); // srai, sub assign FunctCZeroD = (Funct3D == 3'b101 | Funct3D == 3'b111) & (Funct7D == 7'b0000111) & P.ZICOND_SUPPORTED; // czero.eqz or czero.nez - assign Funct7ShiftZeroD = (P.XLEN==64) ? (Funct7D[6:1] == 6'b000000) : Funct7ZeroD; - assign Funct7Shiftb5D = (P.XLEN==64) ? (Funct7D[6:1] == 6'b010000) : Funct7b5D; + assign Funct7ShiftZeroD = (P.XLEN==64 & ~OpD[3]) ? (Funct7D[6:1] == 6'b000000) : Funct7ZeroD; // 64-bit logical shifts allowed on XLEN=64, non-W + assign Funct7Shiftb5D = (P.XLEN==64 & ~OpD[3]) ? (Funct7D[6:1] == 6'b010000) : Funct7b5D; // 64-bit arithmetic shifts allowed on XLEN=64, non-W assign IShiftD = (Funct3D == 3'b001 & Funct7ShiftZeroD) | (Funct3D == 3'b101 & (Funct7ShiftZeroD | Funct7Shiftb5D)); // slli, srli, srai, or w forms assign INoShiftD = ((Funct3D != 3'b001) & (Funct3D != 3'b101)); assign IFunctD = IShiftD | INoShiftD; From cf47dd7e6bf7b1d60dc5d8297f3622181c47abac Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 29 Nov 2024 05:58:14 -0800 Subject: [PATCH 113/212] Fixed bmu shift decode logic: bad funct7 for variable shifts, commented better, removed unnecessary guard --- src/ieu/bmu/bmuctrl.sv | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index f9c524ec9..a551179e9 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -152,18 +152,19 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( endcase end if (P.ZBB_SUPPORTED | P.ZBS_SUPPORTED) // rv32i/64i shift instructions need BMU ALUSelect when BMU shifter is used - if (P.XLEN == 64 | !Funct7D[0]) - casez({OpD, Funct7D, Funct3D}) - // rv32i shifts cannot shift by more than 31. w-type shifts only supported in RV64 - 17'b0110011_000000?_001: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sll - 17'b0110011_0?0000?_101: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sra, srl - 17'b0010011_000000?_001: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // slli - 17'b0010011_0?0000?_101: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // srai, srli - 17'b0111011_0000000_001: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sllw - 17'b0111011_0?00000_101: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sraw, srlw - 17'b0011011_0000000_001: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // slliw - 17'b0011011_0?00000_101: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // sraiw, srliw - endcase + casez({OpD, Funct7D, Funct3D}) + // variable shifts don't encode shift amount in funct7 + 17'b0110011_0000000_001: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sll + 17'b0110011_0?00000_101: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sra, srl + // Immediate Shifts by more than 32 (Funct7[0]) are only supported in RV64 + 17'b0010011_000000?_001: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // slli + 17'b0010011_0?0000?_101: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // srai, srli + // w-type shifts only supported in RV64 and must have Funct7[0] = 0 because the shift amount is < 32 + 17'b0111011_0000000_001: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sllw + 17'b0111011_0?00000_101: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sraw, srlw + 17'b0011011_0000000_001: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // slliw + 17'b0011011_0?00000_101: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // sraiw, srliw + endcase if (P.ZBKB_SUPPORTED) begin // ZBKB Bitmanip casez({OpD,Funct7D, Funct3D}) From 58bfc27c63135011f2b25a3767ce625b18f853fb Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 29 Nov 2024 11:20:12 -0800 Subject: [PATCH 114/212] Fixed decoder for illegal 0b1e0c33 issue #1152 --- src/ieu/bmu/bmuctrl.sv | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index a551179e9..fe781e78b 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -119,13 +119,11 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( if (P.ZBC_SUPPORTED) casez({OpD, Funct7D, Funct3D}) 17'b0110011_0000101_010: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_0_1_0_0_0_0_0; // clmulr - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0; // clmul/clmulh + 17'b0110011_0000101_0?1: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0; // clmul/clmulh endcase if (P.ZBKC_SUPPORTED) begin casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0; // clmul/clmulh - // 17'b0110011_0000101_001: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0; // clmul - // 17'b0110011_0000101_011: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_0_1_0_0_0_0_0; // clmulh + 17'b0110011_0000101_0?1: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0; // clmul/clmulh endcase end From 155d1d511b56632c21e3b22fd849b8cd34aa2467 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 29 Nov 2024 11:39:24 -0800 Subject: [PATCH 115/212] Fixed funct7 code for sinval.vma (issue #1154) --- src/privileged/privdec.sv | 2 +- testbench/common/instrNameDecTB.sv | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv index 6321413d4..99380e63f 100644 --- a/src/privileged/privdec.sv +++ b/src/privileged/privdec.sv @@ -59,7 +59,7 @@ module privdec import cvw::*; #(parameter cvw_t P) ( // svinval instructions // any svinval instruction is treated as sfence.vma on Wally - assign sinvalvmaM = (InstrM[31:25] == 7'b0001001); + assign sinvalvmaM = (InstrM[31:25] == 7'b0001011); assign sfencewinvalM = (InstrM[31:20] == 12'b000110000000) & rs1zeroM; assign sfenceinvalirM = (InstrM[31:20] == 12'b000110000001) & rs1zeroM; assign invalM = P.SVINVAL_SUPPORTED & (sinvalvmaM | sfencewinvalM | sfenceinvalirM); diff --git a/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv index 80f6ed607..ae970513f 100644 --- a/testbench/common/instrNameDecTB.sv +++ b/testbench/common/instrNameDecTB.sv @@ -219,6 +219,10 @@ module instrNameDecTB( else if (imm == 258) name = "SRET"; else if (imm == 770) name = "MRET"; else if (funct7 == 9) name = "SFENCE.VMA"; + else if (funct7 == 11) name = "SINVAL.VMA"; + else if (funct7 == 12 & rs2 == 0) name = "SFENCE.W.INVAL"; + else if (funct7 == 12 & rs2 == 1) name = "SFENCE.INVAL.IR"; + else if (imm == 259) name = "WFI"; else if (imm == 261) name = "WFI"; else name = "ILLEGAL"; 10'b1110011_001: name = "CSRRW"; From ec3143f01471840134064e8b20c20a8e53a33fe5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 29 Nov 2024 12:03:14 -0800 Subject: [PATCH 116/212] Updated warning in ramxdetector --- testbench/common/ramxdetector.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/common/ramxdetector.sv b/testbench/common/ramxdetector.sv index c600cff8c..fac34fb43 100644 --- a/testbench/common/ramxdetector.sv +++ b/testbench/common/ramxdetector.sv @@ -39,7 +39,7 @@ module ramxdetector #(parameter XLEN, LLEN) ( /* verilator lint_off WIDTHXZEXPAND */ if (MemReadM & ~LSULoadAccessFaultM & (ReadDataM === 'bx)) begin /* verilator lint_on WIDTHXZEXPAND */ - $display("WARNING: Attempting to read from unitialized RAM. Processor may go haywire if it uses x value. But this is normal in WALLY-mmu tests."); + $display("WARNING: Attempting to read from unitialized RAM. Processor may go haywire if it uses x value. But this is normal in WALLY-mmu and ExceptionInstr tests."); $display(" PCM = %x InstrM = %x (%s), IEUAdrM = %x", PCM, InstrM, InstrMName, IEUAdrM); //$stop; end From 9d3e82d3ec17bfc0c61d4658759dca821531082e Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 29 Nov 2024 12:05:00 -0800 Subject: [PATCH 117/212] Updated imperas.ic files so rv32 follows rv64 --- config/rv32gc/imperas.ic | 16 +++++++++++----- config/rv64gc/imperas.ic | 4 +--- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic index 2ba3c1280..0c3f2e2ea 100644 --- a/config/rv32gc/imperas.ic +++ b/config/rv32gc/imperas.ic @@ -9,7 +9,7 @@ #--showcommands # Core settings ---variant RV32GC # for RV32GC +--variant RV32GCK # for RV32GC --override cpu/priv_version=1.12 --override cpu/user_version=20191213 # arch @@ -59,7 +59,7 @@ #--override cpu/instret_undefined=T #--override cpu/hpmcounter_undefined=T -## context registers not implemented +# context registers not implemented #--override cpu/scontext_undefined=True #--override cpu/mcontext_undefined=True @@ -69,9 +69,14 @@ #--override cpu/Zicfilp=F --override cpu/trigger_num=0 # disable CSRs 7a0-7a8 ---override no_pseudo_inst=T # For code coverage, don't produce pseudoinstructions +# For code coverage, don't produce pseudoinstructions +--override no_pseudo_inst=T ---override show_c_prefix=T # Show "c." with compressed instructions +# Show "c." with compressed instructions +--override show_c_prefix=T + +# nonratified mnoise register not implemented +--override cpu/mnoise_undefined=T # mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag #--override cpu/ecode_mask=0x8000000F # for RV32 @@ -80,7 +85,8 @@ # Debug mode not yet supported --override cpu/debug_mode=none - +# Zkr entropy source and seed register not supported. +--override cpu/Zkr=F --override cpu/reset_address=0x80000000 diff --git a/config/rv64gc/imperas.ic b/config/rv64gc/imperas.ic index 9ba14f2f0..19a7515a5 100644 --- a/config/rv64gc/imperas.ic +++ b/config/rv64gc/imperas.ic @@ -73,7 +73,7 @@ # Show "c." with compressed instructions --override show_c_prefix=T -# nonratified mnosie register not implemented +# nonratified mnoise register not implemented --override cpu/mnoise_undefined=T # mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag @@ -86,8 +86,6 @@ # Zkr entropy source and seed register not supported. --override cpu/Zkr=F - - --override cpu/reset_address=0x80000000 --override cpu/unaligned=T # Zicclsm (should be true) From 11272984bd42afdb8796e92063f06628d568db15 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 29 Nov 2024 14:49:48 -0800 Subject: [PATCH 118/212] Added ExceptionsZc illegal instruction coverage --- config/rv32gc/coverage.svh | 1 + config/rv64gc/coverage.svh | 1 + 2 files changed, 2 insertions(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 115dbd5f1..90593e0f5 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -45,3 +45,4 @@ `include "EndianM_coverage.svh" `include "EndianS_coverage.svh" `include "ExceptionsM_coverage.svh" +`include "ExceptionsZc_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index e7c574020..6aba1ac9a 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -44,6 +44,7 @@ `include "EndianM_coverage.svh" `include "EndianS_coverage.svh" `include "ExceptionsM_coverage.svh" +`include "ExceptionsZc_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" From b27447f552f45fa4e451aed2bfaca8ef549c40f7 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 29 Nov 2024 15:41:36 -0800 Subject: [PATCH 119/212] Change addLockstepTestsByDir to addTestsByDir --- bin/regression-wally | 52 +++++++++++++++++++++++++++++--------------- 1 file changed, 34 insertions(+), 18 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index f53940d89..58e87b6a2 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -291,18 +291,35 @@ def addTests(tests, sim): configs.append(tc) -def addLockstepTestsByDir(dir, config, sim, fcovMode): - sim_logdir = WALLY+ "/sim/" + sim + "/logs/" - if (coverStr != ""): # use --fcov in place of --lockstep - cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config - else: - cmdPrefix="wsim --lockstep --sim " + sim + " " + config - if (os.path.isdir(dir)): +def addTestsByDir(dir, config, sim, lockstepMode=0): + if os.path.isdir(dir): + sim_logdir = WALLY+ "/sim/" + sim + "/logs/" + if coverStr == "--fcov": # use --fcov in place of --lockstep + cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config + gs="Mismatches : 0" + if ("cvw-arch-verif/tests" in dir and not "priv" in dir): + fileEnd = "ALL.elf" + else: + fileEnd = ".elf" + elif coverStr == "--ccov": + cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config + gs="Single Elf file tests are not signatured verified." + if ("cvw-arch-verif/tests" in dir and not "priv" in dir): + fileEnd = "ALL.elf" + else: + fileEnd = ".elf" + elif lockstepMode: + cmdPrefix="wsim --lockstep --sim " + sim + " " + config + gs="Mismatches : 0" + fileEnd = ".elf" + else: + cmdPrefix="wsim --sim " + sim + " " + config + gs="Single Elf file tests are not signatured verified." + fileEnd = ".elf" for dirpath, dirnames, filenames in os.walk(os.path.abspath(dir)): for file in filenames: # fcov lockstep only runs on WALLY-COV-ALL.elf files; other lockstep runs on all files - if ((file.endswith(".elf") and (fcovMode == 0 or "tests/priv" in dir)) or - (file.endswith("ALL.elf") and fcovMode == 1)): + if file.endswith(fileEnd): fullfile = os.path.join(dirpath, file) fields = fullfile.rsplit('/', 3) if (fields[2] == "ref"): @@ -318,7 +335,7 @@ def addLockstepTestsByDir(dir, config, sim, fcovMode): name=file, variant=config, cmd=cmdPrefix + " " + fullfile + " > " + sim_log, - grepstr="Mismatches : 0", + grepstr=gs, grepfile = sim_log) configs.append(tc) else: @@ -421,11 +438,10 @@ if (args.ccov): # only run RV64GC tests on Questa in code coverage mode if (args.fp): addTests(tests64gc_fp, coveragesim) elif (args.fcov): # run tests in lockstep in functional coverage mode - addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1) - addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1) - addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv32/", "rv32gc", coveragesim, 1) - addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim, 1) - #addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0) + addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim) + addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim) + addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv32/", "rv32gc", coveragesim) + addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim) else: for sim in sims: @@ -437,9 +453,9 @@ else: # run derivative configurations and lockstep tests in nightly regression if (args.nightly): - addLockstepTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, 0) - addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, 0) - addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, 0) + addTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, 1) + addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, 1) + addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, 1) addTests(derivconfigtests, defaultsim) # addTests(bpredtests, defaultsim) # This is currently broken in regression due to something related to the new wsim script. From 716656b71b275909791182c6201f31b86f5227fd Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 29 Nov 2024 15:42:23 -0800 Subject: [PATCH 120/212] Code cleanup --- bin/regression-wally | 33 ++++++++++++++++----------------- bin/wsim | 4 ++-- 2 files changed, 18 insertions(+), 19 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 58e87b6a2..51827bb76 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -34,7 +34,7 @@ tests = [ "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "arch32zfad", "wally32a_lrsc", "wally32priv", "wally32periph", "arch32zcb", "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], - ["rv64i", ["arch64i"]] + ["rv64i", ["arch64i"]] ] # Separate test for short buildroot run through OpenSBI UART output @@ -265,8 +265,8 @@ class bcolors: def addTests(tests, sim): sim_logdir = WALLY+ "/sim/" + sim + "/logs/" for test in tests: - config = test[0]; - suites = test[1]; + config = test[0] + suites = test[1] if (len(test) >= 3): args = " --args " + " ".join(test[2]) else: @@ -401,9 +401,8 @@ parser.add_argument("--dryrun", help="Print commands invoked to console without args = parser.parse_args() if (args.nightly): - nightMode = "--nightly"; + nightMode = "--nightly" sims = ["questa", "verilator", "vcs"] # exercise all simulators; can omit a sim if no license is available -# sims = ["questa", "verilator"] # exercise all simulators; can omit a sim if no license is available else: nightMode = "" sims = [defaultsim] @@ -413,7 +412,7 @@ if (args.ccov): # only run RV64GC tests in coverage mode elif (args.fcov): # only run RV64GC tests in lockstep in coverage mode coverStr = '--fcov' else: - coverStr = '' + coverStr = '' # Run Lint @@ -556,17 +555,17 @@ def main(): else: ImperasDVLicenseCount = 10000 # effectively no license limit for non-lockstep tests with Pool(processes=min(len(configs),multiprocessing.cpu_count(), ImperasDVLicenseCount)) as pool: - num_fail = 0 - results = {} - for config in configs: - results[config] = pool.apply_async(run_test_case,(config, args.dryrun)) - for (config,result) in results.items(): - try: - num_fail+=result.get(timeout=TIMEOUT_DUR) - except TimeoutError: - pool.terminate() - num_fail+=1 - print(f"{bcolors.FAIL}%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.cmd, TIMEOUT_DUR)) + num_fail = 0 + results = {} + for config in configs: + results[config] = pool.apply_async(run_test_case,(config, args.dryrun)) + for (config,result) in results.items(): + try: + num_fail+=result.get(timeout=TIMEOUT_DUR) + except TimeoutError: + pool.terminate() + num_fail+=1 + print(f"{bcolors.FAIL}%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.cmd, TIMEOUT_DUR)) # Coverage report if args.ccov: diff --git a/bin/wsim b/bin/wsim index 2b3849ecc..56abd9567 100755 --- a/bin/wsim +++ b/bin/wsim @@ -101,10 +101,10 @@ if (args.lockstep or args.lockstepverbose): if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog) else: ImperasPlusArgs = "" if(args.fcov): - CovEnableStr = "1" if int(args.covlog) > 0 else "0"; + CovEnableStr = "1" if int(args.covlog) > 0 else "0" if(args.covlog >= 1): EnableLog = 1 else: EnableLog = 0 - ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr; + ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr suffix = "" else: CovEnableStr = "" From e61f66eacac8aa511784b513cc1446f1c5c5d110 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 29 Nov 2024 15:43:21 -0800 Subject: [PATCH 121/212] Use cvw-arch-verif tests for code coverage --- bin/regression-wally | 6 +++--- sim/Makefile | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 51827bb76..0383a1807 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -433,9 +433,9 @@ if (args.buildroot): addTests(tests_buildrootbootlockstep, lockstepsim) # lockstep with Questa and ImperasDV runs overnight if (args.ccov): # only run RV64GC tests on Questa in code coverage mode - addTests(tests64gc_nofp, coveragesim) - if (args.fp): - addTests(tests64gc_fp, coveragesim) + addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim) + addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim) + addTestsByDir(WALLY+"/tests/coverage/", "rv64gc", coveragesim) elif (args.fcov): # run tests in lockstep in functional coverage mode addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim) addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim) diff --git a/sim/Makefile b/sim/Makefile index d94936381..5feb25ae4 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -29,8 +29,8 @@ deriv: .PHONY: QuestaCodeCoverage collect_functcov combine_functcov remove_functcov_artifacts riscvdv riscvdv_functcov -QuestaCodeCoverage: questa/ucdb/rv64gc_arch64i.ucdb - vcover merge -out questa/ucdb/cov.ucdb questa/ucdb/rv64gc_arch64i.ucdb questa/ucdb/rv64gc*.ucdb -logfile questa/cov/log +QuestaCodeCoverage: + vcover merge -out questa/ucdb/cov.ucdb questa/ucdb/rv64gc*.ucdb -logfile questa/cov/log # vcover merge -out questa/ucdb/cov.ucdb questa/ucdb/rv64gc_arch64i.ucdb questa/ucdb/rv64gc*.ucdb questa/ucdb/buildroot_buildroot.ucdb riscv.ucdb -logfile questa/cov/log vcover report -details questa/ucdb/cov.ucdb > questa/cov/rv64gc_coverage_details.rpt vcover report questa/ucdb/cov.ucdb -details -instance=/core/ebu. > questa/cov/rv64gc_coverage_ebu.rpt From c5bb2b42a54d98ac86c571256bdfee1aaa712e78 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 29 Nov 2024 15:43:59 -0800 Subject: [PATCH 122/212] cleanup --- bin/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index 0383a1807..09bd1fa9c 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -396,7 +396,7 @@ parser.add_argument("--fcov", help="Functional Coverage", action="store_true") parser.add_argument("--nightly", help="Run large nightly regression", action="store_true") parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true") parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true") -parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true") +parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true") # Currently not used parser.add_argument("--dryrun", help="Print commands invoked to console without running regression", action="store_true") args = parser.parse_args() From b766c423f3391f4b4a48e17d5881dc29d2e4c745 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 30 Nov 2024 16:14:37 -0800 Subject: [PATCH 123/212] Disable Zks in imperas.ic files --- config/rv32gc/imperas.ic | 14 +++++++++----- config/rv64gc/imperas.ic | 14 +++++++++----- 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic index 0c3f2e2ea..b7d24b1b5 100644 --- a/config/rv32gc/imperas.ic +++ b/config/rv32gc/imperas.ic @@ -10,7 +10,7 @@ # Core settings --variant RV32GCK # for RV32GC ---override cpu/priv_version=1.12 +--override cpu/priv_version=1.12 --override cpu/user_version=20191213 # arch --override cpu/mimpid=0x100 @@ -20,7 +20,7 @@ --override refRoot/cpu/envcfg_mask=1 # dh 1/26/24 this should be deleted when ImperasDV is updated to allow envcfg.FIOM to be written # bit manipulation ---override cpu/add_Extensions=B +--override cpu/add_Extensions=B --override cpu/bitmanip_version=1.0.0 --override cpu/misa_B_Zba_Zbb_Zbs=T @@ -70,9 +70,9 @@ --override cpu/trigger_num=0 # disable CSRs 7a0-7a8 # For code coverage, don't produce pseudoinstructions ---override no_pseudo_inst=T +--override no_pseudo_inst=T -# Show "c." with compressed instructions +# Show "c." with compressed instructions --override show_c_prefix=T # nonratified mnoise register not implemented @@ -88,6 +88,10 @@ # Zkr entropy source and seed register not supported. --override cpu/Zkr=F +# ShangMi Crypto not supported +--override cpu/Zksed=F +--override cpu/Zksh=F + --override cpu/reset_address=0x80000000 --override cpu/unaligned=F # Zicclsm (should be true) @@ -107,7 +111,7 @@ # mstatus.FS is set dirty on any write to a FPR, or when a fp operation signals an exception --override cpu/mstatus_fs_mode=write_1 -# PMA Settings +# PMA Settings # 'r': read access allowed # 'w': write access allowed # 'x': execute access allowed diff --git a/config/rv64gc/imperas.ic b/config/rv64gc/imperas.ic index 19a7515a5..e3cefb911 100644 --- a/config/rv64gc/imperas.ic +++ b/config/rv64gc/imperas.ic @@ -9,7 +9,7 @@ #--showcommands # Core settings ---override cpu/priv_version=1.12 +--override cpu/priv_version=1.12 --override cpu/user_version=20191213 # arch --override cpu/mimpid=0x100 @@ -19,7 +19,7 @@ --override refRoot/cpu/envcfg_mask=1 # dh 1/26/24 this should be deleted when ImperasDV is updated to allow envcfg.FIOM to be written # bit manipulation ---override cpu/add_Extensions=B +--override cpu/add_Extensions=B --override cpu/bitmanip_version=1.0.0 --override cpu/misa_B_Zba_Zbb_Zbs=T @@ -68,9 +68,9 @@ --override cpu/trigger_num=0 # disable CSRs 7a0-7a8 # For code coverage, don't produce pseudoinstructions ---override no_pseudo_inst=T +--override no_pseudo_inst=T -# Show "c." with compressed instructions +# Show "c." with compressed instructions --override show_c_prefix=T # nonratified mnoise register not implemented @@ -86,6 +86,10 @@ # Zkr entropy source and seed register not supported. --override cpu/Zkr=F +# ShangMi Crypto not supported +--override cpu/Zksed=F +--override cpu/Zksh=F + --override cpu/reset_address=0x80000000 --override cpu/unaligned=T # Zicclsm (should be true) @@ -105,7 +109,7 @@ # mstatus.FS is set dirty on any write to a FPR, or when a fp operation signals an exception --override cpu/mstatus_fs_mode=write_1 -# PMA Settings +# PMA Settings # 'r': read access allowed # 'w': write access allowed # 'x': execute access allowed From b7467156c5692220a0c098faa04d03fce03bad33 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 30 Nov 2024 19:12:01 -0800 Subject: [PATCH 124/212] Hello Wally application now running, can print in spike and wsim via UART. Verilator simulation is broken --- examples/C/common/syscalls.c | 60 ++++++++++++++++++++++++++++++++++-- examples/C/hello/Makefile | 33 ++++++++++++++++++++ examples/C/hello/hello.c | 23 ++++++++++++++ 3 files changed, 114 insertions(+), 2 deletions(-) create mode 100644 examples/C/hello/Makefile create mode 100644 examples/C/hello/hello.c diff --git a/examples/C/common/syscalls.c b/examples/C/common/syscalls.c index 39547b3d0..6f57475bc 100644 --- a/examples/C/common/syscalls.c +++ b/examples/C/common/syscalls.c @@ -15,6 +15,44 @@ extern volatile uint64_t tohost; extern volatile uint64_t fromhost; +///////////////////////////// +// Start of code added for Wally +// Use UART rather than syscall host interface for printing +////////////////////////////// + +#include + +void uartInit(void) { + volatile uint8_t *UART_LCR = (uint8_t*)0x10000003; + *UART_LCR = 0b0000011; // 8-bit characters, 1 stop bit, no parity +} + +void uartSend(char c) { + volatile uint8_t *UART_THR = (uint8_t*)0x10000000; + volatile uint8_t *UART_LSR = (uint8_t*)0x10000005; + + while (!(*UART_LSR & (1<<5))); // wait for THRE (trans hold reg empty) + *UART_THR = c; +} + +char uartReceive(void) { + volatile uint8_t *UART_RBR = (uint8_t*)0x10000000; + volatile uint8_t *UART_LSR = (uint8_t*)0x10000005; + + while (!(*UART_LSR & (1<<0))); // wait for DR (Data Ready) + return *UART_RBR; +} + +char uartPutStr(const char *str) { + while (*str) { + uartSend(*str++); + } +} + +///////////////////////////// +// End of code added for Wally +////////////////////////////// + static uintptr_t syscall(uintptr_t which, uint64_t arg0, uint64_t arg1, uint64_t arg2) { volatile uint64_t magic_mem[8] __attribute__((aligned(64))); @@ -76,7 +114,19 @@ void abort() void printstr(const char* s) { - syscall(SYS_write, 1, (uintptr_t)s, strlen(s)); + // david_harris@hmc.edu 11/30/24 switch to printing via UART rather than syscall + // This works on both Spike and Wally simulations + //syscall(SYS_write, 1, (uintptr_t)s, strlen(s)); + uartPutStr(s); +} + +// Added 30 November 2024 David_Harris@hmc.edu +// The compiler encountering printf with a pure string argument tries to invoke puts +// rather than the usual printf, so puts must be defined. +int puts(const char* s) +{ + printstr(s); + return 0; } void __attribute__((weak)) thread_entry(int cid, int nc) @@ -107,6 +157,7 @@ void _init(int cid, int nc) { init_tls(); thread_entry(cid, nc); + uartInit(); // added 11/30/2024 David_Harris@hmc.edu for printing via UART // only single-threaded programs should ever get here. int ret = main(0, 0); @@ -125,6 +176,11 @@ void _init(int cid, int nc) #undef putchar int putchar(int ch) { + // David_Harris@hmc.edu 11/30/2024 + // Replaced syscall with uartSend + uartSend(ch); + + /* static __thread char buf[64] __attribute__((aligned(64))); static __thread int buflen = 0; @@ -134,7 +190,7 @@ int putchar(int ch) { syscall(SYS_write, 1, (uintptr_t)buf, buflen); buflen = 0; - } + } */ return 0; } diff --git a/examples/C/hello/Makefile b/examples/C/hello/Makefile new file mode 100644 index 000000000..ea1ceb910 --- /dev/null +++ b/examples/C/hello/Makefile @@ -0,0 +1,33 @@ +TARGET = hello + +$(TARGET).objdump: $(TARGET) + riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump + cp $(TARGET) $(TARGET).elf + +$(TARGET): $(TARGET).c Makefile + riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\ + -march=rv64gc -mabi=lp64d -mcmodel=medany \ + -nostdlib -static -lm -fno-tree-loop-distribute-patterns \ + -T../common/test.ld -I../common \ + $(TARGET).c ../common/crt.S ../common/syscalls.c +# Compiler flags: +# -o $(TARGET) defines the name of the output file +# -g generates debugging symbols for gdb +# -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization +# -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits +# -static forces static linking (no dynamic shared libraries on bare metal) +# -lm links the math library if necessary (when #include math.h) +# -nostdlib avoids inserting standard startup files and default libraries +# because we are using crt.s on bare metal +# -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library +# -T specifies the linker file +# -I specifies the include path (e.g. for util.h) +# The last line defines the C files to compile. +# crt.S is needed as our startup file to initialize the processor +# syscalls.c implements printf through the HTIF for Spike +# other flags from riscv-tests makefiles that don't seem to be important +# -ffast-math -DPREALLOCATE=1 -std=gnu99 \ +# -fno-common -fno-builtin-printf -nostartfiles -lgcc \ + +clean: + rm -f $(TARGET) $(TARGET).objdump diff --git a/examples/C/hello/hello.c b/examples/C/hello/hello.c new file mode 100644 index 000000000..4e1215cfb --- /dev/null +++ b/examples/C/hello/hello.c @@ -0,0 +1,23 @@ +// hello.c +// David_Harris@hmc.edu 30 November 2024 + +// Hello World program illustrating compiled C code printing via the UART +// The Wally team has modified the Berkeley syscalls.c (in examples/C/common) +// to print via UART rather than the syscall interface. This is supported +// on both Spike and Wally. It assumes the PC16550-compatible UART is at +// the default SiFive address of 0x10000000. +// Note that there seem to be some discrepancies between the UART and Spike +// such that using \n\r for new lines works best. + +// compile with make +// simulate with: wsim rv64gc hello.elf --sim verilator + +#include + +int main(void) { + printf("Hello Wally!\n\r"); + for (int i = 0; i < 10; i++) { + printf("%d ", i); + } + printf("\n\r"); +} \ No newline at end of file From a4301babff29b2c3fc12106d70d764b10314b890 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 30 Nov 2024 19:41:13 -0800 Subject: [PATCH 125/212] GPIO example --- .gitignore | 2 + examples/C/gpio/Makefile | 33 ++++++++++++++++ examples/C/gpio/gpio.c | 28 ++++++++++++++ examples/C/gpio/gpiolib.h | 81 +++++++++++++++++++++++++++++++++++++++ examples/C/hello/hello.c | 4 +- 5 files changed, 147 insertions(+), 1 deletion(-) create mode 100644 examples/C/gpio/Makefile create mode 100644 examples/C/gpio/gpio.c create mode 100644 examples/C/gpio/gpiolib.h diff --git a/.gitignore b/.gitignore index 64fbbbf23..9a0f35cc1 100644 --- a/.gitignore +++ b/.gitignore @@ -153,6 +153,8 @@ examples/C/mcmodel/mcmodel_medany examples/C/mcmodel/mcmodel_medlow examples/C/sum/sum examples/C/sum_mixed/sum_mixed +examples/C/hello/hello +examples/C/gpio/gpio examples/asm/sumtest/sumtest examples/asm/example/example examples/asm/trap/trap diff --git a/examples/C/gpio/Makefile b/examples/C/gpio/Makefile new file mode 100644 index 000000000..c33425ac7 --- /dev/null +++ b/examples/C/gpio/Makefile @@ -0,0 +1,33 @@ +TARGET = gpio + +$(TARGET).objdump: $(TARGET) + riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump + cp $(TARGET) $(TARGET).elf + +$(TARGET): $(TARGET).c Makefile + riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\ + -march=rv64gc -mabi=lp64d -mcmodel=medany \ + -nostdlib -static -lm -fno-tree-loop-distribute-patterns \ + -T../common/test.ld -I../common \ + $(TARGET).c ../common/crt.S ../common/syscalls.c +# Compiler flags: +# -o $(TARGET) defines the name of the output file +# -g generates debugging symbols for gdb +# -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization +# -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits +# -static forces static linking (no dynamic shared libraries on bare metal) +# -lm links the math library if necessary (when #include math.h) +# -nostdlib avoids inserting standard startup files and default libraries +# because we are using crt.s on bare metal +# -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library +# -T specifies the linker file +# -I specifies the include path (e.g. for util.h) +# The last line defines the C files to compile. +# crt.S is needed as our startup file to initialize the processor +# syscalls.c implements printf through the HTIF for Spike +# other flags from riscv-tests makefiles that don't seem to be important +# -ffast-math -DPREALLOCATE=1 -std=gnu99 \ +# -fno-common -fno-builtin-printf -nostartfiles -lgcc \ + +clean: + rm -f $(TARGET) $(TARGET).objdump diff --git a/examples/C/gpio/gpio.c b/examples/C/gpio/gpio.c new file mode 100644 index 000000000..64f3b5a08 --- /dev/null +++ b/examples/C/gpio/gpio.c @@ -0,0 +1,28 @@ +// gpio.c +// David_Harris@hmc.edu 30 November 2024 +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +// General-Purpose I/O (GPIO) example program illustrating compiled C code +// compile with make +// simulate with: wsim rv64gc hello.elf --sim verilator + +#include +#include "gpiolib.h" + +int main(void) { + printf("GPIO Example!\n\r"); + pinMode(0, INPUT); + pinMode(1, OUTPUT); + pinMode(2, OUTPUT); + + for (int i=0; i<10; i++) { + // Read pin 0 and write it to pin 1 + int val = digitalRead(0); + printf("Pin 0: %d\n", val); + digitalWrite(1, val); + + // Toggle pin 2 + printf("Pin 2: %d\n", i%2); + digitalWrite(2, i%2); + } +} diff --git a/examples/C/gpio/gpiolib.h b/examples/C/gpio/gpiolib.h new file mode 100644 index 000000000..819089554 --- /dev/null +++ b/examples/C/gpio/gpiolib.h @@ -0,0 +1,81 @@ +// gpiolib.h +// Basic Arduino-compatible functions for general-purpose input/output + +// Assumes GPIO0_BASE is set to the memory-mapped GPIO address from +// config/rv64gc/config.vh. + +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +#include + +/////////////////////////////////////////////////////////////////////////////// +// Bitfield Structs +/////////////////////////////////////////////////////////////////////////////// + +typedef struct +{ + volatile uint32_t input_val; // (GPIO offset 0x00) Pin value + volatile uint32_t input_en; // (GPIO offset 0x04) Pin input enable* + volatile uint32_t output_en; // (GPIO offset 0x08) Pin output enable* + volatile uint32_t output_val; // (GPIO offset 0x0C) Output value + volatile uint32_t pue; // (GPIO offset 0x10) Internal pull-up enable* + volatile uint32_t ds; // (GPIO offset 0x14) Pin drive strength + volatile uint32_t rise_ie; // (GPIO offset 0x18) Rise interrupt enable + volatile uint32_t rise_ip; // (GPIO offset 0x1C) Rise interrupt pending + volatile uint32_t fall_ie; // (GPIO offset 0x20) Fall interrupt enable + volatile uint32_t fall_ip; // (GPIO offset 0x24) Fall interrupt pending + volatile uint32_t high_ie; // (GPIO offset 0x28) High interrupt enable + volatile uint32_t high_ip; // (GPIO offset 0x2C) High interrupt pending + volatile uint32_t low_ie; // (GPIO offset 0x30) Low interrupt enable + volatile uint32_t low_ip; // (GPIO offset 0x34) Low interrupt pending + volatile uint32_t iof_en; // (GPIO offset 0x38) HW-Driven functions enable + volatile uint32_t iof_sel; // (GPIO offset 0x3C) HW-Driven functions selection + volatile uint32_t out_xor; // (GPIO offset 0x40) Output XOR (invert) + // Registers marked with * are asynchronously reset to 0. All others are synchronously reset to 0. +} GPIO; + +/////////////////////////////////////////////////////////////////////////////// +// GPIO Constant Definitions +/////////////////////////////////////////////////////////////////////////////// + +#define GPIO0_BASE (0x10060000U) // GPIO memory-mapped base address + +#define GPIO0 ((GPIO*) GPIO0_BASE) // Set up pointer to struct of type GPIO aligned at the base GPIO0 memory-mapped address + +#define LOW 0 +#define HIGH 1 + +#define INPUT 0 +#define OUTPUT 1 +#define GPIO_IOF0 2 + +/////////////////////////////////////////////////////////////////////////////// +// GPIO Functions +/////////////////////////////////////////////////////////////////////////////// + +void pinMode(int pin, int function) +{ + switch(function) { + case INPUT: + GPIO0->input_en |= (1 << pin); // Sets a pin as an input + break; + case OUTPUT: + GPIO0->output_en |= (1 << pin); // Set pin as an output + GPIO0->iof_en &= ~(1 << pin); + break; + case GPIO_IOF0: + GPIO0->iof_sel &= ~(1 << pin); + GPIO0->iof_en |= (1 << pin); + } +} + +void digitalWrite(int pin, int val) +{ + if (val) GPIO0->output_val |= (1 << pin); + else GPIO0->output_val &= ~(1 << pin); +} + +int digitalRead(int pin) +{ + return (GPIO0->input_val >> pin) & 0x1; +} diff --git a/examples/C/hello/hello.c b/examples/C/hello/hello.c index 4e1215cfb..2a6cfa033 100644 --- a/examples/C/hello/hello.c +++ b/examples/C/hello/hello.c @@ -1,5 +1,6 @@ // hello.c // David_Harris@hmc.edu 30 November 2024 +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // Hello World program illustrating compiled C code printing via the UART // The Wally team has modified the Berkeley syscalls.c (in examples/C/common) @@ -10,7 +11,8 @@ // such that using \n\r for new lines works best. // compile with make -// simulate with: wsim rv64gc hello.elf --sim verilator +// simulate Wally with: wsim rv64gc hello.elf --sim verilator +// simulate in Spike with: spike hello.elf #include From 9ee4a2b408d69167675758f2c6fc2a84079a3686 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 30 Nov 2024 23:04:13 -0800 Subject: [PATCH 126/212] Support Elffiles on all simulators --- bin/wsim | 11 ++++------- sim/vcs/run_vcs | 5 ++--- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/bin/wsim b/bin/wsim index 56abd9567..4e03b0d95 100755 --- a/bin/wsim +++ b/bin/wsim @@ -64,6 +64,9 @@ if(args.testsuite.endswith('.elf') and args.elf == ""): # No --elf argument; che print("ELF file not found: " + args.testsuite) exit(1) +if (ElfFile != ""): + args.args += " " + ElfFile + if(args.lockstep and not args.testsuite.endswith('.elf') and not args.testsuite == "buildroot"): print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf.") exit(1) @@ -143,8 +146,6 @@ if (args.tb == "testbench_fp" and args.sim != "questa"): if (args.sim == "questa"): if (args.gui) and (args.tb == "testbench"): args.params += "DEBUG=1" - if (ElfFile != ""): - args.args += " " + ElfFile if (args.args != ""): args.args = " --args \\\"" + args.args + "\\\"" if (args.params != ""): @@ -162,7 +163,6 @@ elif (args.sim == "verilator"): print(f"Running Verilator on {args.config} {args.testsuite}") os.system(f"/usr/bin/make -C {regressionDir}/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} PLUS_ARGS=\"{args.args}\" PARAM_ARGS=\"{args.params}\"") elif (args.sim == "vcs"): - print("wsim params: " + args.params) print(f"Running VCS on " + args.config + " " + args.testsuite) # if (args.gui): # flags += " --gui" @@ -174,9 +174,6 @@ elif (args.sim == "vcs"): vcsparams = "" else: vcsparams = " --params \"" + args.params + "\" " - print("VCS params: " + vcsparams) - if (ElfFile != ""): - ElfFile = " --elffile " + ElfFile - cmd = cd + "; " + prefix + " ./run_vcs " + args.config + " " + args.testsuite + " " + " --tb " + args.tb + " " + vcsargs + vcsparams + ElfFile + " " + flags + cmd = cd + "; " + prefix + " ./run_vcs " + args.config + " " + args.testsuite + " " + " --tb " + args.tb + " " + vcsargs + vcsparams + " " + flags print(cmd) os.system(cmd) diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs index 02eccc59b..1234ac4c8 100755 --- a/sim/vcs/run_vcs +++ b/sim/vcs/run_vcs @@ -24,7 +24,6 @@ parser = argparse.ArgumentParser() parser.add_argument("config", help="Configuration file") parser.add_argument("testsuite", help="Test suite (or none, when running a single ELF file) ") parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench") -parser.add_argument("--elffile", "-e", help="ELF file name", default="") parser.add_argument("--coverage", "-c", help="Code & Functional Coverage", action="store_true") parser.add_argument("--fcov", "-f", help="Code & Functional Coverage", action="store_true") parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="") @@ -33,7 +32,7 @@ parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and comp # GUI not yet implemented #parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true") args = parser.parse_args() -print("run_vcs Config=" + args.config + " tests=" + args.testsuite + " elffile=" + args.elffile + " lockstep=" + str(args.lockstep) + " args='" + args.args + "'") +print("run_vcs Config=" + args.config + " tests=" + args.testsuite + " lockstep=" + str(args.lockstep) + " args='" + args.args + "' params='" + args.params + "'") cfgdir = "$WALLY/config" srcdir = "$WALLY/src" @@ -88,7 +87,7 @@ PARAM_OVERRIDES=" -parameters " + wkdir + "/param_overrides.txt " OUTPUT="sim_out" VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF -suppress +warn -sverilog +vc -Mupdate -line -full64 -lca -ntb_opts sensitive_dyn " + "-top " + args.tb + PARAM_OVERRIDES + INCLUDE_PATH # Disabled Debug flags; add them back for a GUI mode -debug_access+all+reverse -kdb +vcs+vcdpluson VCS = VCS_CMD + " -Mdir=" + wkdir + " " + srcdir + "/cvw.sv " + LOCKSTEP_OPTIONS + " " + COV_OPTIONS + " " + RTL_FILES + " -o " + wkdir + "/" + OUTPUT + " -work " + wkdir + " -Mlib=" + wkdir + " -l " + logdir + "/" + args.config + "_" + args.testsuite + ".log" -SIMV_CMD= wkdir + "/" + OUTPUT + " +TEST=" + args.testsuite + " " + args.elffile + " " + args.args + " -no_save " + LOCKSTEP_SIMV +SIMV_CMD= wkdir + "/" + OUTPUT + " +TEST=" + args.testsuite + " " + args.args + " -no_save " + LOCKSTEP_SIMV # Run simulation print("Executing: " + str(VCS) ) From cd90e81c76095135f7d298d7b0d4f2f7c23a64fc Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 30 Nov 2024 23:43:51 -0800 Subject: [PATCH 127/212] wsim cleanup --- bin/wsim | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/bin/wsim b/bin/wsim index 4e03b0d95..907ff9105 100755 --- a/bin/wsim +++ b/bin/wsim @@ -72,10 +72,12 @@ if(args.lockstep and not args.testsuite.endswith('.elf') and not args.testsuite exit(1) # Validate arguments -if (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose): - if args.sim not in ["questa", "vcs"]: - print("Option only supported for Questa and VCS") - exit(1) +if (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose) and args.sim not in ["questa", "vcs"]: + print("Option only supported for Questa and VCS") + exit(1) +elif (args.tb == "testbench_fp" and args.sim != "questa"): + print("Error: testbench_fp presently only supported by Questa, not VCS or Verilator, because of a touchy testbench") + exit(1) if (args.vcd): args.args += " -DMAKEVCD=1" @@ -91,14 +93,10 @@ if(int(args.locksteplog) >= 1): EnableLog = 1 else: EnableLog = 0 prefix = "" if (args.lockstep or args.lockstepverbose or args.fcov): - if (args.sim == "questa" or args.sim == "vcs"): - imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic") - if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs - imperasicPath = os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic") - prefix = "IMPERAS_TOOLS=" + imperasicPath -# Force Questa to use 64-bit mode, sometimes it defaults to 32-bit even on 64-bit machines -if (args.sim == "questa"): - prefix = "MTI_VCO_MODE=64 " + prefix + imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic") + if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs + imperasicPath = os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic") + prefix = "IMPERAS_TOOLS=" + imperasicPath if (args.lockstep or args.lockstepverbose): if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog) @@ -137,13 +135,10 @@ for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb"]: cd = "cd $WALLY/sim/" +args.sim -# check for unsupported sims -if (args.tb == "testbench_fp" and args.sim != "questa"): - print("Error: testbench_fp presently only supported by Questa, not VCS or Verilator, because of a touchy testbench") - exit(1) - # per-simulator launch if (args.sim == "questa"): + # Force Questa to use 64-bit mode, sometimes it defaults to 32-bit even on 64-bit machines + prefix = "MTI_VCO_MODE=64 " + prefix if (args.gui) and (args.tb == "testbench"): args.params += "DEBUG=1" if (args.args != ""): @@ -159,7 +154,6 @@ if (args.sim == "questa"): print("Running Questa with command: " + cmd) os.system(cmd) elif (args.sim == "verilator"): - # PWD=${WALLY}/sim CONFIG=rv64gc TESTSUITE=arch64i print(f"Running Verilator on {args.config} {args.testsuite}") os.system(f"/usr/bin/make -C {regressionDir}/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} PLUS_ARGS=\"{args.args}\" PARAM_ARGS=\"{args.params}\"") elif (args.sim == "vcs"): From fbe3254857cb152bf569e3f998c1f300c5bec18c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 1 Dec 2024 14:16:24 -0800 Subject: [PATCH 128/212] Refactor wsim to use smaller functions and f-strings --- bin/wsim | 264 ++++++++++++++++++++++++++++--------------------------- 1 file changed, 134 insertions(+), 130 deletions(-) diff --git a/bin/wsim b/bin/wsim index 907ff9105..44d9152f5 100755 --- a/bin/wsim +++ b/bin/wsim @@ -14,160 +14,164 @@ import argparse import os -######################## -# main wsim script -######################## - -# Parse arguments -parser = argparse.ArgumentParser() -parser.add_argument("config", help="Configuration file") -parser.add_argument("testsuite", help="Test suite or path to .elf file") -parser.add_argument("--elf", "-e", help="ELF File name; use if name does not end in .elf", default="") -parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilator", "vcs"], default="questa") -parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench") -parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true") -parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true") -parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true") -parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="") -parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="") -parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true") -parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true") -parser.add_argument("--locksteplog", "-b", help="Retired instruction number to be begin logging.", default=0) -parser.add_argument("--lockstepverbose", "-lv", help="Run ImperasDV lock, step, and compare with tracing enabled", action="store_true") -parser.add_argument("--covlog", "-d", help="Log coverage after n instructions.", default=0) -parser.add_argument("--rvvi", "-r", help="Simulate rvvi hardware interface and ethernet.", action="store_true") -args = parser.parse_args() -print("Config=" + args.config + " tests=" + args.testsuite + " sim=" + args.sim + " gui=" + str(args.gui) + " args='" + args.args + "'") -ElfFile="" +# Global variable WALLY = os.environ.get('WALLY') -if(os.path.isfile(args.elf)): - ElfFile = "+ElfFile=" + os.path.abspath(args.elf) -elif (args.elf != ""): - print("ELF file not found: " + args.elf) - exit(1) +def parseArgs(): + parser = argparse.ArgumentParser() + parser.add_argument("config", help="Configuration file") + parser.add_argument("testsuite", help="Test suite or path to .elf file") + parser.add_argument("--elf", "-e", help="ELF File name; use if name does not end in .elf", default="") + parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilator", "vcs"], default="questa") + parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench") + parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true") + parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true") + parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true") + parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="") + parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="") + parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true") + parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true") + parser.add_argument("--locksteplog", "-b", help="Retired instruction number to be begin logging.", default=0) + parser.add_argument("--lockstepverbose", "-lv", help="Run ImperasDV lock, step, and compare with tracing enabled", action="store_true") + parser.add_argument("--covlog", "-d", help="Log coverage after n instructions.", default=0) + parser.add_argument("--rvvi", "-r", help="Simulate rvvi hardware interface and ethernet.", action="store_true") + return parser.parse_args() -if(args.testsuite.endswith('.elf') and args.elf == ""): # No --elf argument; check if testsuite has a .elf extension and use that instead - if (os.path.isfile(args.testsuite)): - ElfFile = "+ElfFile=" + os.path.abspath(args.testsuite) - # extract the elf name from the path to be the test suite - fields = args.testsuite.rsplit('/', 3) - # if the name is just ref.elf in a deep path (riscv-arch-test/wally-riscv-arch-test), then use the directory name as the test suite to make it unique; otherwise work directory will have duplicates. - if (len(fields) > 3): - if (fields[2] == "ref"): - args.testsuite = fields[1] + "_" + fields[3] - else: - args.testsuite = fields[2] + "_" + fields[3] - elif ('/' in args.testsuite): - args.testsuite=args.testsuite.rsplit('/', 1)[1] # strip off path if present - else: - print("ELF file not found: " + args.testsuite) +def elfFileCheck(args): + ElfFile = "" + if os.path.isfile(args.elf): + ElfFile = f"+ElfFile={os.path.abspath(args.elf)}" + elif args.elf != "": + print(f"ELF file not found: {args.elf}") + exit(1) + elif args.testsuite.endswith('.elf'): # No --elf argument; check if testsuite has a .elf extension and use that instead + if os.path.isfile(args.testsuite): + ElfFile = f"+ElfFile={os.path.abspath(args.testsuite)}" + # extract the elf name from the path to be the test suite + fields = args.testsuite.rsplit('/', 3) + # if the name is just ref.elf in a deep path (riscv-arch-test/wally-riscv-arch-test), then use the directory name as the test suite to make it unique; otherwise work directory will have duplicates. + if (len(fields) > 3): + if (fields[2] == "ref"): + args.testsuite = f"{fields[1]}_{fields[3]}" + else: + args.testsuite = f"{fields[2]}_{fields[3]}" + elif ('/' in args.testsuite): + args.testsuite=args.testsuite.rsplit('/', 1)[1] # strip off path if present + else: + print(f"ELF file not found: {args.testsuite}") + exit(1) + return ElfFile + +def validateArgs(args): + if(args.lockstep and not args.testsuite.endswith('.elf') and not args.testsuite == "buildroot"): + print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf.") + exit(1) + elif (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose) and args.sim not in ["questa", "vcs"]: + print("Option only supported for Questa and VCS") + exit(1) + elif (args.tb == "testbench_fp" and args.sim != "questa"): + print("Error: testbench_fp presently only supported by Questa, not VCS or Verilator, because of a touchy testbench") exit(1) -if (ElfFile != ""): - args.args += " " + ElfFile +def prepSim(args, ElfFile): + flags = "" + if args.vcd: + args.args += " -DMAKEVCD=1" + if args.rvvi: + args.params += " RVVI_SYNTH_SUPPORTED=1 " + if args.tb == "testbench_fp": + args.params += f" TEST=\" {args.testsuite} \" " + if ElfFile != "": + args.args += f" {ElfFile}" + if args.ccov: + flags += " --ccov" + if args.fcov: + flags += " --fcov" + prefix, suffix = lockstepSetup(args) + flags += suffix + return flags, prefix -if(args.lockstep and not args.testsuite.endswith('.elf') and not args.testsuite == "buildroot"): - print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf.") - exit(1) - -# Validate arguments -if (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose) and args.sim not in ["questa", "vcs"]: - print("Option only supported for Questa and VCS") - exit(1) -elif (args.tb == "testbench_fp" and args.sim != "questa"): - print("Error: testbench_fp presently only supported by Questa, not VCS or Verilator, because of a touchy testbench") - exit(1) - -if (args.vcd): - args.args += " -DMAKEVCD=1" - -if (args.rvvi): - args.params += " RVVI_SYNTH_SUPPORTED=1 " - -if (args.tb == "testbench_fp"): - args.params += " TEST=\"" + args.testsuite + "\" " - -# if lockstep is enabled, then we need to pass the Imperas lockstep arguments -if(int(args.locksteplog) >= 1): EnableLog = 1 -else: EnableLog = 0 -prefix = "" -if (args.lockstep or args.lockstepverbose or args.fcov): - imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic") - if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs - imperasicPath = os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic") - prefix = "IMPERAS_TOOLS=" + imperasicPath - -if (args.lockstep or args.lockstepverbose): - if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog) - else: ImperasPlusArgs = "" - if(args.fcov): - CovEnableStr = "1" if int(args.covlog) > 0 else "0" - if(args.covlog >= 1): EnableLog = 1 - else: EnableLog = 0 - ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr - suffix = "" - else: - CovEnableStr = "" - suffix = "--lockstep" - if(args.lockstepverbose): - prefix += ":" + WALLY + "/sim/imperas-verbose.ic" -else: - ImperasPlusArgs = "" +def lockstepSetup(args): + prefix = "" suffix = "" -flags = suffix -args.args += ImperasPlusArgs + ImperasPlusArgs = "" + if(int(args.locksteplog) >= 1): EnableLog = 1 + else: EnableLog = 0 + if (args.lockstep or args.lockstepverbose or args.fcov): + imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic") + if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs + imperasicPath = os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic") + if not os.path.isfile(imperasicPath): + print("Error: imperas.ic not found") + exit(1) + prefix += f"IMPERAS_TOOLS= {imperasicPath}" -# other flags -if (args.ccov): - flags += " --ccov" -if (args.fcov): - flags += " --fcov" + if (args.lockstep or args.lockstepverbose): + if(args.locksteplog != 0): ImperasPlusArgs = f" +IDV_TRACE2LOG={EnableLog} +IDV_TRACE2LOG_AFTER={args.locksteplog}" + if(args.fcov): + CovEnableStr = "1" if int(args.covlog) > 0 else "0" + if(args.covlog >= 1): EnableLog = 1 + else: EnableLog = 0 + ImperasPlusArgs = f" +IDV_TRACE2COV={EnableLog} +TRACE2LOG_AFTER={args.covlog} +TRACE2COV_ENABLE={CovEnableStr}" + else: + suffix = "--lockstep" + if(args.lockstepverbose): + prefix += f":{WALLY}/sim/imperas-verbose.ic" + args.args += ImperasPlusArgs + return prefix, suffix -# create the output sub-directories. -regressionDir = WALLY + '/sim/' -for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb"]: - try: - os.mkdir(regressionDir+args.sim+"/"+d) - except: - pass +def createDirs(args): + for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb"]: + os.makedirs(os.path.join(WALLY, "sim", args.sim, d), exist_ok=True) -cd = "cd $WALLY/sim/" +args.sim +def runSim(args, flags, prefix): + if (args.sim == "questa"): + runQuesta(args, flags, prefix) + elif (args.sim == "verilator"): + runVerilator(args, flags, prefix) + elif (args.sim == "vcs"): + runVCS(args, flags, prefix) -# per-simulator launch -if (args.sim == "questa"): +def runQuesta(args, flags, prefix): # Force Questa to use 64-bit mode, sometimes it defaults to 32-bit even on 64-bit machines prefix = "MTI_VCO_MODE=64 " + prefix if (args.gui) and (args.tb == "testbench"): args.params += "DEBUG=1" if (args.args != ""): - args.args = " --args \\\"" + args.args + "\\\"" + args.args = f" --args \\\"{args.args}\\\"" if (args.params != ""): - args.params = " --params \\\"" + args.params + "\\\"" + args.params = f" --params \\\"{args.params}\\\"" # Questa cannot accept more than 9 arguments. fcov implies lockstep - cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args + " " + args.params + " " + flags + cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {flags}" if (args.gui): # launch Questa with GUI; add +acc to keep variables accessible - cmd = cd + "; " + prefix + " vsim -do \"" + cmd + " +acc\"" + cmd = f"cd $WALLY/sim/questa; {prefix} vsim -do \" {cmd} +acc\"" else: # launch Questa in batch mode - cmd = cd + "; " + prefix + " vsim -c -do \"" + cmd + "\"" - print("Running Questa with command: " + cmd) + cmd = f"cd $WALLY/sim/questa; {prefix} vsim -c -do \" {cmd} \"" + print(f"Running Questa with command: {cmd}") os.system(cmd) -elif (args.sim == "verilator"): + +def runVerilator(args, flags, prefix): print(f"Running Verilator on {args.config} {args.testsuite}") - os.system(f"/usr/bin/make -C {regressionDir}/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} PLUS_ARGS=\"{args.args}\" PARAM_ARGS=\"{args.params}\"") -elif (args.sim == "vcs"): - print(f"Running VCS on " + args.config + " " + args.testsuite) + os.system(f"/usr/bin/make -C {WALLY}/sim/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} PLUS_ARGS=\"{args.args}\" PARAM_ARGS=\"{args.params}\"") + +def runVCS(args, flags, prefix): + print(f"Running VCS on {args.config} {args.testsuite}") # if (args.gui): # flags += " --gui" - if (args.args == ""): - vcsargs = "" - else: - vcsargs = " --args \"" + args.args + "\" " - if (args.params == ""): - vcsparams = "" - else: - vcsparams = " --params \"" + args.params + "\" " - cmd = cd + "; " + prefix + " ./run_vcs " + args.config + " " + args.testsuite + " " + " --tb " + args.tb + " " + vcsargs + vcsparams + " " + flags + if (args.args != ""): + args.args = f" --args \"{args.args}\" " + if (args.params != ""): + args.params = f" --params \"{args.params}\" " + cmd = f"cd $WALLY/sim/vcs; {prefix} ./run_vcs {args.config} {args.testsuite} --tb {args.tb} {args.args} {args.params} {flags}" print(cmd) os.system(cmd) + +if __name__ == "__main__": + args = parseArgs() + print(f"Config={args.config} tests={args.testsuite} sim={args.sim} gui={args.gui} args='{args.args} params='{args.params}'") + ElfFile = elfFileCheck(args) + validateArgs(args) + flags, prefix = prepSim(args, ElfFile) + createDirs(args) + exit(runSim(args, flags, prefix)) From 775881f123047fc0e3782c3e0e74dcd7ea427c71 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 1 Dec 2024 14:17:07 -0800 Subject: [PATCH 129/212] Make testsuite parameter to wsim optional if passing the --elf flag --- bin/wsim | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/bin/wsim b/bin/wsim index 44d9152f5..c13216a6f 100755 --- a/bin/wsim +++ b/bin/wsim @@ -20,7 +20,7 @@ WALLY = os.environ.get('WALLY') def parseArgs(): parser = argparse.ArgumentParser() parser.add_argument("config", help="Configuration file") - parser.add_argument("testsuite", help="Test suite or path to .elf file") + parser.add_argument("testsuite", nargs="?", help="Test suite or path to .elf file") parser.add_argument("--elf", "-e", help="ELF File name; use if name does not end in .elf", default="") parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilator", "vcs"], default="questa") parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench") @@ -37,6 +37,20 @@ def parseArgs(): parser.add_argument("--rvvi", "-r", help="Simulate rvvi hardware interface and ethernet.", action="store_true") return parser.parse_args() +def validateArgs(args): + if not args.testsuite and not args.elf: + print("Error: Missing test suite or ELF file") + exit(1) + if(args.lockstep and not args.testsuite.endswith('.elf') and not args.testsuite == "buildroot"): + print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf.") + exit(1) + elif (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose) and args.sim not in ["questa", "vcs"]: + print("Option only supported for Questa and VCS") + exit(1) + elif (args.tb == "testbench_fp" and args.sim != "questa"): + print("Error: testbench_fp presently only supported by Questa, not VCS or Verilator, because of a touchy testbench") + exit(1) + def elfFileCheck(args): ElfFile = "" if os.path.isfile(args.elf): @@ -62,17 +76,6 @@ def elfFileCheck(args): exit(1) return ElfFile -def validateArgs(args): - if(args.lockstep and not args.testsuite.endswith('.elf') and not args.testsuite == "buildroot"): - print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf.") - exit(1) - elif (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose) and args.sim not in ["questa", "vcs"]: - print("Option only supported for Questa and VCS") - exit(1) - elif (args.tb == "testbench_fp" and args.sim != "questa"): - print("Error: testbench_fp presently only supported by Questa, not VCS or Verilator, because of a touchy testbench") - exit(1) - def prepSim(args, ElfFile): flags = "" if args.vcd: @@ -169,9 +172,9 @@ def runVCS(args, flags, prefix): if __name__ == "__main__": args = parseArgs() + validateArgs(args) print(f"Config={args.config} tests={args.testsuite} sim={args.sim} gui={args.gui} args='{args.args} params='{args.params}'") ElfFile = elfFileCheck(args) - validateArgs(args) flags, prefix = prepSim(args, ElfFile) createDirs(args) exit(runSim(args, flags, prefix)) From 4fb282285722322d7cf7d4e0770eacbfc873edf0 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 1 Dec 2024 14:30:34 -0800 Subject: [PATCH 130/212] Use mix of single and double quotes to avoid escaping the quotes in strings --- bin/wsim | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/bin/wsim b/bin/wsim index c13216a6f..60a534d4d 100755 --- a/bin/wsim +++ b/bin/wsim @@ -83,7 +83,7 @@ def prepSim(args, ElfFile): if args.rvvi: args.params += " RVVI_SYNTH_SUPPORTED=1 " if args.tb == "testbench_fp": - args.params += f" TEST=\" {args.testsuite} \" " + args.params += f' TEST="{args.testsuite}" ' if ElfFile != "": args.args += f" {ElfFile}" if args.ccov: @@ -108,7 +108,7 @@ def lockstepSetup(args): if not os.path.isfile(imperasicPath): print("Error: imperas.ic not found") exit(1) - prefix += f"IMPERAS_TOOLS= {imperasicPath}" + prefix += f"IMPERAS_TOOLS={imperasicPath}" if (args.lockstep or args.lockstepverbose): if(args.locksteplog != 0): ImperasPlusArgs = f" +IDV_TRACE2LOG={EnableLog} +IDV_TRACE2LOG_AFTER={args.locksteplog}" @@ -142,30 +142,30 @@ def runQuesta(args, flags, prefix): if (args.gui) and (args.tb == "testbench"): args.params += "DEBUG=1" if (args.args != ""): - args.args = f" --args \\\"{args.args}\\\"" + args.args = f' --args \\"{args.args}\\"' if (args.params != ""): - args.params = f" --params \\\"{args.params}\\\"" + args.params = f' --params \\"{args.params}\\"' # Questa cannot accept more than 9 arguments. fcov implies lockstep cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {flags}" if (args.gui): # launch Questa with GUI; add +acc to keep variables accessible - cmd = f"cd $WALLY/sim/questa; {prefix} vsim -do \" {cmd} +acc\"" + cmd = f'cd $WALLY/sim/questa; {prefix} vsim -do "{cmd} +acc"' else: # launch Questa in batch mode - cmd = f"cd $WALLY/sim/questa; {prefix} vsim -c -do \" {cmd} \"" + cmd = f'cd $WALLY/sim/questa; {prefix} vsim -c -do "{cmd}"' print(f"Running Questa with command: {cmd}") os.system(cmd) def runVerilator(args, flags, prefix): print(f"Running Verilator on {args.config} {args.testsuite}") - os.system(f"/usr/bin/make -C {WALLY}/sim/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} PLUS_ARGS=\"{args.args}\" PARAM_ARGS=\"{args.params}\"") + os.system(f'/usr/bin/make -C {WALLY}/sim/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} PLUS_ARGS="{args.args}" PARAM_ARGS="{args.params}"') def runVCS(args, flags, prefix): print(f"Running VCS on {args.config} {args.testsuite}") # if (args.gui): # flags += " --gui" if (args.args != ""): - args.args = f" --args \"{args.args}\" " + args.args = f' --args "{args.args}" ' if (args.params != ""): - args.params = f" --params \"{args.params}\" " + args.params = f' --params "{args.params}" ' cmd = f"cd $WALLY/sim/vcs; {prefix} ./run_vcs {args.config} {args.testsuite} --tb {args.tb} {args.args} {args.params} {flags}" print(cmd) os.system(cmd) From 79708f8ecca4efd4486257267f3db382ea4ed5e7 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 1 Dec 2024 17:44:07 -0800 Subject: [PATCH 131/212] Change call to make to be lcoation agnostic --- bin/wsim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/wsim b/bin/wsim index 60a534d4d..f098025dd 100755 --- a/bin/wsim +++ b/bin/wsim @@ -156,7 +156,7 @@ def runQuesta(args, flags, prefix): def runVerilator(args, flags, prefix): print(f"Running Verilator on {args.config} {args.testsuite}") - os.system(f'/usr/bin/make -C {WALLY}/sim/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} PLUS_ARGS="{args.args}" PARAM_ARGS="{args.params}"') + os.system(f'make -C {WALLY}/sim/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} PLUS_ARGS="{args.args}" PARAM_ARGS="{args.params}"') def runVCS(args, flags, prefix): print(f"Running VCS on {args.config} {args.testsuite}") From 1932d8bc5dc56931f7b899460ec4fccbc1d6bfab Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 1 Dec 2024 17:56:16 -0800 Subject: [PATCH 132/212] Update testbench makefile to generate memfile even in elf file does not end in .elf --- testbench/Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/testbench/Makefile b/testbench/Makefile index 87870b451..bcecc4c7e 100644 --- a/testbench/Makefile +++ b/testbench/Makefile @@ -2,11 +2,11 @@ # David_Harris@hmc.edu 3 July 2024 # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -%.elf.memfile: %.elf +%.memfile: % riscv64-unknown-elf-elf2hex --bit-width $(if $(findstring rv32,$*),32,64) --input $< --output $@ -%.elf.objdump.addr: %.elf.objdump +%.objdump.addr: %.objdump extractFunctionRadix.sh $< -%.elf.objdump: %.elf - riscv64-unknown-elf-objdump -S -D $< > $@ \ No newline at end of file +%.objdump: % + riscv64-unknown-elf-objdump -S -D $< > $@ From ed2ab62621530ca23406b769bf89ebfcd8ee98a1 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 1 Dec 2024 18:20:37 -0800 Subject: [PATCH 133/212] Fix typo --- bin/wsim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/wsim b/bin/wsim index f098025dd..63b75532b 100755 --- a/bin/wsim +++ b/bin/wsim @@ -173,7 +173,7 @@ def runVCS(args, flags, prefix): if __name__ == "__main__": args = parseArgs() validateArgs(args) - print(f"Config={args.config} tests={args.testsuite} sim={args.sim} gui={args.gui} args='{args.args} params='{args.params}'") + print(f"Config={args.config} tests={args.testsuite} sim={args.sim} gui={args.gui} args='{args.args}' params='{args.params}'") ElfFile = elfFileCheck(args) flags, prefix = prepSim(args, ElfFile) createDirs(args) From f9561721cfa24391f0f2aa05d480f72ffcead659 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 1 Dec 2024 18:34:44 -0800 Subject: [PATCH 134/212] Fix error message --- bin/wsim | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wsim b/bin/wsim index 63b75532b..91f8e30ab 100755 --- a/bin/wsim +++ b/bin/wsim @@ -41,8 +41,8 @@ def validateArgs(args): if not args.testsuite and not args.elf: print("Error: Missing test suite or ELF file") exit(1) - if(args.lockstep and not args.testsuite.endswith('.elf') and not args.testsuite == "buildroot"): - print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf.") + if args.lockstep and not args.testsuite.endswith('.elf') and args.testsuite != "buildroot" : + print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf or buildroot.") exit(1) elif (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose) and args.sim not in ["questa", "vcs"]: print("Option only supported for Questa and VCS") From f426b38b283da0af44e09dba49a8ce68c2034992 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 2 Dec 2024 01:56:39 -0800 Subject: [PATCH 135/212] Adjusted hello and gpio examples to use new wsim --elf syntax --- examples/C/gpio/Makefile | 3 +-- examples/C/gpio/gpio.c | 2 +- examples/C/hello/Makefile | 3 +-- examples/C/hello/hello.c | 4 ++-- 4 files changed, 5 insertions(+), 7 deletions(-) diff --git a/examples/C/gpio/Makefile b/examples/C/gpio/Makefile index c33425ac7..237578a46 100644 --- a/examples/C/gpio/Makefile +++ b/examples/C/gpio/Makefile @@ -2,7 +2,6 @@ TARGET = gpio $(TARGET).objdump: $(TARGET) riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump - cp $(TARGET) $(TARGET).elf $(TARGET): $(TARGET).c Makefile riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\ @@ -30,4 +29,4 @@ $(TARGET): $(TARGET).c Makefile # -fno-common -fno-builtin-printf -nostartfiles -lgcc \ clean: - rm -f $(TARGET) $(TARGET).objdump + rm -f $(TARGET) $(TARGET).objdump* $(TARGET).memfile diff --git a/examples/C/gpio/gpio.c b/examples/C/gpio/gpio.c index 64f3b5a08..8d303a797 100644 --- a/examples/C/gpio/gpio.c +++ b/examples/C/gpio/gpio.c @@ -4,7 +4,7 @@ // General-Purpose I/O (GPIO) example program illustrating compiled C code // compile with make -// simulate with: wsim rv64gc hello.elf --sim verilator +// simulate with: wsim rv64gc --elf hello.elf --sim verilator #include #include "gpiolib.h" diff --git a/examples/C/hello/Makefile b/examples/C/hello/Makefile index ea1ceb910..b6003d5c0 100644 --- a/examples/C/hello/Makefile +++ b/examples/C/hello/Makefile @@ -2,7 +2,6 @@ TARGET = hello $(TARGET).objdump: $(TARGET) riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump - cp $(TARGET) $(TARGET).elf $(TARGET): $(TARGET).c Makefile riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\ @@ -30,4 +29,4 @@ $(TARGET): $(TARGET).c Makefile # -fno-common -fno-builtin-printf -nostartfiles -lgcc \ clean: - rm -f $(TARGET) $(TARGET).objdump + rm -f $(TARGET) $(TARGET).objdump* $(TARGET).memfile diff --git a/examples/C/hello/hello.c b/examples/C/hello/hello.c index 2a6cfa033..77c562369 100644 --- a/examples/C/hello/hello.c +++ b/examples/C/hello/hello.c @@ -11,8 +11,8 @@ // such that using \n\r for new lines works best. // compile with make -// simulate Wally with: wsim rv64gc hello.elf --sim verilator -// simulate in Spike with: spike hello.elf +// simulate Wally with: wsim rv64gc --elf hello --sim verilator +// simulate in Spike with: spike hello #include From 8bc2a7fd4f4ead3bc173ec642a88f7abc1f63791 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 2 Dec 2024 02:25:38 -0800 Subject: [PATCH 136/212] Fixed typo in gpio simulation command --- examples/C/gpio/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/C/gpio/gpio.c b/examples/C/gpio/gpio.c index 8d303a797..e2af967e2 100644 --- a/examples/C/gpio/gpio.c +++ b/examples/C/gpio/gpio.c @@ -4,7 +4,7 @@ // General-Purpose I/O (GPIO) example program illustrating compiled C code // compile with make -// simulate with: wsim rv64gc --elf hello.elf --sim verilator +// simulate with: wsim rv64gc --elf gpio --sim verilator #include #include "gpiolib.h" From cfe15481e48346a18bb1f349997eeba845d7c41a Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 2 Dec 2024 14:23:25 +0000 Subject: [PATCH 137/212] Bump addins/cvw-arch-verif from `d6bae48` to `b37edba` Bumps [addins/cvw-arch-verif](https://github.com/openhwgroup/cvw-arch-verif) from `d6bae48` to `b37edba`. - [Commits](https://github.com/openhwgroup/cvw-arch-verif/compare/d6bae481c784461a2d2be14325041ea284319098...b37edba7f625cc3bc2b161d03bc1cd90df0fa2e3) --- updated-dependencies: - dependency-name: addins/cvw-arch-verif dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- addins/cvw-arch-verif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index d6bae481c..b37edba7f 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit d6bae481c784461a2d2be14325041ea284319098 +Subproject commit b37edba7f625cc3bc2b161d03bc1cd90df0fa2e3 From baf2b140e4f55cc39a2f786a184b7aeb7b515e3d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 2 Dec 2024 07:39:29 -0800 Subject: [PATCH 138/212] Add ignore directives to dependabot --- .github/dependabot.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.github/dependabot.yml b/.github/dependabot.yml index a91ebaf1d..96ad736b0 100644 --- a/.github/dependabot.yml +++ b/.github/dependabot.yml @@ -10,6 +10,10 @@ updates: directory: "/" schedule: interval: "weekly" + ignore: + - dependency-name: "coremark" + - dependency-name: "embench-iot" + - dependency-name: "verilog-ethernet" # Update actions in the GitHub Actions workflow files - package-ecosystem: "github-actions" directory: "/" From e37c8e6c6a986acc0ce4b825bad7d40ec87b05a9 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 2 Dec 2024 07:43:37 -0800 Subject: [PATCH 139/212] Fix dependabot ignore conditions? --- .github/dependabot.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/dependabot.yml b/.github/dependabot.yml index 96ad736b0..fe7eab6c8 100644 --- a/.github/dependabot.yml +++ b/.github/dependabot.yml @@ -11,9 +11,9 @@ updates: schedule: interval: "weekly" ignore: - - dependency-name: "coremark" - - dependency-name: "embench-iot" - - dependency-name: "verilog-ethernet" + - dependency-name: "addins/coremark" + - dependency-name: "addins/embench-iot" + - dependency-name: "addins/verilog-ethernet" # Update actions in the GitHub Actions workflow files - package-ecosystem: "github-actions" directory: "/" From e9b0b696965195e13c6304cf762197b3fafd759c Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 2 Dec 2024 14:20:57 -0600 Subject: [PATCH 140/212] Add arty a7 debuggers for wfi and uart. --- fpga/constraints/marked_debug.txt | 62 ++++---- fpga/constraints/marked_debug_spi.txt | 59 ++++---- fpga/constraints/small-debug-uart.xdc | 208 ++++++++++++++++++++++++++ fpga/generator/wally.tcl | 2 +- 4 files changed, 268 insertions(+), 63 deletions(-) create mode 100644 fpga/constraints/small-debug-uart.xdc diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index a5ffb3c83..4ac6b1bc6 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -5,39 +5,29 @@ wally/wallypipelinedcore.sv: logic InstrM lsu/lsu.sv: logic IEUAdrM lsu/lsu.sv: logic MemRWM mmu/hptw.sv: logic SATP_REGW -uncore/uncore.sv: logic SDCCmd -uncore/uncore.sv: logic SDCCLK -uncore/uncore.sv: logic SDCIn -uncore/uncore.sv: logic SDCCS -uncore/spi_apb.sv: logic InterruptPending -uncore/spi_apb.sv: logic TransmitFIFOWriteInc -uncore/spi_apb.sv: logic TransmitFIFOEmpty -uncore/spi_apb.sv: logic TransmitFIFOReadInc -uncore/spi_apb.sv: logic TransmitLoad -uncore/spi_apb.sv: logic ShiftEdge -uncore/spi_apb.sv: logic SampleEdge -uncore/spi_apb.sv: logic ReceiveShiftReg -uncore/spi_apb.sv: logic TransmitReg -uncore/spi_apb.sv: logic ShiftIn -uncore/spi_apb.sv: logic EndOfFrame -uncore/spi_apb.sv: logic TransmitRegLoaded -uncore/spi_apb.sv: logic TransmitData -uncore/spi_apb.sv: logic ReceiveFIFOWriteInc -uncore/spi_apb.sv: logic ReceiveFIFOReadInc -uncore/spi_apb.sv: logic ReceiveShiftRegEndian -uncore/spi_apb.sv: logic ReceiveWatermark -uncore/spi_apb.sv: logic ReceiveReadWatermarkLevel -uncore/spi_apb.sv: logic ReceiveData -uncore/spi_apb.sv: logic ReceiveFIFOFull -uncore/spi_apb.sv: logic ReceiveFIFOEmpty -uncore/spi_controller.sv: logic SCLKenable -uncore/spi_controller.sv: statetype CurrState -uncore/spi_controller.sv: statetype NextState -uncore/spi_controller.sv: logic BitNum -uncore/spi_controller.sv: logic ContinueTransmit -uncore/spi_controller.sv: logic PhaseOneOffset -uncore/spi_controller.sv: logic SPICLK -uncore/spi_fifo.sv: logic rptr -uncore/spi_fifo.sv: logic rptrnext -uncore/spi_fifo.sv: logic raddr -uncore/spi_fifo.sv: logic waddr +uncore/uartPC16550D.sv : logic MCR +uncore/uartPC16550D.sv : logic FCR +uncore/uartPC16550D.sv : logic MSR +uncore/uartPC16550D.sv : logic DTRb +uncore/uartPC16550D.sv : logic INTR +uncore/uartPC16550D.sv : logic RXRDYb +uncore/uartPC16550D.sv : logic TXRDYb +uncore/uartPC16550D.sv : logic RXerrIP +uncore/uartPC16550D.sv : logic IER +uncore/uartPC16550D.sv : logic LSR +uncore/uartPC16550D.sv : logic SCR +uncore/uartPC16550D.sv : statetype txstate +uncore/uartPC16550D.sv : logic RBR +uncore/uartPC16550D.sv : logic rxparityerr +uncore/uartPC16550D.sv : logic LCR +uncore/uartPC16550D.sv : logic intrID +uncore/uartPC16550D.sv : logic rxdataavailintr +uncore/uartPC16550D.sv : logic fifoenabled +uncore/uartPC16550D.sv : logic rxfifoentries +uncore/uartPC16550D.sv : logic txsrfull +uncore/uartPC16550D.sv : logic txhrfull +uncore/uartPC16550D.sv : logic txfifofull +uncore/uartPC16550D.sv : logic txfifotail +uncore/uartPC16550D.sv : logic txfifohead +uncore/uartPC16550D.sv : logic rxfifotriggered +uncore/uartPC16550D.sv : logic rxdataready diff --git a/fpga/constraints/marked_debug_spi.txt b/fpga/constraints/marked_debug_spi.txt index c840f6b99..a5ffb3c83 100644 --- a/fpga/constraints/marked_debug_spi.txt +++ b/fpga/constraints/marked_debug_spi.txt @@ -5,32 +5,39 @@ wally/wallypipelinedcore.sv: logic InstrM lsu/lsu.sv: logic IEUAdrM lsu/lsu.sv: logic MemRWM mmu/hptw.sv: logic SATP_REGW -uncore/spi_apb.sv: logic ShiftIn -uncore/spi_apb.sv: logic ReceiveShiftReg -uncore/spi_apb.sv: logic SCLKenable -uncore/spi_apb.sv: logic SampleEdge -uncore/spi_apb.sv: logic Active -uncore/spi_apb.sv: statetype state -uncore/spi_apb.sv: typedef rsrstatetype -uncore/spi_apb.sv: logic SPICLK -uncore/spi_apb.sv: logic SPIOut -uncore/spi_apb.sv: logic SPICS -uncore/spi_apb.sv: logic SckMode -uncore/spi_apb.sv: logic SckDiv +uncore/uncore.sv: logic SDCCmd +uncore/uncore.sv: logic SDCCLK +uncore/uncore.sv: logic SDCIn +uncore/uncore.sv: logic SDCCS +uncore/spi_apb.sv: logic InterruptPending +uncore/spi_apb.sv: logic TransmitFIFOWriteInc +uncore/spi_apb.sv: logic TransmitFIFOEmpty +uncore/spi_apb.sv: logic TransmitFIFOReadInc +uncore/spi_apb.sv: logic TransmitLoad uncore/spi_apb.sv: logic ShiftEdge -uncore/spi_apb.sv: logic TransmitShiftRegLoadSingleCycle -uncore/spi_apb.sv: logic TransmitShiftReg +uncore/spi_apb.sv: logic SampleEdge +uncore/spi_apb.sv: logic ReceiveShiftReg +uncore/spi_apb.sv: logic TransmitReg +uncore/spi_apb.sv: logic ShiftIn +uncore/spi_apb.sv: logic EndOfFrame +uncore/spi_apb.sv: logic TransmitRegLoaded uncore/spi_apb.sv: logic TransmitData -uncore/spi_apb.sv: logic ReceiveData +uncore/spi_apb.sv: logic ReceiveFIFOWriteInc +uncore/spi_apb.sv: logic ReceiveFIFOReadInc uncore/spi_apb.sv: logic ReceiveShiftRegEndian -uncore/spi_apb.sv: logic TransmitShiftReg -uncore/spi_apb.sv: logic TransmitShift -uncore/spi_apb.sv: logic ReceiveShiftFullDelay -uncore/spi_apb.sv: logic TransmitShiftEmpty -uncore/spi_apb.sv: logic ReceiveFIFOWriteFull -uncore/spi_apb.sv: logic ReceiveFIFOReadIncrement -uncore/spi_apb.sv: logic ReceiveFIFOReadEmpty -uncore/spi_apb.sv: logic TransmitFIFOWriteIncrement -uncore/spi_apb.sv: logic TransmitFIFOReadIncrement -uncore/spi_apb.sv: logic TransmitFIFOWriteFull -uncore/spi_apb.sv: logic TransmitFIFOReadEmpty +uncore/spi_apb.sv: logic ReceiveWatermark +uncore/spi_apb.sv: logic ReceiveReadWatermarkLevel +uncore/spi_apb.sv: logic ReceiveData +uncore/spi_apb.sv: logic ReceiveFIFOFull +uncore/spi_apb.sv: logic ReceiveFIFOEmpty +uncore/spi_controller.sv: logic SCLKenable +uncore/spi_controller.sv: statetype CurrState +uncore/spi_controller.sv: statetype NextState +uncore/spi_controller.sv: logic BitNum +uncore/spi_controller.sv: logic ContinueTransmit +uncore/spi_controller.sv: logic PhaseOneOffset +uncore/spi_controller.sv: logic SPICLK +uncore/spi_fifo.sv: logic rptr +uncore/spi_fifo.sv: logic rptrnext +uncore/spi_fifo.sv: logic raddr +uncore/spi_fifo.sv: logic waddr diff --git a/fpga/constraints/small-debug-uart.xdc b/fpga/constraints/small-debug-uart.xdc new file mode 100644 index 000000000..d2e9e3e34 --- /dev/null +++ b/fpga/constraints/small-debug-uart.xdc @@ -0,0 +1,208 @@ +create_debug_core u_ila_0 ila + + + + +set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +startgroup +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] +endgroup +connect_debug_port u_ila_0/clk [get_nets CPUCLK] + +set_property port_width 33 [get_debug_ports u_ila_0/probe0] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} } ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe1] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe2] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe3] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe4] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsoc/core/lsu/MemRWM[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe5] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe6] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe7] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 5 [get_debug_ports u_ila_0/probe8] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[4]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe9] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe10] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[3]} ]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe11] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] +connect_debug_port u_ila_0/probe11 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/DTRb ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe12] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] +connect_debug_port u_ila_0/probe12 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/INTR ]] + + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe13] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] +connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[3]}]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe14] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] +connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txsrfull}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe15] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] +connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txhrfull}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe16] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] +connect_debug_port u_ila_0/probe16 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RXRDYb ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe17] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] +connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifofull}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe18] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] +connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifoempty}]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe19] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] +connect_debug_port u_ila_0/probe19 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/TXRDYb ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe20] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] +connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RXerrIP} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe21] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] +connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe22] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] +connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe23] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] +connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe24] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] +connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txstate[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txstate[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 11 [get_debug_ports u_ila_0/probe25] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] +connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[7]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[8]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[9]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[10]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe26] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] +connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxparityerr} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe27] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] +connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxstate[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxstate[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe28] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] +connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe29] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] +connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[2]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe30] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] +connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxdataavailintr} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe31] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] +connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/fifoenabled} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe32] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] +connect_debug_port u_ila_0/probe32 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifotriggered} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe33] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] +connect_debug_port u_ila_0/probe33 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe34] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] +connect_debug_port u_ila_0/probe34 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxdataready} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe35] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] +connect_debug_port u_ila_0/probe35 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[3]}]] + + +# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock. +#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk] +connect_debug_port dbg_hub/clk [get_nets CPUCLK] diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 7935b5913..ff18bff1a 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -98,7 +98,7 @@ write_verilog -force -mode funcsim sim/syn-funcsim.v if {$board=="ArtyA7"} { #source ../constraints/small-debug.xdc #source ../constraints/small-debug-rvvi.xdc - #source ../constraints/small-debug-spi.xdc + source ../constraints/small-debug-uart.xdc } else { #source ../constraints/vcu-small-debug.xdc #source ../constraints/small-debug.xdc From 5758ced1ea37753009c92e264487a743d4715ddc Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 22 Nov 2024 17:44:59 -0800 Subject: [PATCH 141/212] Add breker derived config --- config/derivlist.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index a82339cfc..76f09ebf4 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -1432,5 +1432,6 @@ UART_SUPPORTED 0 PLIC_SUPPORTED 0 SPI_SUPPORTED 0 - - +derive breker rv64gc +EXT_MEM_SUPPORTED 1 +EXT_MEM_BASE 64'h90000000 From 311125f4bdbe6e99b6e6b8116a58212bb7d0d85c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 27 Nov 2024 00:13:17 -0800 Subject: [PATCH 142/212] WIP Breker --- bin/regression-wally | 4 +- bin/wsim | 5 + sim/questa/wally.do | 39 +++- site-setup.sh | 1 + testbench/testbench.sv | 11 + testbench/trek_files/Makefile | 12 + testbench/trek_files/breker-setup.sh | 5 + testbench/trek_files/customer.yaml | 27 +++ testbench/trek_files/platform.yaml | 258 +++++++++++++++++++++ testbench/trek_files/trek_user_backdoor.sv | 91 ++++++++ tests/breker/Makefile | 56 +++++ tests/breker/constraints/atomics.yaml | 73 ++++++ tests/breker/constraints/coherency.yaml | 72 ++++++ tests/breker/constraints/dekker.yaml | 73 ++++++ tests/breker/constraints/hello.yaml | 58 +++++ tests/breker/constraints/microloops.yaml | 72 ++++++ tests/breker/constraints/mmu.yaml | 72 ++++++ tests/breker/constraints/riscv.yaml | 72 ++++++ tests/breker/constraints/test.yaml | 72 ++++++ tests/breker/constraints/workload.yaml | 72 ++++++ 20 files changed, 1134 insertions(+), 11 deletions(-) create mode 100644 testbench/trek_files/Makefile create mode 100644 testbench/trek_files/breker-setup.sh create mode 100644 testbench/trek_files/customer.yaml create mode 100644 testbench/trek_files/platform.yaml create mode 100644 testbench/trek_files/trek_user_backdoor.sv create mode 100644 tests/breker/Makefile create mode 100644 tests/breker/constraints/atomics.yaml create mode 100644 tests/breker/constraints/coherency.yaml create mode 100644 tests/breker/constraints/dekker.yaml create mode 100644 tests/breker/constraints/hello.yaml create mode 100644 tests/breker/constraints/microloops.yaml create mode 100644 tests/breker/constraints/mmu.yaml create mode 100644 tests/breker/constraints/riscv.yaml create mode 100644 tests/breker/constraints/test.yaml create mode 100644 tests/breker/constraints/workload.yaml diff --git a/bin/regression-wally b/bin/regression-wally index 09bd1fa9c..800d0dd82 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -397,6 +397,7 @@ parser.add_argument("--nightly", help="Run large nightly regression", action="st parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true") parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true") parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true") # Currently not used +parser.add_argument("--breker", help="Run Breker tests", action="store_true") parser.add_argument("--dryrun", help="Print commands invoked to console without running regression", action="store_true") args = parser.parse_args() @@ -441,7 +442,8 @@ elif (args.fcov): # run tests in lockstep in functional coverage mode addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim) addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv32/", "rv32gc", coveragesim) addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim) - +# elif (args.breker): +# addLockstepTestsByDir(WALLY+"/tests/breker/work", "breker", coveragesim, 0) else: for sim in sims: if (not (args.buildroot and sim == lockstepsim)): # skip short buildroot sim if running long one diff --git a/bin/wsim b/bin/wsim index 91f8e30ab..a6bb89b72 100755 --- a/bin/wsim +++ b/bin/wsim @@ -50,6 +50,9 @@ def validateArgs(args): elif (args.tb == "testbench_fp" and args.sim != "questa"): print("Error: testbench_fp presently only supported by Questa, not VCS or Verilator, because of a touchy testbench") exit(1) + elif ("breker" in args.elf or "breker" in args.testsuite) and args.sim != "questa": + print("Error: Breker tests currently only supported by Questa") + exit(1) def elfFileCheck(args): ElfFile = "" @@ -90,6 +93,8 @@ def prepSim(args, ElfFile): flags += " --ccov" if args.fcov: flags += " --fcov" + if "breker" in ElfFile: + flags += " --breker" prefix, suffix = lockstepSetup(args) flags += suffix return flags, prefix diff --git a/sim/questa/wally.do b/sim/questa/wally.do index f42bf4930..2a0fcb052 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -37,6 +37,7 @@ onerror {quit -f} # Initialize variables set CFG ${1} set TESTSUITE ${2} +set TESTSUITE_NO_ELF [file rootname ${TESTSUITE}] set TESTBENCH ${3} set WKDIR wkdir/${CFG}_${TESTSUITE} set WALLY $::env(WALLY) @@ -62,11 +63,17 @@ set CoverageVsimArg "" set FunctCoverage 0 set FCvlog "" -set FCvopt "" +set FCvsim "" set FCdefineCOVER_EXTS {} +set breker 0 +set brekervlog "" +set brekervopt "" +set brekervsim "" + set lockstep 0 set lockstepvlog "" + set SVLib "" set GUI 0 @@ -107,13 +114,11 @@ if {[lcheck lst "--ccov"]} { if {[lcheck lst "--fcov"]} { set FunctCoverage 1 # COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but no longer affects tests - set FCvlog "+define+INCLUDE_TRACE2COV \ + set FCvlog "+define+INCLUDE_TRACE2COV \ +define+IDV_INCLUDE_TRACE2COV \ +define+COVER_BASE_RV32I \ - +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source \ - " - set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1" - + +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source" + set FCvsim "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1" } # if --lockstep or --fcov found set flag and remove from list @@ -124,7 +129,20 @@ if {[lcheck lst "--lockstep"] || $FunctCoverage == 1} { +incdir+${IMPERAS_HOME}/ImpProprietary/include/host \ ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/*.sv \ ${IMPERAS_HOME}/ImpProprietary/source/host/idv/*.sv" - set SVLib "-sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model" + set SVLib " -sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model " +} + +# if --breker found set flag and remove from list +if {[lcheck lst "--breker"]} { + set breker 1 + set BREKER_HOME $::env(BREKER_HOME) + set brekervlog "+define+USE_TREK_DV \ + +incdir+${WALLY}/testbench/trek_files \ + ${WALLY}/testbench/trek_files/uvm_output/trek_uvm_pkg.sv" + set brekervopt "${WKDIR}.trek_uvm" + # may need to change this path + set brekervsim "+TREK_TBX_FILE=${WALLY}/tests/breker/work/${TESTSUITE_NO_ELF}/${TESTSUITE_NO_ELF}.tbx" + append SVLib " -sv_lib ${BREKER_HOME}/linux64/lib/libtrek " } # Set PlusArgs passed using the --args flag @@ -151,6 +169,7 @@ if {$DEBUG > 0} { echo "ccov = $ccov" echo "lockstep = $lockstep" echo "FunctCoverage = $FunctCoverage" + echo "Breker = $breker" echo "remaining list = $lst" echo "Extra +args = $PlusArgs" echo "Extra -args = $ExpandedParamArgs" @@ -162,13 +181,13 @@ if {$DEBUG > 0} { # because vsim will run vopt set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv32_priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}" set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv" -vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 +vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} {*}${brekervlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} {*}${ExpandedParamArgs} -o testbenchopt ${CoverageVoptArg} +vopt $accFlag ${WKDIR}.${TESTBENCH} ${brekervopt} -work ${WKDIR} {*}${ExpandedParamArgs} -o testbenchopt ${CoverageVoptArg} -vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} {*}${PlusArgs} -fatal 7 {*}${SVLib} {*}${FCvopt} -suppress 3829 ${CoverageVsimArg} +vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} {*}${PlusArgs} -fatal 7 {*}${SVLib} {*}${FCvsim} {*}${brekervsim} -suppress 3829 ${CoverageVsimArg} # power add generates the logging necessary for saif generation. # power add -r /dut/core/* diff --git a/site-setup.sh b/site-setup.sh index 4699ff348..81f17fff2 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -15,6 +15,7 @@ export IMPERASD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change thi export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys DC, excluding bin export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, excluding bin +export BREKER_HOME=/cad/breker/trek5-2.1.10b-GCC6_el7 # Change this for your path to Breker Trek # Tools # Questa and Synopsys diff --git a/testbench/testbench.sv b/testbench/testbench.sv index c777fdf3f..312467a33 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -45,6 +45,13 @@ module testbench; parameter D_CACHE_ADDR_LOGGER=0; parameter RVVI_SYNTH_SUPPORTED=0; + `ifdef USE_TREK_DV + event trek_start; + always @(testbench.trek_start) begin + trek_uvm_pkg::trek_uvm_events::do_backdoor_init(); + end + `endif + `ifdef USE_IMPERAS_DV import idvPkg::*; import rvviApiPkg::*; @@ -518,6 +525,10 @@ module testbench; end else begin $fclose(uncoreMemFile); $readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.ram.RAM); + `ifdef USE_TREK_DV + -> trek_start; + $display("starting Trek...."); + `endif end end if (TEST == "embench") $display("Read memfile %s", memfilename); diff --git a/testbench/trek_files/Makefile b/testbench/trek_files/Makefile new file mode 100644 index 000000000..02c9b6f56 --- /dev/null +++ b/testbench/trek_files/Makefile @@ -0,0 +1,12 @@ +TREKFILES := $(WALLY)/testbench/trek_files +PLATFORM_YAML := $(TREKFILES)/platform.yaml +TREKSVIP_YAML := $(BREKER_HOME)/examples/tutorials/svip/treksvip/yaml/treksvip.yaml +TREKEXE_FLAGS += --seed 0x # free (0x) or lock (0x1) the seed used for test generation +TREKSVIP = source $(TREKFILES)/breker-setup.sh && treksvip -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) $(TREKEXE_FLAGS) + +uvm_output: + rm -rf uvm_output + $(TREKSVIP) -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) --uvm_output=uvm_output + +clean: + rm -rf uvm_output diff --git a/testbench/trek_files/breker-setup.sh b/testbench/trek_files/breker-setup.sh new file mode 100644 index 000000000..9b651eeef --- /dev/null +++ b/testbench/trek_files/breker-setup.sh @@ -0,0 +1,5 @@ +#!/bin/bash +export BREKER_ARCH=${BREKER_HOME}/linux64 +export PATH=${BREKER_HOME}/bin:${BREKER_HOME}/examples/tutorials/apps/coherency/bin:${PATH} +export LD_LIBRARY_PATH=".:${BREKER_ARCH}/lib:${BREKER_HOME}/opensrc/gcc/lib:${BREKER_HOME}/opensrc/gcc/lib64":${LD_LIBRARY_PATH} +export LIBRARY_PATH=/usr/lib/x86_64-linux-gnu/:$LIBRARY_PATH diff --git a/testbench/trek_files/customer.yaml b/testbench/trek_files/customer.yaml new file mode 100644 index 000000000..e06733797 --- /dev/null +++ b/testbench/trek_files/customer.yaml @@ -0,0 +1,27 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 5 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + # uncomment the `weights:` line below if any entries under `weights:` need to be enabled + # weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + + diff --git a/testbench/trek_files/platform.yaml b/testbench/trek_files/platform.yaml new file mode 100644 index 000000000..16b1da612 --- /dev/null +++ b/testbench/trek_files/platform.yaml @@ -0,0 +1,258 @@ +trek: + platform_config: + doc: >- + Testbench platform specific configuration. + processors: + doc: >- + Information about available processors. + processor_count: + value: 1 + doc: >- + How many processors can be used by the generated test case + sw_threads_per_processor: + value: 2 + doc: >- + How many software threads to put on each processor + tlm_generic_ports: + doc: >- + Information about available tlm_generic_payload ports + port_count: + value: 0 + doc: >- + How many tlm ports to use for memory operations + threads_per_port: + value: 4 + doc: >- + How many threads to put on each tlm port + debug: + value: 1 + doc: >- + Turn on for verbose tlm port messages + memories: + doc: >- + Information about memory regions that can be used by the generated test case. + defaults: + doc: >- + Default values for all memories + natural_alignment: + value: 1 + doc: >- + Should all memory addresses be naturally aligned (up to 8 byte alignment) + init_type: + value: frontdoor + doc: >- + Strategy to use for memory initialization. + Options are: + - static + - backdoor + - frontdoor + memory: + doc: >- + Define a memory region. + Multiple memory regions may be defined in this section. + name: + value: ddr0 + doc: >- + Name of the memory region + base: + value: 0x82000000 + doc: >- + Base address of memory region. + Ignored for `static` initialized memory + size: + value: 0x100000 + doc: >- + Size of memory region in bytes. + init_type: + value: backdoor #frontdoor + doc: >- + Strategy to use for memory initialization. + Options are: + - static + - backdoor + - frontdoor + caches: + doc: >- + parameters related to cache architecture + cache_line_size: + value: 64 + doc: >- + Size of a cache line in bytes + llc_cache_size: + value: 0x200000 + doc: >- + size of last level cache in bytes + llc_cache_ways: + value: 8 + doc: >- + number of ways in the last level cache + mailbox: + doc: >- + Configure memory mailbox usage + type: + value: single + doc: >- + Configure mailbox type. + Options are: + - single: for use by TrekBox with backdoor access + - queue: for use in post-silicon post-process flow + single: + doc: >- + Detail settings when mailbox type is `single` + init_type: + value: static + doc: >- + Strategy to use for mailbox memory initialization. + Options are: + - static + - backdoor + - frontdoor + c2t_base: + value: 0x1000 + doc: >- + Fixed base address of C to trekbox mailbox region. + Allow 64 bytes per processor. + Used for init_type of `backdoor` and `frontdoor` only. + t2c_base: + value: 0x2000 + doc: >- + Fixed base address of trekbox to C mailbox region. + Allow 64 bytes per processor. + Used for init_type of `backdoor` and `frontdoor` only. + cacheable: + value: 1 + doc: >- + Set this parameter to 1 to do a cache flush after every mailbox + write. + queue: + doc: >- + Detail settings when mailbox type is `queue` + length: + value: 1000 + doc: >- + Max number of messages that can be stored in the queue mailbox. + Longer tests may need a larger queue. + debug: + value: 0 + doc: >- + If this flag is set to 1, messages will be printed directly to the + console instead of being queued in memory. + stdio: + doc: >- + Is the standard library available for use by the generated test. + available: + value: 0 + doc: >- + Set this value to 0 of the library is not available in + your system. + use_lock: + value: 1 + doc: >- + Calls to console print messages will be mutex locked unless + this flag is set to 0. + header: + doc: >- + Verbatim code that will be put into the header section of the test. + value: |- + + declaration: + doc: >- + Verbatim code that will be put into the declaration section of the test. + value: |- + int main(void) + { + return trek_main(); + } + + mmu: # Trek can generate code to program page/translation tables + # that you MAY want to use with your SDV generated C files. + # Here, you have some control over that process. + + va_bits: 39 # How many bits are used for virtual addresses + # + # For aarch64, the value here is used to determine the + # "initial lookup level" (as detailed in Table D5-13). + # This must correlate to TCR_EL3.T0SZ! + # + # For riscv64, only 39, 48, and 57 are supported + # corresponding to "Sv39", "Sv48", and "Sv57". + # + # default: 39 [from T0SZ=64-39=25(0x19)] + + memory_map: # A *MAP* of all memory regions, excluding the + # memory_resources in your platformConfig.h file. + # + # Each map entry should be a unique name. + # + # Mandatory submap pairs: + # normal: *true*/false (false = "device"/"io" memory) + # begin: starting address + # end: ending address + # + # Optional submap pairs: + # readable: *true*/false + # writeable: *true*/false + # executable: true/*false* + # cacheable: *true*/false (*false* for device) + # share_type (aarch64 only): *inner-shareable*, + # outer-shareable, non-shareable + # + # Note that memory_resources will use all defaults. + # + # Note that "normal: false" (device-memory) change defaults + # to "cacheable = false", and on arch64 it implies + # share_type = non-shareable, and alloc_type = no-allocate + + UART0: + type: device + begin: 0x10000000 + end: 0x10000fff + + code: + type: normal + begin: 0x80000000 + end: 0x807fffff + executable: true + + stack: + type: normal + begin: 0x87000000 + end: 0x87ffffff + + + aarch64: # Customizations that are only valid for aarch64. + + TCR_EL3: 0x80923519 # Should Trek to program the TCR_TL3 register? If + # so, put the value here. If not, comment out + # this option. + # NOTE: T0SZ should correlate to va_bits above! + # default: -no default- + + allocate_type: read-write-allocate # Default allocate_type. + # read-allocate, write-allocate, + # *read-write-allocate*, no-allocate + + cache_type: write-back-nontransient # non-cacheable, + # write-through-transient, + # write-back-transient, + # write-through-non-transient, + # *write-back-non-transient* + + device_type: nGnRnE # *nGnRnE*, nGnRE, nGRE, GRE + + share_type: inner-shareable # non-shareable + # inner-shareable + # outer-shareable + + riscv64: # Customizations that are only valid for riscv64. + + Svnapot: false # If standard extension "Svnapot" is implemented, and + # when you are using Sv39, you might set this to "true" + # to allow PTE bit[63] "N" to be set when appropriate. + # default: false + + Svpbmt: true # If standard extension "Svpbmt" is implemented, and + # when you are using Sv39, you might set this to "true" + # to allow cacheable/device information to flow into + # bits[62:61] "PBMT" as appropriate. + # default: false diff --git a/testbench/trek_files/trek_user_backdoor.sv b/testbench/trek_files/trek_user_backdoor.sv new file mode 100644 index 000000000..342ade7b9 --- /dev/null +++ b/testbench/trek_files/trek_user_backdoor.sv @@ -0,0 +1,91 @@ +/// custom routines defined for the platform + +// Design parameters, used in the code below and custom to this design! +//`define RAM_PATH soc_top.soc_instance.i_sram_subsystem.i_shared_ram +//sim:/testbench/dut/uncore/uncore/ram/ram/memory/RAM +//`define RAM_PATH testbench.dut.uncore.uncore.ram.ram.memory.RAM +//`define RAM_PATH testbench.dut.uncore.uncore.ram.ram.memory +`define RAM_PATH testbench.dut.uncoregen.uncore.ram.ram.memory.ram +//`define RAM_BASE_ADDR 32'h80000000 +`define RAM_BASE_ADDR testbench.P.UNCORE_RAM_BASE + +// These two routines are specific to a particular design. They are used +// to read and write to the "mailbox" locations, to synchronize behaviors +// between C code on the processors with activity performed in UVM (and +// among activities in UVM). +// +// Every design will be different. Here we just have a simple Verilog +// array that we can read and write. +// +function automatic void trek_backdoor_read64( + input longint unsigned address, + output longint unsigned data, + input int unsigned debug = 1); + + //bit [15:0] offset = (address-`RAM_BASE_ADDR) >> 2; + bit [31:0] offset = ((address-`RAM_BASE_ADDR)/(testbench.P.XLEN/8)); + if (address[1:0] != 2'b00) begin: misaligned + $display("%t trek_backdoor_read64: Misaligned address", $time); + $finish(); + end + + //data[63:32] = `RAM_PATH[offset + 0]; + //data[31: 0] = `RAM_PATH[offset + 1]; + data[63:0] = `RAM_PATH.RAM[offset + 0]; +if (data != 0) + $display("%t trek_backdoor_read64: Read 64'h%016h from address 64'h%016h", + $time, data, address); +endfunction: trek_backdoor_read64 + + +function automatic void trek_backdoor_write64( + input longint unsigned address, + input longint unsigned data, + input int unsigned debug = 1); + + //bit [15:0] offset = (address-`RAM_BASE_ADDR) >> 2; + bit [31:0] offset = ((address-`RAM_BASE_ADDR)/(testbench.P.XLEN/8)); + + if (address[1:0] != 2'b00) begin: misaligned + $display("%t trek_backdoor_write64: Misaligned address", $time); + $finish(); + end + //`RAM_PATH[offset + 0] = data[63:32]; + //`RAM_PATH[offset + 1] = data[31: 0]; + `RAM_PATH.RAM[offset + 0] = data[63:0]; + //$display("%t trek_backdoor_write64: Wrote 64'h%016h to address 64'h%016h", + //$time, data, address); +endfunction: trek_backdoor_write64 + + +// For performance, we want to read mailboxes ONLY when they're written to! +// (This is very important on emulators!) +// +// Here we trigger a signal when a memory write happens to the range of +// addresses where the mailboxes are. +// +// A clock later, we go poll all the mailboxes (using the "backdoor_read" +// method above. +// +// Each design will be different, depending on where you are able to snoop +// for writes and how long it takes a write to propagate from that point +// to the place where the backdoor read will find it. + +bit trek_c2t_mbox_event; +bit trek_is_event_addr; + +//assign trek_is_event_addr = +// ((((`RAM_PATH.ad << 2) + `RAM_BASE_ADDR) >= `TREK_C2T_MBOX_BASE) && +// (((`RAM_PATH.ad << 2) + `RAM_BASE_ADDR) < `TREK_C2T_MBOX_LIMIT)); +// +//always_ff @(posedge `RAM_PATH.clk) begin: trigger_reading_of_mailboxes +// trek_c2t_mbox_event <= (trek_is_event_addr && +// (`RAM_PATH.n_cs == 1'b0) && +// (`RAM_PATH.n_we == 1'b0)); +//end + +// Design specifc: one stage delayed so write has a time to settle +//always @(posedge trek_c2t_mbox_event) begin: read_all_mailboxes +always @(posedge testbench.clk) begin: read_all_mailboxes + trek_poll_mbox(); +end diff --git a/tests/breker/Makefile b/tests/breker/Makefile new file mode 100644 index 000000000..bd21b8b22 --- /dev/null +++ b/tests/breker/Makefile @@ -0,0 +1,56 @@ +shell := /bin/bash + +# Breker/Trek paths and variables +TESTDIR := $(WALLY)/tests/breker/work +TREKFILES := $(WALLY)/testbench/trek_files +CONSTRAINTS_DIR := $(WALLY)/tests/breker/constraints +PLATFORM_YAML := $(TREKFILES)/platform.yaml +CUSTOMER_YAML := $(TREKFILES)/customer.yaml +TREKSVIP_YAML := $(BREKER_HOME)/examples/tutorials/svip/treksvip/yaml/treksvip.yaml +CONSTRAINT_FILES := $(shell find $(CONSTRAINTS_DIR) -type f) +TREKEXE_FLAGS += --seed 0x # free (0x) or lock (0x1) the seed used for test generation +TREKSVIP = source $(TREKFILES)/breker-setup.sh && treksvip -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) $(TREKEXE_FLAGS) + +# Compilation paths and variables +MARCH :=-march=rv64gc_zcb_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh_svinval +MABI :=-mabi=lp64d +LINKER := $(WALLY)/tests/custom/linker8000-0000.x +LINK_FLAGS := -nostartfiles +CFLAGS := -Wa,-alhs -Wa,-L -mcmodel=medany -Og -DSINGLE_CPU +CRT0_DIR := $(WALLY)/tests/custom/crt0 +WIDTH := 64 + +# Find all constraint files and generate tests for each one +TESTS = $(patsubst $(CONSTRAINTS_DIR)/%.yaml,$(TESTDIR)/%,$(CONSTRAINT_FILES)) +.PHONY: all clean +all: $(TESTS) + +# Generate c tests +$(TESTDIR)/%: $(CONSTRAINTS_DIR)/%.yaml | $(TESTDIR) + $(TREKSVIP) -p $< -p $(CUSTOMER_YAML) -o $@/$* -e pss_top.entry + $(MAKE) $@/$*.elf.memfile + +# Compile c code +.PRECIOUS: %.elf +%.elf: %.c $(CRT0_DIR)/libcrt0.a + riscv64-unknown-elf-gcc $(MARCH) $(MABI) $(CFLAGS) $(LINK_FLAGS) -g -o $@ $< -L$(CRT0_DIR) -lcrt0 -T $(LINKER) > /dev/null + +# Convert elf to hex +%.elf.memfile: %.elf + riscv64-unknown-elf-objdump -D $< > $<.objdump + riscv64-unknown-elf-elf2hex --bit-width $(WIDTH) --input $< --output $@ + extractFunctionRadix.sh $<.objdump + +# View the model graph TODO: What does this do? Move to another makefile? +%.view_graph:% + $(TREKSVIP) -p ../tests/test_$^.yaml -p $(CUSTOMER_YAML) -t pss_top.entry + +# Library needed for C code +$(CRT0_DIR)/libcrt0.a: + make -C $(CRT0_DIR) + +$(TESTDIR): + mkdir -p $(TESTDIR) + +clean: + rm -rf $(TESTS) diff --git a/tests/breker/constraints/atomics.yaml b/tests/breker/constraints/atomics.yaml new file mode 100644 index 000000000..c505b957d --- /dev/null +++ b/tests/breker/constraints/atomics.yaml @@ -0,0 +1,73 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + # pss_top.soc: 0 + pss_top.dekker.dekkerTest: 0 + # pss_top.atomics.atomicsTest: 0 + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + pss_top.coherency: 0 + + # turn off coherency memory workload tests + # pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + # pss_top.readOnly.entry: 0 + # pss_top.writeOnly.entry: 0 + # pss_top.writeRead.entry: 0 + # pss_top.readWrite.entry: 0 + # pss_top.moesiStates.entry: 0 + # pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + # pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/coherency.yaml b/tests/breker/constraints/coherency.yaml new file mode 100644 index 000000000..62908c90c --- /dev/null +++ b/tests/breker/constraints/coherency.yaml @@ -0,0 +1,72 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + # pss_top.soc: 0 + + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + # pss_top.coherency: 0 + + # turn off coherency memory workload tests + pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + # pss_top.readOnly.entry: 0 + # pss_top.writeOnly.entry: 0 + # pss_top.writeRead.entry: 0 + # pss_top.readWrite.entry: 0 + # pss_top.moesiStates.entry: 0 + # pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/dekker.yaml b/tests/breker/constraints/dekker.yaml new file mode 100644 index 000000000..052c7e02d --- /dev/null +++ b/tests/breker/constraints/dekker.yaml @@ -0,0 +1,73 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + # pss_top.soc: 0 + # pss_top.dekker.dekkerTest: 0 + pss_top.atomics.atomicsTest: 0 + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + pss_top.coherency: 0 + + # turn off coherency memory workload tests + # pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + # pss_top.readOnly.entry: 0 + # pss_top.writeOnly.entry: 0 + # pss_top.writeRead.entry: 0 + # pss_top.readWrite.entry: 0 + # pss_top.moesiStates.entry: 0 + # pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + # pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/hello.yaml b/tests/breker/constraints/hello.yaml new file mode 100644 index 000000000..94b30664d --- /dev/null +++ b/tests/breker/constraints/hello.yaml @@ -0,0 +1,58 @@ +# Constraint file to generate simple hello world test that checks the +# initialized values for a few memory locations. + +# This constraint file disable all features other than the +trek: + svip: + global: + scenarios: + scenario_count: + # reduce number of scenarios + value: 2 + memory_allocation: + memory_sets: + block_size: + # force 4 byte operation + min: 4 + max: 4 + block_count: + # force a single memory block + min: 1 + max: 1 + riscv: + extensions: + # disable hypervisor extension + # if your system does not support this feature + h_hypervisor: + value: 0 + coherency: + cacheline_states: + scenario_length: + # minimize scenario length + min: 1 + max: 1 + weights: + + # turn of SoC level Dekker and Atomics tests + pss_top.soc: 0 + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off memory workload tests + # pss_top.workload.entry: 0 + + # turn of various cache state tests + pss_top.readOnly.entry: 0 + pss_top.writeOnly.entry: 0 + pss_top.writeRead.entry: 0 + pss_top.readWrite.entry: 0 + pss_top.moesiStates.entry: 0 + pss_top.tilelinkStates.entry: 0 + + # turn of micro loop feature + pss_top.microLoops.microLoopScn: 0 + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + diff --git a/tests/breker/constraints/microloops.yaml b/tests/breker/constraints/microloops.yaml new file mode 100644 index 000000000..b8502b0f6 --- /dev/null +++ b/tests/breker/constraints/microloops.yaml @@ -0,0 +1,72 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + pss_top.soc: 0 + + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + # pss_top.coherency: 0 + + # turn off coherency memory workload tests + pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + pss_top.readOnly.entry: 0 + pss_top.writeOnly.entry: 0 + pss_top.writeRead.entry: 0 + pss_top.readWrite.entry: 0 + pss_top.moesiStates.entry: 0 + pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + # pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/mmu.yaml b/tests/breker/constraints/mmu.yaml new file mode 100644 index 000000000..2b2dbac44 --- /dev/null +++ b/tests/breker/constraints/mmu.yaml @@ -0,0 +1,72 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + # pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + pss_top.soc: 0 + + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + pss_top.coherency: 0 + + # turn off coherency memory workload tests + # pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + # pss_top.readOnly.entry: 0 + # pss_top.writeOnly.entry: 0 + # pss_top.writeRead.entry: 0 + # pss_top.readWrite.entry: 0 + # pss_top.moesiStates.entry: 0 + # pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + # pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/riscv.yaml b/tests/breker/constraints/riscv.yaml new file mode 100644 index 000000000..7e8a6c0d1 --- /dev/null +++ b/tests/breker/constraints/riscv.yaml @@ -0,0 +1,72 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + pss_top.soc: 0 + + + # turn off RV64 opcode tests + # pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + # pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + pss_top.coherency: 0 + + # turn off coherency memory workload tests + # pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + # pss_top.readOnly.entry: 0 + # pss_top.writeOnly.entry: 0 + # pss_top.writeRead.entry: 0 + # pss_top.readWrite.entry: 0 + # pss_top.moesiStates.entry: 0 + # pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + # pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/test.yaml b/tests/breker/constraints/test.yaml new file mode 100644 index 000000000..fdf3e294b --- /dev/null +++ b/tests/breker/constraints/test.yaml @@ -0,0 +1,72 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + # weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + # pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + # pss_top.soc: 0 + + + # turn off RV64 opcode tests + # pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + # pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + # pss_top.coherency: 0 + + # turn off coherency memory workload tests + # pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + # pss_top.readOnly.entry: 0 + # pss_top.writeOnly.entry: 0 + # pss_top.writeRead.entry: 0 + # pss_top.readWrite.entry: 0 + # pss_top.moesiStates.entry: 0 + # pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + # pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/workload.yaml b/tests/breker/constraints/workload.yaml new file mode 100644 index 000000000..61f641ea5 --- /dev/null +++ b/tests/breker/constraints/workload.yaml @@ -0,0 +1,72 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + pss_top.soc: 0 + + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + # pss_top.coherency: 0 + + # turn off coherency memory workload tests + # pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + pss_top.readOnly.entry: 0 + pss_top.writeOnly.entry: 0 + pss_top.writeRead.entry: 0 + pss_top.readWrite.entry: 0 + pss_top.moesiStates.entry: 0 + pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + pss_top.microLoops.microLoopScn: 0 From 68205b844dc8aa3d9deaf898ea3bebc6990557b4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 2 Dec 2024 13:07:54 -0800 Subject: [PATCH 143/212] Update Breker platform.yaml and test compilation --- .gitignore | 1 + Makefile | 4 ++++ bin/regression-wally | 16 ++++++++++------ bin/wsim | 4 +++- testbench/trek_files/Makefile | 5 +++-- testbench/trek_files/platform.yaml | 6 +++--- 6 files changed, 24 insertions(+), 12 deletions(-) diff --git a/.gitignore b/.gitignore index 9a0f35cc1..41086d3b4 100644 --- a/.gitignore +++ b/.gitignore @@ -33,6 +33,7 @@ tests/fp/combined_IF_vectors/IF_vectors/*.tv tests/custom/*/*/ tests/custom/*/*/*.memfile sim/tests/riscvdv +testbench/trek_files/uvm_output # Linux linux/buildroot diff --git a/Makefile b/Makefile index 52513a812..f52fd943d 100644 --- a/Makefile +++ b/Makefile @@ -39,6 +39,10 @@ coverage: cvw-arch-verif: $(MAKE) -C ${WALLY}/addins/cvw-arch-verif +breker: + $(MAKE) -C ${WALLY}/testbench/trek_files + $(MAKE) -C ${WALLY}/tests/breker + clean: $(MAKE) clean -C sim $(MAKE) clean -C ${WALLY}/tests/fp diff --git a/bin/regression-wally b/bin/regression-wally index 800d0dd82..e119422b1 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -291,7 +291,7 @@ def addTests(tests, sim): configs.append(tc) -def addTestsByDir(dir, config, sim, lockstepMode=0): +def addTestsByDir(dir, config, sim, lockstepMode=0, brekerMode=0): if os.path.isdir(dir): sim_logdir = WALLY+ "/sim/" + sim + "/logs/" if coverStr == "--fcov": # use --fcov in place of --lockstep @@ -312,6 +312,10 @@ def addTestsByDir(dir, config, sim, lockstepMode=0): cmdPrefix="wsim --lockstep --sim " + sim + " " + config gs="Mismatches : 0" fileEnd = ".elf" + elif brekerMode: + cmdPrefix="wsim --sim " + sim + " " + config + gs="# trek: info: summary: Test PASSED" + fileEnd = ".elf" else: cmdPrefix="wsim --sim " + sim + " " + config gs="Single Elf file tests are not signatured verified." @@ -442,8 +446,8 @@ elif (args.fcov): # run tests in lockstep in functional coverage mode addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim) addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv32/", "rv32gc", coveragesim) addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim) -# elif (args.breker): -# addLockstepTestsByDir(WALLY+"/tests/breker/work", "breker", coveragesim, 0) +elif (args.breker): + addTestsByDir(WALLY+"/tests/breker/work", "breker", "questa", brekerMode=1) else: for sim in sims: if (not (args.buildroot and sim == lockstepsim)): # skip short buildroot sim if running long one @@ -454,9 +458,9 @@ else: # run derivative configurations and lockstep tests in nightly regression if (args.nightly): - addTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, 1) - addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, 1) - addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, 1) + addTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, lockstepMode=1) + addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, lockstepMode=1) + addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, lockstepMode=1) addTests(derivconfigtests, defaultsim) # addTests(bpredtests, defaultsim) # This is currently broken in regression due to something related to the new wsim script. diff --git a/bin/wsim b/bin/wsim index a6bb89b72..075d473b2 100755 --- a/bin/wsim +++ b/bin/wsim @@ -67,7 +67,9 @@ def elfFileCheck(args): # extract the elf name from the path to be the test suite fields = args.testsuite.rsplit('/', 3) # if the name is just ref.elf in a deep path (riscv-arch-test/wally-riscv-arch-test), then use the directory name as the test suite to make it unique; otherwise work directory will have duplicates. - if (len(fields) > 3): + if ("breker" in args.testsuite): + args.testsuite = fields[-1] + elif (len(fields) > 3): if (fields[2] == "ref"): args.testsuite = f"{fields[1]}_{fields[3]}" else: diff --git a/testbench/trek_files/Makefile b/testbench/trek_files/Makefile index 02c9b6f56..34409e0ae 100644 --- a/testbench/trek_files/Makefile +++ b/testbench/trek_files/Makefile @@ -4,8 +4,9 @@ TREKSVIP_YAML := $(BREKER_HOME)/examples/tutorials/svip/treksvip/yaml/treksvi TREKEXE_FLAGS += --seed 0x # free (0x) or lock (0x1) the seed used for test generation TREKSVIP = source $(TREKFILES)/breker-setup.sh && treksvip -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) $(TREKEXE_FLAGS) -uvm_output: - rm -rf uvm_output +uvm_output: uvm_output/trek_uvm.sv + +uvm_output/trek_uvm.sv: $(PLATFORM_YAML) $(TREKSVIP_YAML) $(TREKSVIP) -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) --uvm_output=uvm_output clean: diff --git a/testbench/trek_files/platform.yaml b/testbench/trek_files/platform.yaml index 16b1da612..376a25857 100644 --- a/testbench/trek_files/platform.yaml +++ b/testbench/trek_files/platform.yaml @@ -100,7 +100,7 @@ trek: doc: >- Detail settings when mailbox type is `single` init_type: - value: static + value: backdoor #static doc: >- Strategy to use for mailbox memory initialization. Options are: @@ -108,13 +108,13 @@ trek: - backdoor - frontdoor c2t_base: - value: 0x1000 + value: 0x83000000 doc: >- Fixed base address of C to trekbox mailbox region. Allow 64 bytes per processor. Used for init_type of `backdoor` and `frontdoor` only. t2c_base: - value: 0x2000 + value: 0x83001000 doc: >- Fixed base address of trekbox to C mailbox region. Allow 64 bytes per processor. From 78e11ed9f3cbe1f2fe0121ad3462bfc3a7da0dee Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 2 Dec 2024 15:24:46 -0600 Subject: [PATCH 144/212] Remove old unused file. --- fpga/src/axi_sdc_controller.v | 669 ---------------------------------- 1 file changed, 669 deletions(-) delete mode 100644 fpga/src/axi_sdc_controller.v diff --git a/fpga/src/axi_sdc_controller.v b/fpga/src/axi_sdc_controller.v deleted file mode 100644 index c32a6a783..000000000 --- a/fpga/src/axi_sdc_controller.v +++ /dev/null @@ -1,669 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2013-2022 Authors //// -//// //// -//// Based on original work by //// -//// Adam Edvardsson (adam.edvardsson@orsoc.se) //// -//// //// -//// Copyright (C) 2009 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from https://www.gnu.org/licenses/ //// -//// //// -////////////////////////////////////////////////////////////////////// - -module sdc_controller #( - parameter dma_addr_bits = 32, - parameter fifo_addr_bits = 7, - parameter sdio_card_detect_level = 1, - parameter voltage_controll_reg = 3300, - parameter capabilies_reg = 16'b0000_0000_0000_0011 -) ( - input wire async_resetn, - - (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK" *) - (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF M_AXI:S_AXI_LITE, FREQ_HZ 100000000" *) - input wire clock, - - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR" *) - (* X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32" *) - input wire [15:0] s_axi_awaddr, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *) - input wire s_axi_awvalid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *) - output wire s_axi_awready, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *) - input wire [31:0] s_axi_wdata, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *) - input wire s_axi_wvalid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *) - output wire s_axi_wready, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *) - output reg [1:0] s_axi_bresp, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *) - output reg s_axi_bvalid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *) - input wire s_axi_bready, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *) - input wire [15:0] s_axi_araddr, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *) - input wire s_axi_arvalid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *) - output wire s_axi_arready, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *) - output reg [31:0] s_axi_rdata, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *) - output reg [1:0] s_axi_rresp, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *) - output reg s_axi_rvalid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *) - input wire s_axi_rready, - - (* X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4, DATA_WIDTH 32" *) - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) - output reg [dma_addr_bits-1:0] m_axi_awaddr, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) - output reg [7:0] m_axi_awlen, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) - output reg m_axi_awvalid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) - input wire m_axi_awready, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) - output wire [31:0] m_axi_wdata, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) - output reg m_axi_wlast, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) - output reg m_axi_wvalid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) - input wire m_axi_wready, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) - input wire [1:0] m_axi_bresp, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) - input wire m_axi_bvalid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) - output wire m_axi_bready, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) - output reg [dma_addr_bits-1:0] m_axi_araddr, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) - output reg [7:0] m_axi_arlen, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) - output reg m_axi_arvalid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) - input wire m_axi_arready, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) - input wire [31:0] m_axi_rdata, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) - input wire m_axi_rlast, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) - input wire [1:0] m_axi_rresp, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) - input wire m_axi_rvalid, - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) - output wire m_axi_rready, - - // SD BUS - //inout wire sdio_cmd, - //inout wire [3:0] sdio_dat, - (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 sdio_clk CLK" *) - (* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000" *) - output reg sdio_clk, - (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 sdio_reset RST" *) - (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *) - output reg sdio_reset, - input wire sdio_cd, - - output reg sd_dat_reg_t, - output reg [3:0] sd_dat_reg_o, - input wire [3:0] sd_dat_i, - - output reg sd_cmd_reg_t, - output reg sd_cmd_reg_o, - input wire sd_cmd_i, - - // Interrupts - output wire interrupt -); - -`include "sd_defines.h" - -wire reset; - -wire go_idle; -reg cmd_start; -wire [1:0] cmd_setting; -wire cmd_start_tx; -wire [39:0] cmd; -wire [119:0] cmd_response; -wire cmd_crc_ok; -wire cmd_index_ok; -wire cmd_finish; - -wire d_write; -wire d_read; -wire [31:0] data_in_rx_fifo; -wire en_tx_fifo; -wire en_rx_fifo; -wire sd_data_busy; -(* mark_debug = "true" *) wire data_busy; -wire data_crc_ok; -wire tx_fifo_re; -wire rx_fifo_we; - -reg data_start_rx; -reg data_start_tx; -reg data_prepare_tx; -reg cmd_int_rst; -reg data_int_rst; -reg ctrl_rst; - -// AXI accessible registers -(* mark_debug = "true" *) reg [31:0] argument_reg; -(* mark_debug = "true" *) reg [`CMD_REG_SIZE-1:0] command_reg; -(* mark_debug = "true" *) reg [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg; -(* mark_debug = "true" *) reg [`DATA_TIMEOUT_W-1:0] data_timeout_reg; -(* mark_debug = "true" *) reg [0:0] software_reset_reg; -(* mark_debug = "true" *) wire [31:0] response_0_reg; -(* mark_debug = "true" *) wire [31:0] response_1_reg; -(* mark_debug = "true" *) wire [31:0] response_2_reg; -(* mark_debug = "true" *) wire [31:0] response_3_reg; -(* mark_debug = "true" *) reg [`BLKSIZE_W-1:0] block_size_reg; -(* mark_debug = "true" *) reg [1:0] controller_setting_reg; -(* mark_debug = "true" *) wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg; -(* mark_debug = "true" *) wire [`INT_DATA_SIZE-1:0] data_int_status_reg; -(* mark_debug = "true" *) wire [`INT_DATA_SIZE-1:0] data_int_status; -(* mark_debug = "true" *) reg [`INT_CMD_SIZE-1:0] cmd_int_enable_reg; -(* mark_debug = "true" *) reg [`INT_DATA_SIZE-1:0] data_int_enable_reg; -(* mark_debug = "true" *) reg [`BLKCNT_W-1:0] block_count_reg; -(* mark_debug = "true" *) reg [dma_addr_bits-1:0] dma_addr_reg; -(* mark_debug = "true" *) reg [7:0] clock_divider_reg = 124; // 400KHz - -// ------ Clocks and resets - -(* ASYNC_REG="true" *) -reg [2:0] reset_sync; -assign reset = reset_sync[2]; - -always @(posedge clock) - reset_sync <= {reset_sync[1:0], !async_resetn}; - -reg [7:0] clock_cnt; -(* mark_debug = "true" *) reg clock_state; -(* mark_debug = "true" *) reg clock_posedge; -reg clock_data_in; -wire fifo_almost_full; -wire fifo_almost_empty; - -always @(posedge clock) begin - if (reset) begin - clock_posedge <= 0; - clock_data_in <= 0; - clock_state <= 0; - clock_cnt <= 0; - end else if (clock_cnt < clock_divider_reg) begin - clock_posedge <= 0; - clock_data_in <= 0; - clock_cnt <= clock_cnt + 1; - end else if (clock_cnt < 124 && data_busy && en_rx_fifo && fifo_almost_full) begin - // Prevent Rx FIFO overflow - clock_posedge <= 0; - clock_data_in <= 0; - clock_cnt <= clock_cnt + 1; - end else if (clock_cnt < 124 && data_busy && en_tx_fifo && fifo_almost_empty) begin - // Prevent Tx FIFO underflow - clock_posedge <= 0; - clock_data_in <= 0; - clock_cnt <= clock_cnt + 1; - end else begin - clock_state <= !clock_state; - clock_posedge <= !clock_state; - if (clock_divider_reg == 0) - clock_data_in <= !clock_state; - else - clock_data_in <= clock_state; - clock_cnt <= 0; - end - sdio_clk <= sdio_reset || clock_state; - - if (reset) sdio_reset <= 0; - else if (clock_posedge) sdio_reset <= controller_setting_reg[1]; -end - -// ------ SD IO Buffers - -// wire sd_cmd_i; -wire sd_cmd_o; -wire sd_cmd_oe; -// reg sd_cmd_reg_o; -// reg sd_cmd_reg_t; -// wire [3:0] sd_dat_i; -wire [3:0] sd_dat_o; -wire sd_dat_oe; -// reg [3:0] sd_dat_reg_o; -// reg sd_dat_reg_t; - -// IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(sdio_cmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); -// IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t)); -// IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t)); -// IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t)); -// IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t)); - -always @(negedge sdio_clk) begin - // Output data delayed by 1/2 clock cycle (5ns) to ensure - // required hold time: default speed - min 5ns, high speed - min 2ns (actual 5ns) - if (sdio_reset) begin - sd_cmd_reg_o <= 0; - sd_dat_reg_o <= 0; - sd_cmd_reg_t <= 0; - sd_dat_reg_t <= 0; - end else begin - sd_cmd_reg_o <= sd_cmd_o; - sd_dat_reg_o <= sd_dat_o; - sd_cmd_reg_t <= !sd_cmd_oe; - sd_dat_reg_t <= !(sd_dat_oe || (cmd_start_tx && (command_reg == 0))); - end -end - -// ------ SD card detect - -reg [25:0] sd_detect_cnt; -wire sd_insert_int = sd_detect_cnt[25]; -wire sd_remove_int = !sd_detect_cnt[25]; -reg sd_insert_ie; -reg sd_remove_ie; - -always @(posedge clock) begin - if (sdio_cd != sdio_card_detect_level) begin - sd_detect_cnt <= 0; - end else if (!sd_insert_int) begin - sd_detect_cnt <= sd_detect_cnt + 1; - end -end - -// ------ AXI Slave Interface - -reg [15:0] read_addr; -reg [15:0] write_addr; -reg [31:0] write_data; -reg rd_req; -reg [1:0] wr_req; - -assign s_axi_arready = !rd_req && !s_axi_rvalid; -assign s_axi_awready = !wr_req[0] && !s_axi_bvalid; -assign s_axi_wready = !wr_req[1] && !s_axi_bvalid; - -always @(posedge clock) begin - if (reset) begin - s_axi_rdata <= 0; - s_axi_rresp <= 0; - s_axi_rvalid <= 0; - s_axi_bresp <= 0; - s_axi_bvalid <= 0; - rd_req <= 0; - wr_req <= 0; - read_addr <= 0; - write_addr <= 0; - write_data <= 0; - cmd_start <= 0; - data_int_rst <= 0; - cmd_int_rst <= 0; - ctrl_rst <= 0; - argument_reg <= 0; - command_reg <= 0; - cmd_timeout_reg <= 0; - data_timeout_reg <= 0; - block_size_reg <= `RESET_BLOCK_SIZE; - controller_setting_reg <= 0; - cmd_int_enable_reg <= 0; - data_int_enable_reg <= 0; - software_reset_reg <= 0; - clock_divider_reg <= `RESET_CLOCK_DIV; - block_count_reg <= 0; - sd_insert_ie <= 0; - sd_remove_ie <= 0; - dma_addr_reg <= 0; - end else begin - if (clock_posedge) begin - cmd_start <= 0; - data_int_rst <= 0; - cmd_int_rst <= 0; - ctrl_rst <= software_reset_reg[0]; - end - if (s_axi_arready && s_axi_arvalid) begin - read_addr <= s_axi_araddr; - rd_req <= 1; - end - if (s_axi_rvalid && s_axi_rready) begin - s_axi_rvalid <= 0; - end else if (!s_axi_rvalid && rd_req) begin - s_axi_rdata <= 0; - if (read_addr[15:8] == 0) begin - case (read_addr[7:0]) - `argument : s_axi_rdata <= argument_reg; - `command : s_axi_rdata <= command_reg; - `resp0 : s_axi_rdata <= response_0_reg; - `resp1 : s_axi_rdata <= response_1_reg; - `resp2 : s_axi_rdata <= response_2_reg; - `resp3 : s_axi_rdata <= response_3_reg; - `controller : s_axi_rdata <= controller_setting_reg; - `blksize : s_axi_rdata <= block_size_reg; - `voltage : s_axi_rdata <= voltage_controll_reg; - `capa : s_axi_rdata <= capabilies_reg | (dma_addr_bits << 8); - `clock_d : s_axi_rdata <= clock_divider_reg; - `reset : s_axi_rdata <= { cmd_start, data_int_rst, cmd_int_rst, ctrl_rst }; - `cmd_timeout : s_axi_rdata <= cmd_timeout_reg; - `data_timeout : s_axi_rdata <= data_timeout_reg; - `cmd_isr : s_axi_rdata <= cmd_int_status_reg; - `cmd_iser : s_axi_rdata <= cmd_int_enable_reg; - `data_isr : s_axi_rdata <= data_int_status_reg; - `data_iser : s_axi_rdata <= data_int_enable_reg; - `blkcnt : s_axi_rdata <= block_count_reg; - `card_detect : s_axi_rdata <= { sd_remove_int, sd_remove_ie, sd_insert_int, sd_insert_ie }; - `dst_src_addr : s_axi_rdata <= dma_addr_reg[31:0]; - `dst_src_addr_high : if (dma_addr_bits > 32) s_axi_rdata <= dma_addr_reg[dma_addr_bits-1:32]; - endcase - end - s_axi_rresp <= 0; - s_axi_rvalid <= 1; - rd_req <= 0; - end - if (s_axi_awready && s_axi_awvalid) begin - write_addr <= s_axi_awaddr; - wr_req[0] <= 1; - end - if (s_axi_wready && s_axi_wvalid) begin - write_data <= s_axi_wdata; - wr_req[1] <= 1; - end - if (s_axi_bvalid && s_axi_bready) begin - s_axi_bvalid <= 0; - end else if (!s_axi_bvalid && wr_req == 2'b11) begin - if (write_addr[15:8] == 0) begin - case (write_addr[7:0]) - `argument : begin argument_reg <= write_data; cmd_start <= 1; end - `command : command_reg <= write_data; - `reset : software_reset_reg <= write_data; - `cmd_timeout : cmd_timeout_reg <= write_data; - `data_timeout : data_timeout_reg <= write_data; - `blksize : block_size_reg <= write_data; - `controller : controller_setting_reg <= write_data; - `cmd_isr : cmd_int_rst <= 1; - `cmd_iser : cmd_int_enable_reg <= write_data; - `clock_d : clock_divider_reg <= write_data; - `data_isr : data_int_rst <= 1; - `data_iser : data_int_enable_reg <= write_data; - `blkcnt : block_count_reg <= write_data; - `card_detect : begin sd_remove_ie <= write_data[2]; sd_insert_ie <= write_data[0]; end - `dst_src_addr : dma_addr_reg[31:0] <= write_data; - `dst_src_addr_high : if (dma_addr_bits > 32) dma_addr_reg[dma_addr_bits-1:32] <= write_data; - endcase - end - s_axi_bresp <= 0; - s_axi_bvalid <= 1; - wr_req <= 0; - end - end -end - -// ------ Data FIFO - -reg [31:0] fifo_mem [(1<= (1 << fifo_addr_bits) / 2; -wire [31:0] fifo_din = en_rx_fifo ? data_in_rx_fifo : m_bus_dat_i; -wire fifo_we = en_rx_fifo ? rx_fifo_we && clock_posedge : m_axi_rready && m_axi_rvalid; -wire fifo_re = en_rx_fifo ? m_axi_wready && m_axi_wvalid : tx_fifo_re && clock_posedge; -reg [31:0] fifo_dout; - -assign fifo_almost_full = fifo_data_len > (1 << fifo_addr_bits) * 3 / 4; -assign fifo_almost_empty = fifo_free_len > (1 << fifo_addr_bits) * 3 / 4; - -wire tx_stb = en_tx_fifo && fifo_free_len >= (1 << fifo_addr_bits) / 3; -wire rx_stb = en_rx_fifo && m_axi_bresp_cnt != 3'b111 && (fifo_data_len >= (1 << fifo_addr_bits) / 3 || (!fifo_empty && !data_busy)); - -always @(posedge clock) - if (reset || ctrl_rst || !(en_rx_fifo || en_tx_fifo)) begin - fifo_inp_pos <= 0; - fifo_out_pos <= 0; - end else begin - if (fifo_we && !fifo_full) begin - fifo_mem[fifo_inp_pos] <= fifo_din; - fifo_inp_pos <= fifo_inp_nxt; - if (fifo_empty) fifo_dout <= fifo_din; - end - if (fifo_re && !fifo_empty) begin - if (fifo_we && !fifo_full && fifo_out_nxt == fifo_inp_pos) fifo_dout <= fifo_din; - else fifo_dout <= fifo_mem[fifo_out_nxt]; - fifo_out_pos <= fifo_out_nxt; - end - end - -// ------ AXI Master Interface - -// AXI transaction (DDR access) is over 80 clock cycles -// Must use burst to achive required throughput - -reg m_axi_cyc; -wire m_axi_write = en_rx_fifo; -reg [7:0] m_axi_wcnt; -reg [dma_addr_bits-1:2] m_bus_adr_o; -wire [31:0] m_bus_dat_i; -reg [2:0] m_axi_bresp_cnt; -reg m_bus_error; - -assign m_axi_bready = m_axi_bresp_cnt != 0; -assign m_axi_rready = m_axi_cyc & !m_axi_write; -assign m_bus_dat_i = {m_axi_rdata[7:0],m_axi_rdata[15:8],m_axi_rdata[23:16],m_axi_rdata[31:24]}; -assign m_axi_wdata = {fifo_dout[7:0],fifo_dout[15:8],fifo_dout[23:16],fifo_dout[31:24]}; - -// AXI burst cannot cross a 4KB boundary -wire [fifo_addr_bits-1:0] tx_burst_len; -wire [fifo_addr_bits-1:0] rx_burst_len; -assign tx_burst_len = m_bus_adr_o[11:2] + fifo_free_len >= m_bus_adr_o[11:2] ? fifo_free_len - 1 : ~m_bus_adr_o[fifo_addr_bits+1:2]; -assign rx_burst_len = m_bus_adr_o[11:2] + fifo_data_len >= m_bus_adr_o[11:2] ? fifo_data_len - 1 : ~m_bus_adr_o[fifo_addr_bits+1:2]; - -assign data_int_status_reg = { data_int_status[`INT_DATA_SIZE-1:1], - !en_rx_fifo && !en_tx_fifo && !m_axi_cyc && m_axi_bresp_cnt == 0 && data_int_status[0] }; - -always @(posedge clock) begin - if (reset | ctrl_rst) begin - m_axi_arvalid <= 0; - m_axi_awvalid <= 0; - m_axi_wvalid <= 0; - m_axi_cyc <= 0; - end else if (m_axi_cyc) begin - if (m_axi_awvalid && m_axi_awready) begin - m_axi_awvalid <= 0; - end - if (m_axi_arvalid && m_axi_arready) begin - m_axi_arvalid <= 0; - end - if (m_axi_wvalid && m_axi_wready) begin - if (m_axi_wlast) begin - m_axi_wvalid <= 0; - m_axi_cyc <= 0; - end else begin - m_axi_wlast <= m_axi_wcnt + 1 == m_axi_awlen; - m_axi_wcnt <= m_axi_wcnt + 1; - end - end - if (m_axi_rvalid && m_axi_rready && m_axi_rlast) begin - m_axi_cyc <= 0; - end - end else if (tx_stb || rx_stb) begin - m_axi_cyc <= 1; - m_axi_wcnt <= 0; - if (m_axi_write) begin - m_axi_awaddr <= { m_bus_adr_o, 2'b00 }; - m_axi_awlen <= rx_burst_len < 8'hff ? rx_burst_len : 8'hff; - m_axi_wlast <= rx_burst_len == 0; - m_axi_awvalid <= 1; - m_axi_wvalid <= 1; - end else begin - m_axi_araddr <= { m_bus_adr_o, 2'b00 }; - m_axi_arlen <= tx_burst_len < 8'hff ? tx_burst_len : 8'hff; - m_axi_arvalid <= 1; - end - end - if (reset | ctrl_rst) begin - m_bus_adr_o <= 0; - end else if ((m_axi_wready && m_axi_wvalid) || (m_axi_rready && m_axi_rvalid)) begin - m_bus_adr_o <= m_bus_adr_o + 1; - end else if (!m_axi_cyc && !en_rx_fifo && !en_tx_fifo) begin - m_bus_adr_o <= dma_addr_reg[dma_addr_bits-1:2]; - end - if (reset | ctrl_rst) begin - m_axi_bresp_cnt <= 0; - end else if ((m_axi_awvalid && m_axi_awready) && !(m_axi_bvalid && m_axi_bready)) begin - m_axi_bresp_cnt <= m_axi_bresp_cnt + 1; - end else if (!(m_axi_awvalid && m_axi_awready) && (m_axi_bvalid && m_axi_bready)) begin - m_axi_bresp_cnt <= m_axi_bresp_cnt - 1; - end - if (reset | ctrl_rst | cmd_start) begin - m_bus_error <= 0; - end else if (m_axi_bvalid && m_axi_bready && m_axi_bresp) begin - m_bus_error <= 1; - end else if (m_axi_rvalid && m_axi_rready && m_axi_rresp) begin - m_bus_error <= 1; - end - if (reset | ctrl_rst) begin - data_start_tx <= 0; - data_start_rx <= 0; - data_prepare_tx <= 0; - end else if (clock_posedge) begin - data_start_tx <= 0; - data_start_rx <= 0; - if (cmd_start) begin - data_prepare_tx <= 0; - if (command_reg[`CMD_WITH_DATA] == 2'b01) data_start_rx <= 1; - else if (command_reg[`CMD_WITH_DATA] != 2'b00) data_prepare_tx <= 1; - end else if (data_prepare_tx) begin - if (cmd_int_status_reg[`INT_CMD_CC]) begin - data_prepare_tx <= 0; - data_start_tx <= 1; - end else if (cmd_int_status_reg[`INT_CMD_EI]) begin - data_prepare_tx <= 0; - end - end - end -end - -// ------ SD Card Interface - -sd_cmd_master sd_cmd_master0( - .clock (clock), - .clock_posedge (clock_posedge), - .reset (reset | ctrl_rst), - .start (cmd_start), - .int_status_rst (cmd_int_rst), - .setting (cmd_setting), - .start_xfr (cmd_start_tx), - .go_idle (go_idle), - .cmd (cmd), - .response (cmd_response), - .crc_error (!cmd_crc_ok), - .index_ok (cmd_index_ok), - .busy (sd_data_busy), - .finish (cmd_finish), - .argument (argument_reg), - .command (command_reg), - .timeout (cmd_timeout_reg), - .int_status (cmd_int_status_reg), - .response_0 (response_0_reg), - .response_1 (response_1_reg), - .response_2 (response_2_reg), - .response_3 (response_3_reg) - ); - -sd_cmd_serial_host cmd_serial_host0( - .clock (clock), - .clock_posedge (clock_posedge), - .clock_data_in (clock_data_in), - .reset (reset | ctrl_rst | go_idle), - .setting (cmd_setting), - .cmd (cmd), - .start (cmd_start_tx), - .finish (cmd_finish), - .response (cmd_response), - .crc_ok (cmd_crc_ok), - .index_ok (cmd_index_ok), - .cmd_i (sd_cmd_i), - .cmd_o (sd_cmd_o), - .cmd_oe (sd_cmd_oe) - ); - -sd_data_master sd_data_master0( - .clock (clock), - .clock_posedge (clock_posedge), - .reset (reset | ctrl_rst), - .start_tx (data_start_tx), - .start_rx (data_start_rx), - .timeout (data_timeout_reg), - .d_write (d_write), - .d_read (d_read), - .en_tx_fifo (en_tx_fifo), - .en_rx_fifo (en_rx_fifo), - .fifo_empty (fifo_empty), - .fifo_ready (fifo_ready), - .fifo_full (fifo_full), - .bus_cycle (m_axi_cyc || m_axi_bresp_cnt != 0), - .xfr_complete (!data_busy), - .crc_error (!data_crc_ok), - .bus_error (m_bus_error), - .int_status (data_int_status), - .int_status_rst (data_int_rst) - ); - -sd_data_serial_host sd_data_serial_host0( - .clock (clock), - .clock_posedge (clock_posedge), - .clock_data_in (clock_data_in), - .reset (reset | ctrl_rst), - .data_in (fifo_dout), - .rd (tx_fifo_re), - .data_out (data_in_rx_fifo), - .we (rx_fifo_we), - .dat_oe (sd_dat_oe), - .dat_o (sd_dat_o), - .dat_i (sd_dat_i), - .blksize (block_size_reg), - .bus_4bit (controller_setting_reg[0]), - .blkcnt (block_count_reg), - .start ({d_read, d_write}), - .byte_alignment (dma_addr_reg[1:0]), - .sd_data_busy (sd_data_busy), - .busy (data_busy), - .crc_ok (data_crc_ok) - ); - -assign interrupt = - |(cmd_int_status_reg & cmd_int_enable_reg) || - |(data_int_status_reg & data_int_enable_reg) || - (sd_insert_int & sd_insert_ie) || - (sd_remove_int & sd_remove_ie); - -endmodule From d5159d35a2bd69eb85ca5f0cf9caadc49f491867 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 2 Dec 2024 13:32:23 -0800 Subject: [PATCH 145/212] Remove locksteplog --- bin/wsim | 4 ---- 1 file changed, 4 deletions(-) diff --git a/bin/wsim b/bin/wsim index 91f8e30ab..740193e0f 100755 --- a/bin/wsim +++ b/bin/wsim @@ -31,7 +31,6 @@ def parseArgs(): parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="") parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true") parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true") - parser.add_argument("--locksteplog", "-b", help="Retired instruction number to be begin logging.", default=0) parser.add_argument("--lockstepverbose", "-lv", help="Run ImperasDV lock, step, and compare with tracing enabled", action="store_true") parser.add_argument("--covlog", "-d", help="Log coverage after n instructions.", default=0) parser.add_argument("--rvvi", "-r", help="Simulate rvvi hardware interface and ethernet.", action="store_true") @@ -99,8 +98,6 @@ def lockstepSetup(args): suffix = "" ImperasPlusArgs = "" - if(int(args.locksteplog) >= 1): EnableLog = 1 - else: EnableLog = 0 if (args.lockstep or args.lockstepverbose or args.fcov): imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic") if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs @@ -111,7 +108,6 @@ def lockstepSetup(args): prefix += f"IMPERAS_TOOLS={imperasicPath}" if (args.lockstep or args.lockstepverbose): - if(args.locksteplog != 0): ImperasPlusArgs = f" +IDV_TRACE2LOG={EnableLog} +IDV_TRACE2LOG_AFTER={args.locksteplog}" if(args.fcov): CovEnableStr = "1" if int(args.covlog) > 0 else "0" if(args.covlog >= 1): EnableLog = 1 From 783b81f8b8fcca56483167d1b86bedaa871dd1ad Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 2 Dec 2024 13:52:44 -0800 Subject: [PATCH 146/212] VCD support in all simulators --- bin/wsim | 2 +- testbench/testbench.sv | 9 +++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/bin/wsim b/bin/wsim index 740193e0f..9defcc1c9 100755 --- a/bin/wsim +++ b/bin/wsim @@ -78,7 +78,7 @@ def elfFileCheck(args): def prepSim(args, ElfFile): flags = "" if args.vcd: - args.args += " -DMAKEVCD=1" + args.params += " MAKE_VCD=1 " if args.rvvi: args.params += " RVVI_SYNTH_SUPPORTED=1 " if args.tb == "testbench_fp": diff --git a/testbench/testbench.sv b/testbench/testbench.sv index c777fdf3f..40f5410ef 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -44,6 +44,7 @@ module testbench; parameter I_CACHE_ADDR_LOGGER=0; parameter D_CACHE_ADDR_LOGGER=0; parameter RVVI_SYNTH_SUPPORTED=0; + parameter MAKE_VCD=0; `ifdef USE_IMPERAS_DV import idvPkg::*; @@ -230,10 +231,10 @@ module testbench; end $finish; end -`ifdef MAKEVCD - $dumpfile("testbench.vcd"); - $dumpvars; -`endif + if (MAKE_VCD) begin + $dumpfile("testbench.vcd"); + $dumpvars; + end end // initial begin // Model the testbench as an fsm. From edf96a7211763ebdd5f413d417121eacd76b3e9d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 2 Dec 2024 13:56:34 -0800 Subject: [PATCH 147/212] Move wsim debug flag to common flags section --- bin/wsim | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wsim b/bin/wsim index 9defcc1c9..8766957b1 100755 --- a/bin/wsim +++ b/bin/wsim @@ -85,6 +85,8 @@ def prepSim(args, ElfFile): args.params += f' TEST="{args.testsuite}" ' if ElfFile != "": args.args += f" {ElfFile}" + if args.gui and args.tb == "testbench": + args.params += " DEBUG=1 " if args.ccov: flags += " --ccov" if args.fcov: @@ -135,8 +137,6 @@ def runSim(args, flags, prefix): def runQuesta(args, flags, prefix): # Force Questa to use 64-bit mode, sometimes it defaults to 32-bit even on 64-bit machines prefix = "MTI_VCO_MODE=64 " + prefix - if (args.gui) and (args.tb == "testbench"): - args.params += "DEBUG=1" if (args.args != ""): args.args = f' --args \\"{args.args}\\"' if (args.params != ""): From 479c6667fe7a0d408ba4e27e874e19e9a9873650 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 2 Dec 2024 14:02:33 -0800 Subject: [PATCH 148/212] Generalize wsim gui flag and simplify questa launch command --- bin/wsim | 9 +++------ sim/questa/wally.do | 4 ++-- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/bin/wsim b/bin/wsim index 8766957b1..512ee5e42 100755 --- a/bin/wsim +++ b/bin/wsim @@ -91,6 +91,8 @@ def prepSim(args, ElfFile): flags += " --ccov" if args.fcov: flags += " --fcov" + if args.gui: + flags += " --gui" prefix, suffix = lockstepSetup(args) flags += suffix return flags, prefix @@ -143,10 +145,7 @@ def runQuesta(args, flags, prefix): args.params = f' --params \\"{args.params}\\"' # Questa cannot accept more than 9 arguments. fcov implies lockstep cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {flags}" - if (args.gui): # launch Questa with GUI; add +acc to keep variables accessible - cmd = f'cd $WALLY/sim/questa; {prefix} vsim -do "{cmd} +acc"' - else: # launch Questa in batch mode - cmd = f'cd $WALLY/sim/questa; {prefix} vsim -c -do "{cmd}"' + cmd = f'cd $WALLY/sim/questa; {prefix} vsim {"-c" if not args.gui else ""} -do "{cmd}"' print(f"Running Questa with command: {cmd}") os.system(cmd) @@ -156,8 +155,6 @@ def runVerilator(args, flags, prefix): def runVCS(args, flags, prefix): print(f"Running VCS on {args.config} {args.testsuite}") - # if (args.gui): - # flags += " --gui" if (args.args != ""): args.args = f' --args "{args.args}" ' if (args.params != ""): diff --git a/sim/questa/wally.do b/sim/questa/wally.do index f42bf4930..3935d7a25 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -8,7 +8,7 @@ # # Takes 1:10 to run RV64IC tests using gui -# Usage: do wally.do [--ccov] [--fcov] [+acc] [--args "any number of +value"] [--params "any number of VAR=VAL parameter overrides"] +# Usage: do wally.do [--ccov] [--fcov] [--gui] [--args "any number of +value"] [--params "any number of VAR=VAL parameter overrides"] # Example: do wally.do rv64gc arch64i testbench # Use this wally.do file to run this example. @@ -91,7 +91,7 @@ echo "number of args = $argc" echo "lst = $lst" # if +acc found set flag and remove from list -if {[lcheck lst "+acc"]} { +if {[lcheck lst "--gui"]} { set GUI 1 set accFlag "+acc" } From bd9ca6ada6d0fac5dd67b3ac7a1cedc31c1ac91e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 3 Dec 2024 00:18:00 -0800 Subject: [PATCH 149/212] Remove covlog --- bin/wsim | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/bin/wsim b/bin/wsim index 512ee5e42..1b0a848bf 100755 --- a/bin/wsim +++ b/bin/wsim @@ -32,7 +32,6 @@ def parseArgs(): parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true") parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true") parser.add_argument("--lockstepverbose", "-lv", help="Run ImperasDV lock, step, and compare with tracing enabled", action="store_true") - parser.add_argument("--covlog", "-d", help="Log coverage after n instructions.", default=0) parser.add_argument("--rvvi", "-r", help="Simulate rvvi hardware interface and ethernet.", action="store_true") return parser.parse_args() @@ -113,10 +112,7 @@ def lockstepSetup(args): if (args.lockstep or args.lockstepverbose): if(args.fcov): - CovEnableStr = "1" if int(args.covlog) > 0 else "0" - if(args.covlog >= 1): EnableLog = 1 - else: EnableLog = 0 - ImperasPlusArgs = f" +IDV_TRACE2COV={EnableLog} +TRACE2LOG_AFTER={args.covlog} +TRACE2COV_ENABLE={CovEnableStr}" + ImperasPlusArgs = f" +IDV_TRACE2COV={0} +TRACE2LOG_AFTER={0} +TRACE2COV_ENABLE={0}" else: suffix = "--lockstep" if(args.lockstepverbose): From 9f92572f2bd9fe3c4061a36a3b612761154072a4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 3 Dec 2024 01:26:31 -0800 Subject: [PATCH 150/212] Significantly simplify lockstepSetup function now that covlog and locksteplog are removed --- bin/wsim | 38 ++++++++++++++------------------------ 1 file changed, 14 insertions(+), 24 deletions(-) diff --git a/bin/wsim b/bin/wsim index 1b0a848bf..0db6bb68d 100755 --- a/bin/wsim +++ b/bin/wsim @@ -76,6 +76,7 @@ def elfFileCheck(args): def prepSim(args, ElfFile): flags = "" + prefix = "" if args.vcd: args.params += " MAKE_VCD=1 " if args.rvvi: @@ -92,33 +93,22 @@ def prepSim(args, ElfFile): flags += " --fcov" if args.gui: flags += " --gui" - prefix, suffix = lockstepSetup(args) - flags += suffix + if args.lockstep or args.lockstepverbose: + flags += " --lockstep" + if args.lockstep or args.lockstepverbose or args.fcov: + prefix = lockstepSetup(args) return flags, prefix def lockstepSetup(args): - prefix = "" - suffix = "" - ImperasPlusArgs = "" - - if (args.lockstep or args.lockstepverbose or args.fcov): - imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic") - if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs - imperasicPath = os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic") - if not os.path.isfile(imperasicPath): - print("Error: imperas.ic not found") - exit(1) - prefix += f"IMPERAS_TOOLS={imperasicPath}" - - if (args.lockstep or args.lockstepverbose): - if(args.fcov): - ImperasPlusArgs = f" +IDV_TRACE2COV={0} +TRACE2LOG_AFTER={0} +TRACE2COV_ENABLE={0}" - else: - suffix = "--lockstep" - if(args.lockstepverbose): - prefix += f":{WALLY}/sim/imperas-verbose.ic" - args.args += ImperasPlusArgs - return prefix, suffix + imperasicVerbosePath = os.path.join(WALLY, "sim", "imperas-verbose.ic") + imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic") + if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs + imperasicPath = os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic") + if not os.path.isfile(imperasicPath): + print("Error: imperas.ic not found") + exit(1) + prefix = f"IMPERAS_TOOLS={imperasicPath}{f':{imperasicVerbosePath}' if args.lockstepverbose else ''} " + return prefix def createDirs(args): for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb"]: From c1e6283201f736c43ae81e69c320ff4e59405f39 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Tue, 3 Dec 2024 03:54:36 -0800 Subject: [PATCH 151/212] Added another signal for VM Coverage --- testbench/common/wallyTracer.sv | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 51f0d302a..7f7919ee3 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -69,6 +69,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic [(P.XLEN-1):0] PTE_iM,PTE_dM,PTE_iW,PTE_dW; logic [(P.PA_BITS-1):0] PAIM,PADM,PAIW,PADW; logic [(P.PPN_BITS-1):0] PPN_iM,PPN_dM,PPN_iW,PPN_dW; + logic [1:0] PageType_iM, PageType_iW, PageType_dM, PageType_dW; logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW; logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW; @@ -121,6 +122,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE; assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; + assign PageType_iM = testbench.dut.core.lsu.PageType; + assign PageType_dM = testbench.dut.core.lsu.PageType; logic valid; @@ -359,10 +362,12 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW); flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW); flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW); - flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~StallW, PTE_iM, PTE_iW); - flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~StallW, PTE_dM, PTE_dW); + flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, StallW, PTE_iM, PTE_iW); + flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, StallW, PTE_dM, PTE_dW); flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~StallW, PPN_iM, PPN_iW); flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW); + flopenrc #(2) PageType_iWReg (clk, reset, FlushW, ~StallW, PageType_iM, PageType_iW); + flopenrc #(2) PageType_dWReg (clk, reset, FlushW, ~StallW, PageType_dM, PageType_dW); flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~StallW, ReadAccessM, ReadAccessW); flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~StallW, WriteAccessM, WriteAccessW); // *** what is this used for? From 4591d625d52abee228c5a478f94d22f1596a4d0e Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Tue, 3 Dec 2024 03:54:36 -0800 Subject: [PATCH 152/212] Added another signal for VM Coverage --- testbench/common/wallyTracer.sv | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 51f0d302a..7f7919ee3 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -69,6 +69,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic [(P.XLEN-1):0] PTE_iM,PTE_dM,PTE_iW,PTE_dW; logic [(P.PA_BITS-1):0] PAIM,PADM,PAIW,PADW; logic [(P.PPN_BITS-1):0] PPN_iM,PPN_dM,PPN_iW,PPN_dW; + logic [1:0] PageType_iM, PageType_iW, PageType_dM, PageType_dW; logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW; logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW; @@ -121,6 +122,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE; assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; + assign PageType_iM = testbench.dut.core.lsu.PageType; + assign PageType_dM = testbench.dut.core.lsu.PageType; logic valid; @@ -359,10 +362,12 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW); flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW); flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW); - flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~StallW, PTE_iM, PTE_iW); - flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~StallW, PTE_dM, PTE_dW); + flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, StallW, PTE_iM, PTE_iW); + flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, StallW, PTE_dM, PTE_dW); flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~StallW, PPN_iM, PPN_iW); flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW); + flopenrc #(2) PageType_iWReg (clk, reset, FlushW, ~StallW, PageType_iM, PageType_iW); + flopenrc #(2) PageType_dWReg (clk, reset, FlushW, ~StallW, PageType_dM, PageType_dW); flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~StallW, ReadAccessM, ReadAccessW); flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~StallW, WriteAccessM, WriteAccessW); // *** what is this used for? From 8bd4b8b235bb8e843ccf9d54a6e12eabbb6944d3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 3 Dec 2024 04:08:23 -0800 Subject: [PATCH 153/212] Simplify wsim createDirs function --- bin/wsim | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/bin/wsim b/bin/wsim index 0db6bb68d..a2527205a 100755 --- a/bin/wsim +++ b/bin/wsim @@ -110,9 +110,9 @@ def lockstepSetup(args): prefix = f"IMPERAS_TOOLS={imperasicPath}{f':{imperasicVerbosePath}' if args.lockstepverbose else ''} " return prefix -def createDirs(args): +def createDirs(sim): for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb"]: - os.makedirs(os.path.join(WALLY, "sim", args.sim, d), exist_ok=True) + os.makedirs(os.path.join(WALLY, "sim", sim, d), exist_ok=True) def runSim(args, flags, prefix): if (args.sim == "questa"): @@ -155,5 +155,5 @@ if __name__ == "__main__": print(f"Config={args.config} tests={args.testsuite} sim={args.sim} gui={args.gui} args='{args.args}' params='{args.params}'") ElfFile = elfFileCheck(args) flags, prefix = prepSim(args, ElfFile) - createDirs(args) + createDirs(args.sim) exit(runSim(args, flags, prefix)) From ffdaca2760c390e15a8827b4c9190203f759f3a0 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Tue, 3 Dec 2024 04:09:11 -0800 Subject: [PATCH 154/212] Removing debug signals --- testbench/common/wallyTracer.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 7f7919ee3..0e691741c 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -122,8 +122,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE; assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; - assign PageType_iM = testbench.dut.core.lsu.PageType; - assign PageType_dM = testbench.dut.core.lsu.PageType; + assign PageType_iM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal; + assign PageType_dM = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal; logic valid; @@ -362,8 +362,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW); flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW); flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW); - flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, StallW, PTE_iM, PTE_iW); - flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, StallW, PTE_dM, PTE_dW); + flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~StallW, PTE_iM, PTE_iW); + flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~StallW, PTE_dM, PTE_dW); flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~StallW, PPN_iM, PPN_iW); flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW); flopenrc #(2) PageType_iWReg (clk, reset, FlushW, ~StallW, PageType_iM, PageType_iW); From 54e09df77cdbf5c2a6acf77661f8e211340ed3d6 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Tue, 3 Dec 2024 04:10:22 -0800 Subject: [PATCH 155/212] Removing debug signals --- testbench/common/wallyTracer.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 0e691741c..fbe5d0163 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -122,8 +122,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE; assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; - assign PageType_iM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal; - assign PageType_dM = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal; + assign PageType_iM = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal; + assign PageType_dM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal; logic valid; From 3c848cd16c98fb5b4df1b9eae3cb173e9c5681ea Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 3 Dec 2024 09:56:03 -0600 Subject: [PATCH 156/212] Fixed bug in the wally tracer to support hptw pte accesses. --- testbench/common/wallyTracer.sv | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 51f0d302a..c873d5819 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -44,6 +44,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic [31:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW; logic InstrValidM, InstrValidW; logic StallE, StallM, StallW; + logic GatedStallW; logic FlushD, FlushE, FlushM, FlushW; logic TrapM, TrapW; logic HaltM, HaltW; @@ -89,6 +90,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign StallE = testbench.dut.core.StallE; assign StallM = testbench.dut.core.StallM; assign StallW = testbench.dut.core.StallW; + assign GatedStallW = testbench.dut.core.lsu.GatedStallW; assign FlushD = testbench.dut.core.FlushD; assign FlushE = testbench.dut.core.FlushE; assign FlushM = testbench.dut.core.FlushM; @@ -359,12 +361,12 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW); flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW); flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW); - flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~StallW, PTE_iM, PTE_iW); - flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~StallW, PTE_dM, PTE_dW); - flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~StallW, PPN_iM, PPN_iW); - flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW); - flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~StallW, ReadAccessM, ReadAccessW); - flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~StallW, WriteAccessM, WriteAccessW); + flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~GatedStallW, PTE_iM, PTE_iW); + flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~GatedStallW, PTE_dM, PTE_dW); + flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~GatedStallW, PPN_iM, PPN_iW); + flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~GatedStallW, PPN_dM, PPN_dW); + flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~GatedStallW, ReadAccessM, ReadAccessW); + flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~GatedStallW, WriteAccessM, WriteAccessW); // *** what is this used for? flopenrc #(1) ExecuteAccessDReg (clk, reset, FlushE, ~StallE, ExecuteAccessF, ExecuteAccessD); flopenrc #(1) ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE); From f071383a19b08bef5ac562ca0a24b900f5ea7795 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 3 Dec 2024 12:17:10 -0600 Subject: [PATCH 157/212] Added new debug scripts. --- fpga/constraints/marked_debug.txt | 7 + fpga/constraints/marked_debug_uart.txt | 33 +++++ fpga/constraints/small-debug-uart.xdc | 4 +- fpga/constraints/small-debug-wfi.xdc | 191 +++++++++++++++++++++++++ fpga/generator/wally.tcl | 2 +- 5 files changed, 234 insertions(+), 3 deletions(-) create mode 100644 fpga/constraints/marked_debug_uart.txt create mode 100644 fpga/constraints/small-debug-wfi.xdc diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index 4ac6b1bc6..9df1e86c3 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -31,3 +31,10 @@ uncore/uartPC16550D.sv : logic txfifotail uncore/uartPC16550D.sv : logic txfifohead uncore/uartPC16550D.sv : logic rxfifotriggered uncore/uartPC16550D.sv : logic rxdataready +privileged/privdec.sv : logic wfiM +privileged/privdec.sv : logic wfiW +privileged/privdec.sv : logic WFITimeoutM +uncore/plic_apb.sv : logic requests +uncore/plic_apb.sv : logic intInProgress +uncore/plic_apb.sv : logic intPending +uncore/plic_apb.sv : logic intClaim diff --git a/fpga/constraints/marked_debug_uart.txt b/fpga/constraints/marked_debug_uart.txt new file mode 100644 index 000000000..4ac6b1bc6 --- /dev/null +++ b/fpga/constraints/marked_debug_uart.txt @@ -0,0 +1,33 @@ +wally/wallypipelinedcore.sv: logic PCM +wally/wallypipelinedcore.sv: logic TrapM +wally/wallypipelinedcore.sv: logic InstrValidM +wally/wallypipelinedcore.sv: logic InstrM +lsu/lsu.sv: logic IEUAdrM +lsu/lsu.sv: logic MemRWM +mmu/hptw.sv: logic SATP_REGW +uncore/uartPC16550D.sv : logic MCR +uncore/uartPC16550D.sv : logic FCR +uncore/uartPC16550D.sv : logic MSR +uncore/uartPC16550D.sv : logic DTRb +uncore/uartPC16550D.sv : logic INTR +uncore/uartPC16550D.sv : logic RXRDYb +uncore/uartPC16550D.sv : logic TXRDYb +uncore/uartPC16550D.sv : logic RXerrIP +uncore/uartPC16550D.sv : logic IER +uncore/uartPC16550D.sv : logic LSR +uncore/uartPC16550D.sv : logic SCR +uncore/uartPC16550D.sv : statetype txstate +uncore/uartPC16550D.sv : logic RBR +uncore/uartPC16550D.sv : logic rxparityerr +uncore/uartPC16550D.sv : logic LCR +uncore/uartPC16550D.sv : logic intrID +uncore/uartPC16550D.sv : logic rxdataavailintr +uncore/uartPC16550D.sv : logic fifoenabled +uncore/uartPC16550D.sv : logic rxfifoentries +uncore/uartPC16550D.sv : logic txsrfull +uncore/uartPC16550D.sv : logic txhrfull +uncore/uartPC16550D.sv : logic txfifofull +uncore/uartPC16550D.sv : logic txfifotail +uncore/uartPC16550D.sv : logic txfifohead +uncore/uartPC16550D.sv : logic rxfifotriggered +uncore/uartPC16550D.sv : logic rxdataready diff --git a/fpga/constraints/small-debug-uart.xdc b/fpga/constraints/small-debug-uart.xdc index d2e9e3e34..01e8f9199 100644 --- a/fpga/constraints/small-debug-uart.xdc +++ b/fpga/constraints/small-debug-uart.xdc @@ -3,7 +3,7 @@ create_debug_core u_ila_0 ila -set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] @@ -198,7 +198,7 @@ set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] connect_debug_port u_ila_0/probe34 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxdataready} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe35] +set_property port_width 4 [get_debug_ports u_ila_0/probe35] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] connect_debug_port u_ila_0/probe35 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[3]}]] diff --git a/fpga/constraints/small-debug-wfi.xdc b/fpga/constraints/small-debug-wfi.xdc new file mode 100644 index 000000000..e87f3bce9 --- /dev/null +++ b/fpga/constraints/small-debug-wfi.xdc @@ -0,0 +1,191 @@ +create_debug_core u_ila_0 ila + + + + +set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +startgroup +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] +endgroup +connect_debug_port u_ila_0/clk [get_nets CPUCLK] + +set_property port_width 33 [get_debug_ports u_ila_0/probe0] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} } ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe1] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe2] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe3] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe4] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsoc/core/lsu/MemRWM[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe5] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe6] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe7] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe8] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe9] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe10] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/core/priv.priv/pmd/wfiM} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe11] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] +connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/core/priv.priv/pmd/wfiW} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe12] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] +connect_debug_port u_ila_0/probe12 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/INTR ]] + + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe13] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] +connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[3]}]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe14] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] +connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txsrfull}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe15] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] +connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txhrfull}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe16] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] +connect_debug_port u_ila_0/probe16 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RXRDYb ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe17] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] +connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifofull}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe18] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] +connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifoempty}]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe19] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] +connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/core/priv.priv/pmd/WFITimeoutM} ]] + +create_debug_port u_ila_0 probe +set_property port_width 12 [get_debug_ports u_ila_0/probe20] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] +connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[7]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[8]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[9]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[10]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[11]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[12]}]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe21] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] +connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 12 [get_debug_ports u_ila_0/probe22] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] +connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[7]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[8]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[9]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[10]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[11]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[12]}]] + +create_debug_port u_ila_0 probe +set_property port_width 12 [get_debug_ports u_ila_0/probe23] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] +connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[12]}]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe24] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] +connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txstate[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txstate[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe25] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] +connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxdataready} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe26] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] +connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[3]}]] + + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe27] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] +connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxstate[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxstate[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe28] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] +connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe29] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] +connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[2]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe30] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] +connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifotriggered} ]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe31] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] +connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/fifoenabled} ]] + + + + +# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock. +#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk] +connect_debug_port dbg_hub/clk [get_nets CPUCLK] diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index ff18bff1a..29e3a5a92 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -98,7 +98,7 @@ write_verilog -force -mode funcsim sim/syn-funcsim.v if {$board=="ArtyA7"} { #source ../constraints/small-debug.xdc #source ../constraints/small-debug-rvvi.xdc - source ../constraints/small-debug-uart.xdc + source ../constraints/small-debug-wfi.xdc } else { #source ../constraints/vcu-small-debug.xdc #source ../constraints/small-debug.xdc From 6c9c1fc8415a33df9d83a87e9d840593a2e8092a Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 3 Dec 2024 15:28:39 -0600 Subject: [PATCH 158/212] Added new tsm for debuggin the plic. --- fpga/generator/debug/plic.tsm | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 fpga/generator/debug/plic.tsm diff --git a/fpga/generator/debug/plic.tsm b/fpga/generator/debug/plic.tsm new file mode 100644 index 000000000..13edad457 --- /dev/null +++ b/fpga/generator/debug/plic.tsm @@ -0,0 +1,32 @@ +################################################## +# +# For info on creating trigger state machines: +# 1) In the main Vivado menu bar, select +# Window > Language Templates +# 2) In the Templates window, select +# Debug > Trigger State Machine +# 3) Refer to the entry 'Info' for an overview +# of the trigger state machine language. +# +# More information can be found in this document: +# +# Vivado Design Suite User Guide: Programming +# and Debugging (UG908) +# +################################################## +state state_reset: + if(wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress == 12'h200) then + goto state_1; + else + goto state_reset; + endif + +state state_1: + if(wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress == 12'h000) then + goto state_trigger; + else + goto state_1; + endif + +state state_trigger: + trigger; From c1eab9e77894f8cb8072867cbcd3d5eb61604043 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Thu, 5 Dec 2024 06:55:23 -0800 Subject: [PATCH 159/212] Updates to WallyTracer --- testbench/common/wallyTracer.sv | 39 +++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 70ed2b159..f74fb3d06 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -360,23 +360,28 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(1) CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW); //for VM Verification - flopenrc #(P.XLEN) VAdrIWReg (clk, reset, FlushW, ~StallW, VAdrIM, VAdrIW); - flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW); - flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW); - flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW); - flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~GatedStallW, PTE_iM, PTE_iW); - flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~GatedStallW, PTE_dM, PTE_dW); - flopenrc #(2) PageType_iWReg (clk, reset, FlushW, ~GatedStallW, PageType_iM, PageType_iW); - flopenrc #(2) PageType_dWReg (clk, reset, FlushW, ~GatedStallW, PageType_dM, PageType_dW); - flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~GatedStallW, PPN_iM, PPN_iW); - flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~GatedStallW, PPN_dM, PPN_dW); - flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~GatedStallW, ReadAccessM, ReadAccessW); - flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~GatedStallW, WriteAccessM, WriteAccessW); - // *** what is this used for? - flopenrc #(1) ExecuteAccessDReg (clk, reset, FlushE, ~StallD, ExecuteAccessF, ExecuteAccessD); - flopenrc #(1) ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE); - flopenrc #(1) ExecuteAccessMReg (clk, reset, FlushM, ~StallM, ExecuteAccessE, ExecuteAccessM); - flopenrc #(1) ExecuteAccessWReg (clk, reset, FlushW, ~StallW, ExecuteAccessM, ExecuteAccessW); + flopenrc #(P.XLEN) VAdrIWReg (clk, reset, FlushW, ~StallW, VAdrIM, VAdrIW); //Virtual Address for IMMU + flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW); //Virtual Address for DMMU + + flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW); //Physical Address for IMMU + flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW); //Physical Address for DMMU + + flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~GatedStallW, PTE_iM, PTE_iW); //PTE for IMMU + flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~GatedStallW, PTE_dM, PTE_dW); //PTE for DMMU + + flopenrc #(2) PageType_iWReg (clk, reset, FlushW, ~GatedStallW, PageType_iM, PageType_iW); //Page Type (kilo, mega, giga, tera) from IMMU + flopenrc #(2) PageType_dWReg (clk, reset, FlushW, ~GatedStallW, PageType_dM, PageType_dW); //Page Type (kilo, mega, giga, tera) from DMMU + + flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~GatedStallW, PPN_iM, PPN_iW); //Physical Page Number for IMMU + flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~GatedStallW, PPN_dM, PPN_dW); //Physical Page Number for DMMU + + flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~GatedStallW, ReadAccessM, ReadAccessW); //LoadAccess + flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~GatedStallW, WriteAccessM, WriteAccessW); //StoreAccess + + flopenrc #(1) ExecuteAccessDReg (clk, reset, FlushE, ~StallD, ExecuteAccessF, ExecuteAccessD); //Instruction Fetch Access + flopenrc #(1) ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE); //Instruction Fetch Access + flopenrc #(1) ExecuteAccessMReg (clk, reset, FlushM, ~StallM, ExecuteAccessE, ExecuteAccessM); //Instruction Fetch Access + flopenrc #(1) ExecuteAccessWReg (clk, reset, FlushW, ~StallW, ExecuteAccessM, ExecuteAccessW); //Instruction Fetch Access // Initially connecting the writeback stage signals, but may need to use M stage // and gate on ~FlushW. From a3cd2669672f8566e6710cf7277632ad93c8f7a9 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 7 Dec 2024 12:54:51 -0800 Subject: [PATCH 160/212] Fix run_vcs code coverage flag --- sim/vcs/run_vcs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs index 1234ac4c8..fb04d0fd2 100755 --- a/sim/vcs/run_vcs +++ b/sim/vcs/run_vcs @@ -24,8 +24,8 @@ parser = argparse.ArgumentParser() parser.add_argument("config", help="Configuration file") parser.add_argument("testsuite", help="Test suite (or none, when running a single ELF file) ") parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench") -parser.add_argument("--coverage", "-c", help="Code & Functional Coverage", action="store_true") -parser.add_argument("--fcov", "-f", help="Code & Functional Coverage", action="store_true") +parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true") +parser.add_argument("--fcov", "-f", help="Functional Coverage", action="store_true") parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="") parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="") parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true") @@ -65,7 +65,7 @@ else: LOCKSTEP_SIMV = "" # coverage mode -if (args.coverage): +if (args.ccov): COV_OPTIONS = "-cm line+cond+branch+fsm+tgl -cm_log " + wkdir + "/coverage.log -cm_dir " + wkdir + "/coverage" else: COV_OPTIONS = "" @@ -93,6 +93,6 @@ SIMV_CMD= wkdir + "/" + OUTPUT + " +TEST=" + args.testsuite + " " + args.args + print("Executing: " + str(VCS) ) subprocess.run(VCS, shell=True) subprocess.run(SIMV_CMD, shell=True) -if (args.coverage): +if (args.ccov): COV_RUN = "urg -dir " + wkdir + "/coverage.vdb -format text -report IndividualCovReport/" + args.config + "_" + args.testsuite subprocess.run(COV_RUN, shell=True) From 14ad03cde13b3d33cd6d56f538d6ccf00baca3c4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 7 Dec 2024 12:55:48 -0800 Subject: [PATCH 161/212] Add .memfile to gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 9a0f35cc1..1a8b66e80 100644 --- a/.gitignore +++ b/.gitignore @@ -12,6 +12,7 @@ *.map *.elf* *.list +*.memfile # General directories to ignore .vscode/ From 95a5070a729915f7bd56330e7e88746a48802ba4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 7 Dec 2024 12:56:12 -0800 Subject: [PATCH 162/212] Move IMPERAS_HOME in wally.do to avoid issue if not set --- sim/questa/wally.do | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 3935d7a25..6e073ea87 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -40,7 +40,6 @@ set TESTSUITE ${2} set TESTBENCH ${3} set WKDIR wkdir/${CFG}_${TESTSUITE} set WALLY $::env(WALLY) -set IMPERAS_HOME $::env(IMPERAS_HOME) set CONFIG ${WALLY}/config set SRC ${WALLY}/src set TB ${WALLY}/testbench @@ -118,6 +117,7 @@ if {[lcheck lst "--fcov"]} { # if --lockstep or --fcov found set flag and remove from list if {[lcheck lst "--lockstep"] || $FunctCoverage == 1} { + set IMPERAS_HOME $::env(IMPERAS_HOME) set lockstep 1 set lockstepvlog "+define+USE_IMPERAS_DV \ +incdir+${IMPERAS_HOME}/ImpPublic/include/host \ From 25cdf83aaee202eeb4c4c371f090efe0552ef884 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 7 Dec 2024 13:13:35 -0800 Subject: [PATCH 163/212] Remove extra spaces and use lists for assembling args and params --- bin/wsim | 40 +++++++++++++++++++++++----------------- 1 file changed, 23 insertions(+), 17 deletions(-) diff --git a/bin/wsim b/bin/wsim index a2527205a..1fde4eda1 100755 --- a/bin/wsim +++ b/bin/wsim @@ -39,7 +39,7 @@ def validateArgs(args): if not args.testsuite and not args.elf: print("Error: Missing test suite or ELF file") exit(1) - if args.lockstep and not args.testsuite.endswith('.elf') and args.testsuite != "buildroot" : + if args.lockstep and not args.testsuite.endswith('.elf') and args.testsuite != "buildroot": print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf or buildroot.") exit(1) elif (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose) and args.sim not in ["questa", "vcs"]: @@ -75,28 +75,34 @@ def elfFileCheck(args): return ElfFile def prepSim(args, ElfFile): - flags = "" prefix = "" + params = [] + args = [] + flags = [] if args.vcd: - args.params += " MAKE_VCD=1 " + params.append("MAKE_VCD=1") if args.rvvi: - args.params += " RVVI_SYNTH_SUPPORTED=1 " + params.append("RVVI_SYNTH_SUPPORTED=1") if args.tb == "testbench_fp": - args.params += f' TEST="{args.testsuite}" ' - if ElfFile != "": - args.args += f" {ElfFile}" + params.append(f'TEST="{args.testsuite}"') + if ElfFile: + args.append += f"{ElfFile}" if args.gui and args.tb == "testbench": - args.params += " DEBUG=1 " + params.append("DEBUG=1") if args.ccov: - flags += " --ccov" + flags.append("--ccov") if args.fcov: - flags += " --fcov" + flags.append("--fcov") if args.gui: - flags += " --gui" + flags.append("--gui") if args.lockstep or args.lockstepverbose: - flags += " --lockstep" + flags.append("--lockstep") if args.lockstep or args.lockstepverbose or args.fcov: prefix = lockstepSetup(args) + # Combine into a single string + args.args += " ".join(args) + args.params += " ".join(params) + flags = " ".join(flags) return flags, prefix def lockstepSetup(args): @@ -107,7 +113,7 @@ def lockstepSetup(args): if not os.path.isfile(imperasicPath): print("Error: imperas.ic not found") exit(1) - prefix = f"IMPERAS_TOOLS={imperasicPath}{f':{imperasicVerbosePath}' if args.lockstepverbose else ''} " + prefix = f"IMPERAS_TOOLS={imperasicPath}{f':{imperasicVerbosePath}' if args.lockstepverbose else ''}" return prefix def createDirs(sim): @@ -126,9 +132,9 @@ def runQuesta(args, flags, prefix): # Force Questa to use 64-bit mode, sometimes it defaults to 32-bit even on 64-bit machines prefix = "MTI_VCO_MODE=64 " + prefix if (args.args != ""): - args.args = f' --args \\"{args.args}\\"' + args.args = fr'--args \"{args.args}\"' if (args.params != ""): - args.params = f' --params \\"{args.params}\\"' + args.params = fr'--params \"{args.params}\"' # Questa cannot accept more than 9 arguments. fcov implies lockstep cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {flags}" cmd = f'cd $WALLY/sim/questa; {prefix} vsim {"-c" if not args.gui else ""} -do "{cmd}"' @@ -142,9 +148,9 @@ def runVerilator(args, flags, prefix): def runVCS(args, flags, prefix): print(f"Running VCS on {args.config} {args.testsuite}") if (args.args != ""): - args.args = f' --args "{args.args}" ' + args.args = f'--args "{args.args}"' if (args.params != ""): - args.params = f' --params "{args.params}" ' + args.params = f'--params "{args.params}"' cmd = f"cd $WALLY/sim/vcs; {prefix} ./run_vcs {args.config} {args.testsuite} --tb {args.tb} {args.args} {args.params} {flags}" print(cmd) os.system(cmd) From bdc20243a6d183ca73bd8d7d9e317c46becdf551 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 7 Dec 2024 13:18:03 -0800 Subject: [PATCH 164/212] Fix overriding args --- bin/wsim | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/bin/wsim b/bin/wsim index 1fde4eda1..9bc3252bc 100755 --- a/bin/wsim +++ b/bin/wsim @@ -76,33 +76,33 @@ def elfFileCheck(args): def prepSim(args, ElfFile): prefix = "" - params = [] - args = [] - flags = [] + paramsList = [] + argsList = [] + flagsList = [] if args.vcd: - params.append("MAKE_VCD=1") + paramsList.append("MAKE_VCD=1") if args.rvvi: - params.append("RVVI_SYNTH_SUPPORTED=1") + paramsList.append("RVVI_SYNTH_SUPPORTED=1") if args.tb == "testbench_fp": - params.append(f'TEST="{args.testsuite}"') + paramsList.append(f'TEST="{args.testsuite}"') if ElfFile: - args.append += f"{ElfFile}" + argsList.append += f"{ElfFile}" if args.gui and args.tb == "testbench": - params.append("DEBUG=1") + paramsList.append("DEBUG=1") if args.ccov: - flags.append("--ccov") + flagsList.append("--ccov") if args.fcov: - flags.append("--fcov") + flagsList.append("--fcov") if args.gui: - flags.append("--gui") + flagsList.append("--gui") if args.lockstep or args.lockstepverbose: - flags.append("--lockstep") + flagsList.append("--lockstep") if args.lockstep or args.lockstepverbose or args.fcov: prefix = lockstepSetup(args) # Combine into a single string - args.args += " ".join(args) - args.params += " ".join(params) - flags = " ".join(flags) + args.args += " ".join(argsList) + args.params += " ".join(paramsList) + flags = " ".join(flagsList) return flags, prefix def lockstepSetup(args): From 59bedb78c58377df3844d27cdafcf97e65226856 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 7 Dec 2024 13:24:10 -0800 Subject: [PATCH 165/212] Cleanup verilator paths --- sim/verilator/Makefile | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile index 6a6ad267a..666516c2d 100644 --- a/sim/verilator/Makefile +++ b/sim/verilator/Makefile @@ -17,12 +17,10 @@ EXPANDED_PARAM_ARGS:=$(patsubst %,-G%,$(PARAM_ARGS)) WALLYCONF?=rv64gc TEST?=arch64i -TESTBENCH?=testbench +TESTBENCH?=testbench # constants # assume WALLY variable is correctly configured in the shell environment -WORKING_DIR=${WALLY}/sim/verilator -TARGET=$(WORKING_DIR)/target # INCLUDE_PATH are pathes that Verilator should search for files it needs INCLUDE_PATH="-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)" # SOURCES are source files @@ -30,6 +28,8 @@ SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/${TESTBENCH}.sv ${WALLY}/testbenc # DEPENDENCIES are configuration files and source files, which leads to recompilation of executables DEPENDENCIES=${WALLY}/config/shared/*.vh $(SOURCES) +WORKDIR = $(VERILATOR_DIR)/wkdir/$(WALLYCONF)_$(TEST) + # regular testbench requires a wrapper defining getenvval ifeq ($(TESTBENCH), testbench) WRAPPER=${WALLY}/sim/verilator/wrapper.c @@ -41,9 +41,9 @@ endif default: run -run: wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH} +run: $(WORKDIR)/V${TESTBENCH} mkdir -p $(VERILATOR_DIR)/logs - wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH} ${ARGTEST} $(PLUS_ARGS) + $(WORKDIR)/V${TESTBENCH} ${ARGTEST} $(PLUS_ARGS) profile: obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF) $(VERILATOR_DIR)/obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF) ${ARGTEST} @@ -54,10 +54,10 @@ profile: obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF) mv gmon_$(WALLYCONF)* $(VERILATOR_DIR)/logs_profiling echo "Please check $(VERILATOR_DIR)/logs_profiling/gmon_$(WALLYCONF)* for logs and output files." -wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH}: $(DEPENDENCIES) - mkdir -p wkdir/$(WALLYCONF)_$(TEST) +$(WORKDIR)/V${TESTBENCH}: $(DEPENDENCIES) + mkdir -p $(WORKDIR) verilator \ - --Mdir wkdir/$(WALLYCONF)_$(TEST) -o V${TESTBENCH} \ + --Mdir $(WORKDIR) -o V${TESTBENCH} \ --binary --trace \ $(OPT) $(PARAMS) $(NONPROF) \ --top-module ${TESTBENCH} --relative-includes \ From 8b2a053bd430972b74122ef935359500d1b0bc17 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 7 Dec 2024 13:32:56 -0800 Subject: [PATCH 166/212] Remove unnecessary parentheses in wsim --- bin/wsim | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/bin/wsim b/bin/wsim index 9bc3252bc..597d7f111 100755 --- a/bin/wsim +++ b/bin/wsim @@ -121,19 +121,19 @@ def createDirs(sim): os.makedirs(os.path.join(WALLY, "sim", sim, d), exist_ok=True) def runSim(args, flags, prefix): - if (args.sim == "questa"): + if args.sim == "questa": runQuesta(args, flags, prefix) - elif (args.sim == "verilator"): + elif args.sim == "verilator": runVerilator(args, flags, prefix) - elif (args.sim == "vcs"): + elif args.sim == "vcs": runVCS(args, flags, prefix) def runQuesta(args, flags, prefix): # Force Questa to use 64-bit mode, sometimes it defaults to 32-bit even on 64-bit machines prefix = "MTI_VCO_MODE=64 " + prefix - if (args.args != ""): + if args.args != "": args.args = fr'--args \"{args.args}\"' - if (args.params != ""): + if args.params != "": args.params = fr'--params \"{args.params}\"' # Questa cannot accept more than 9 arguments. fcov implies lockstep cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {flags}" From 8fc907a4966a0ace4998d9d681e492cf759eee3c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 7 Dec 2024 13:33:14 -0800 Subject: [PATCH 167/212] Switch to sys.exit in wsim --- bin/wsim | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/bin/wsim b/bin/wsim index 597d7f111..95bbda312 100755 --- a/bin/wsim +++ b/bin/wsim @@ -13,6 +13,7 @@ import argparse import os +import sys # Global variable WALLY = os.environ.get('WALLY') @@ -38,16 +39,16 @@ def parseArgs(): def validateArgs(args): if not args.testsuite and not args.elf: print("Error: Missing test suite or ELF file") - exit(1) + sys.exit(1) if args.lockstep and not args.testsuite.endswith('.elf') and args.testsuite != "buildroot": print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf or buildroot.") - exit(1) + sys.exit(1) elif (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose) and args.sim not in ["questa", "vcs"]: print("Option only supported for Questa and VCS") - exit(1) + sys.exit(1) elif (args.tb == "testbench_fp" and args.sim != "questa"): print("Error: testbench_fp presently only supported by Questa, not VCS or Verilator, because of a touchy testbench") - exit(1) + sys.exit(1) def elfFileCheck(args): ElfFile = "" @@ -55,23 +56,23 @@ def elfFileCheck(args): ElfFile = f"+ElfFile={os.path.abspath(args.elf)}" elif args.elf != "": print(f"ELF file not found: {args.elf}") - exit(1) + sys.exit(1) elif args.testsuite.endswith('.elf'): # No --elf argument; check if testsuite has a .elf extension and use that instead if os.path.isfile(args.testsuite): ElfFile = f"+ElfFile={os.path.abspath(args.testsuite)}" # extract the elf name from the path to be the test suite fields = args.testsuite.rsplit('/', 3) # if the name is just ref.elf in a deep path (riscv-arch-test/wally-riscv-arch-test), then use the directory name as the test suite to make it unique; otherwise work directory will have duplicates. - if (len(fields) > 3): - if (fields[2] == "ref"): + if len(fields) > 3: + if fields[2] == "ref": args.testsuite = f"{fields[1]}_{fields[3]}" else: args.testsuite = f"{fields[2]}_{fields[3]}" - elif ('/' in args.testsuite): + elif '/' in args.testsuite: args.testsuite=args.testsuite.rsplit('/', 1)[1] # strip off path if present else: print(f"ELF file not found: {args.testsuite}") - exit(1) + sys.exit(1) return ElfFile def prepSim(args, ElfFile): @@ -112,7 +113,7 @@ def lockstepSetup(args): imperasicPath = os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic") if not os.path.isfile(imperasicPath): print("Error: imperas.ic not found") - exit(1) + sys.exit(1) prefix = f"IMPERAS_TOOLS={imperasicPath}{f':{imperasicVerbosePath}' if args.lockstepverbose else ''}" return prefix @@ -147,9 +148,9 @@ def runVerilator(args, flags, prefix): def runVCS(args, flags, prefix): print(f"Running VCS on {args.config} {args.testsuite}") - if (args.args != ""): + if args.args != "": args.args = f'--args "{args.args}"' - if (args.params != ""): + if args.params != "": args.params = f'--params "{args.params}"' cmd = f"cd $WALLY/sim/vcs; {prefix} ./run_vcs {args.config} {args.testsuite} --tb {args.tb} {args.args} {args.params} {flags}" print(cmd) @@ -162,4 +163,4 @@ if __name__ == "__main__": ElfFile = elfFileCheck(args) flags, prefix = prepSim(args, ElfFile) createDirs(args.sim) - exit(runSim(args, flags, prefix)) + sys.exit(runSim(args, flags, prefix)) From c178180b0f50cda7de4098e46a2d51fdddc2491e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 7 Dec 2024 13:53:18 -0800 Subject: [PATCH 168/212] A bit more cleanup --- bin/wsim | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/bin/wsim b/bin/wsim index 95bbda312..dbe106280 100755 --- a/bin/wsim +++ b/bin/wsim @@ -43,7 +43,7 @@ def validateArgs(args): if args.lockstep and not args.testsuite.endswith('.elf') and args.testsuite != "buildroot": print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf or buildroot.") sys.exit(1) - elif (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose) and args.sim not in ["questa", "vcs"]: + elif any([args.gui, args.ccov, args.fcov, args.lockstep, args.lockstepverbose]) and args.sim not in ["questa", "vcs"]: print("Option only supported for Questa and VCS") sys.exit(1) elif (args.tb == "testbench_fp" and args.sim != "questa"): @@ -125,7 +125,7 @@ def runSim(args, flags, prefix): if args.sim == "questa": runQuesta(args, flags, prefix) elif args.sim == "verilator": - runVerilator(args, flags, prefix) + runVerilator(args) elif args.sim == "vcs": runVCS(args, flags, prefix) @@ -142,7 +142,7 @@ def runQuesta(args, flags, prefix): print(f"Running Questa with command: {cmd}") os.system(cmd) -def runVerilator(args, flags, prefix): +def runVerilator(args): print(f"Running Verilator on {args.config} {args.testsuite}") os.system(f'make -C {WALLY}/sim/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} PLUS_ARGS="{args.args}" PARAM_ARGS="{args.params}"') From c9885ff495ad6f314cb6bfddeb888336db6008b8 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 7 Dec 2024 13:54:47 -0800 Subject: [PATCH 169/212] Change wsim main function for potential use as imported module in regression-wally --- bin/wsim | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/bin/wsim b/bin/wsim index dbe106280..55ca015e6 100755 --- a/bin/wsim +++ b/bin/wsim @@ -156,11 +156,14 @@ def runVCS(args, flags, prefix): print(cmd) os.system(cmd) -if __name__ == "__main__": - args = parseArgs() +def main(args): validateArgs(args) print(f"Config={args.config} tests={args.testsuite} sim={args.sim} gui={args.gui} args='{args.args}' params='{args.params}'") ElfFile = elfFileCheck(args) flags, prefix = prepSim(args, ElfFile) createDirs(args.sim) sys.exit(runSim(args, flags, prefix)) + +if __name__ == "__main__": + args = parseArgs() + main(args) From 464a516e989309a2a134e3be48bcb6da47666147 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 7 Dec 2024 13:58:45 -0800 Subject: [PATCH 170/212] Disable fcov on testsuite --- bin/wsim | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wsim b/bin/wsim index 55ca015e6..e8862ec95 100755 --- a/bin/wsim +++ b/bin/wsim @@ -40,8 +40,8 @@ def validateArgs(args): if not args.testsuite and not args.elf: print("Error: Missing test suite or ELF file") sys.exit(1) - if args.lockstep and not args.testsuite.endswith('.elf') and args.testsuite != "buildroot": - print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf or buildroot.") + if any([args.lockstep, args.lockstepverbose, args.fcov]) and not (args.testsuite.endswith('.elf') or args.elf) and args.testsuite != "buildroot": + print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep or fcov. Must run a single elf or buildroot.") sys.exit(1) elif any([args.gui, args.ccov, args.fcov, args.lockstep, args.lockstepverbose]) and args.sim not in ["questa", "vcs"]: print("Option only supported for Questa and VCS") From 256211e4dcc3bfb806ba5d97ea25886aa06a8f4d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 7 Dec 2024 14:06:31 -0800 Subject: [PATCH 171/212] Fix wsim elfile handling --- bin/wsim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/wsim b/bin/wsim index e8862ec95..ebee44883 100755 --- a/bin/wsim +++ b/bin/wsim @@ -87,7 +87,7 @@ def prepSim(args, ElfFile): if args.tb == "testbench_fp": paramsList.append(f'TEST="{args.testsuite}"') if ElfFile: - argsList.append += f"{ElfFile}" + argsList.append(f"{ElfFile}") if args.gui and args.tb == "testbench": paramsList.append("DEBUG=1") if args.ccov: From 1c0e5de07b4544164b86c1642a24694966dcd49e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 8 Dec 2024 01:46:44 -0800 Subject: [PATCH 172/212] Add --define to wsim --- bin/wsim | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/bin/wsim b/bin/wsim index ebee44883..acb5cec76 100755 --- a/bin/wsim +++ b/bin/wsim @@ -30,6 +30,7 @@ def parseArgs(): parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true") parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="") parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="") + parser.add_argument("--define", "-d", help="Optional define macros passed to simulator", default="") parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true") parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true") parser.add_argument("--lockstepverbose", "-lv", help="Run ImperasDV lock, step, and compare with tracing enabled", action="store_true") @@ -136,6 +137,8 @@ def runQuesta(args, flags, prefix): args.args = fr'--args \"{args.args}\"' if args.params != "": args.params = fr'--params \"{args.params}\"' + if args.define != "": + args.define = fr'--define \"{args.define}\"' # Questa cannot accept more than 9 arguments. fcov implies lockstep cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {flags}" cmd = f'cd $WALLY/sim/questa; {prefix} vsim {"-c" if not args.gui else ""} -do "{cmd}"' @@ -144,7 +147,7 @@ def runQuesta(args, flags, prefix): def runVerilator(args): print(f"Running Verilator on {args.config} {args.testsuite}") - os.system(f'make -C {WALLY}/sim/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} PLUS_ARGS="{args.args}" PARAM_ARGS="{args.params}"') + os.system(f'make -C {WALLY}/sim/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} PLUS_ARGS="{args.args}" PARAM_ARGS="{args.params}" DEFINE_ARGS="{args.define}"') def runVCS(args, flags, prefix): print(f"Running VCS on {args.config} {args.testsuite}") @@ -152,6 +155,8 @@ def runVCS(args, flags, prefix): args.args = f'--args "{args.args}"' if args.params != "": args.params = f'--params "{args.params}"' + if args.define != "": + args.define = f'--define "{args.define}"' cmd = f"cd $WALLY/sim/vcs; {prefix} ./run_vcs {args.config} {args.testsuite} --tb {args.tb} {args.args} {args.params} {flags}" print(cmd) os.system(cmd) From f4473c03abdf7dd2e1321fee0545f0c16ebad749 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 8 Dec 2024 01:47:23 -0800 Subject: [PATCH 173/212] add --define support to questa --- sim/questa/wally.do | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 6e073ea87..639539e02 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -54,6 +54,7 @@ vlib ${WKDIR} set PlusArgs "" set ParamArgs "" set ExpandedParamArgs {} +set DefineArgs "" set ccov 0 set CoverageVoptArg "" @@ -62,7 +63,6 @@ set CoverageVsimArg "" set FunctCoverage 0 set FCvlog "" set FCvopt "" -set FCdefineCOVER_EXTS {} set lockstep 0 set lockstepvlog "" @@ -106,13 +106,11 @@ if {[lcheck lst "--ccov"]} { if {[lcheck lst "--fcov"]} { set FunctCoverage 1 # COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but no longer affects tests - set FCvlog "+define+INCLUDE_TRACE2COV \ + set FCvlog "+define+INCLUDE_TRACE2COV \ +define+IDV_INCLUDE_TRACE2COV \ +define+COVER_BASE_RV32I \ - +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source \ - " + +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source" set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1" - } # if --lockstep or --fcov found set flag and remove from list @@ -145,6 +143,13 @@ if {$ParamArgsIndex >= 0} { set lst [lreplace $lst $ParamArgsIndex [expr {$ParamArgsIndex + 1}]] } +# Set +define macros passed using the --define flag +set DefineArgsIndex [lsearch -exact $lst "--define"] +if {$DefineArgsIndex >= 0} { + set DefineArgs [lindex $lst [expr {$DefineArgsIndex + 1}]] + set lst [lreplace $lst $DefineArgsIndex [expr {$DefineArgsIndex + 1}]] +} + # Debug print statements if {$DEBUG > 0} { echo "GUI = $GUI" @@ -153,7 +158,8 @@ if {$DEBUG > 0} { echo "FunctCoverage = $FunctCoverage" echo "remaining list = $lst" echo "Extra +args = $PlusArgs" - echo "Extra -args = $ExpandedParamArgs" + echo "Extra params = $ExpandedParamArgs" + echo "Extra defines = $DefineArgs" } # compile source files @@ -162,7 +168,7 @@ if {$DEBUG > 0} { # because vsim will run vopt set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv32_priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}" set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv" -vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 +vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}{$DefineArgs} {*}${FCvlog} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals From f856ed15ba1adff7ce40cfe37781344620b48af1 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 8 Dec 2024 01:51:08 -0800 Subject: [PATCH 174/212] add --define support to VCS --- sim/vcs/run_vcs | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs index fb04d0fd2..7e2c7aca8 100755 --- a/sim/vcs/run_vcs +++ b/sim/vcs/run_vcs @@ -28,11 +28,12 @@ parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true") parser.add_argument("--fcov", "-f", help="Functional Coverage", action="store_true") parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="") parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="") +parser.add_argument("--define", "-d", help="Optional define macros passed to simulator", default="") parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true") # GUI not yet implemented #parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true") args = parser.parse_args() -print("run_vcs Config=" + args.config + " tests=" + args.testsuite + " lockstep=" + str(args.lockstep) + " args='" + args.args + "' params='" + args.params + "'") +print("run_vcs Config=" + args.config + " tests=" + args.testsuite + " lockstep=" + str(args.lockstep) + " args='" + args.args + "' params='" + args.params + "'" + " define='" + args.define + "'") cfgdir = "$WALLY/config" srcdir = "$WALLY/src" @@ -85,7 +86,7 @@ PARAM_OVERRIDES=" -parameters " + wkdir + "/param_overrides.txt " # Simulation commands OUTPUT="sim_out" -VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF -suppress +warn -sverilog +vc -Mupdate -line -full64 -lca -ntb_opts sensitive_dyn " + "-top " + args.tb + PARAM_OVERRIDES + INCLUDE_PATH # Disabled Debug flags; add them back for a GUI mode -debug_access+all+reverse -kdb +vcs+vcdpluson +VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF -suppress +warn -sverilog +vc -Mupdate -line -full64 -lca -ntb_opts sensitive_dyn " + "-top " + args.tb + " " + args.define + " " + PARAM_OVERRIDES + INCLUDE_PATH # Disabled Debug flags; add them back for a GUI mode -debug_access+all+reverse -kdb +vcs+vcdpluson VCS = VCS_CMD + " -Mdir=" + wkdir + " " + srcdir + "/cvw.sv " + LOCKSTEP_OPTIONS + " " + COV_OPTIONS + " " + RTL_FILES + " -o " + wkdir + "/" + OUTPUT + " -work " + wkdir + " -Mlib=" + wkdir + " -l " + logdir + "/" + args.config + "_" + args.testsuite + ".log" SIMV_CMD= wkdir + "/" + OUTPUT + " +TEST=" + args.testsuite + " " + args.args + " -no_save " + LOCKSTEP_SIMV From 410c279396e764f18d9110b8079272e43e4d931c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 8 Dec 2024 01:55:15 -0800 Subject: [PATCH 175/212] add --define support to verilator --- sim/verilator/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile index 666516c2d..ecb6b5f42 100644 --- a/sim/verilator/Makefile +++ b/sim/verilator/Makefile @@ -13,6 +13,7 @@ VERILATOR_DIR=${WALLY}/sim/verilator SOURCE=${WALLY}/config/shared/*.vh ${WALLY}/config/${WALLYCONF} ${WALLY}/config/deriv/${WALLYCONF} ${WALLY}/src/cvw.sv ${WALLY}/testbench/*.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv PLUS_ARGS= PARAM_ARGS= +DEFINE_ARGS= EXPANDED_PARAM_ARGS:=$(patsubst %,-G%,$(PARAM_ARGS)) WALLYCONF?=rv64gc @@ -63,6 +64,7 @@ $(WORKDIR)/V${TESTBENCH}: $(DEPENDENCIES) --top-module ${TESTBENCH} --relative-includes \ $(INCLUDE_PATH) \ ${WRAPPER} \ + ${DEFINE_ARGS} \ ${EXPANDED_PARAM_ARGS} \ $(SOURCES) @@ -75,6 +77,7 @@ obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF): $(DEPENDENCIES) --top-module ${TESTBENCH} --relative-includes \ $(INCLUDE_PATH) \ ${WRAPPER} \ + ${DEFINE_ARGS} \ ${EXPANDED_PARAM_ARGS} \ $(SOURCES) From fe4a0c1b7b9b82d2257c3cdc65ebec7b0a328d19 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 8 Dec 2024 02:47:04 -0800 Subject: [PATCH 176/212] Move most of the fcov defines and args into wsim --- bin/wsim | 11 ++++++++--- sim/questa/wally.do | 13 +++---------- sim/vcs/run_vcs | 2 +- 3 files changed, 12 insertions(+), 14 deletions(-) diff --git a/bin/wsim b/bin/wsim index acb5cec76..3c7bdc554 100755 --- a/bin/wsim +++ b/bin/wsim @@ -81,6 +81,7 @@ def prepSim(args, ElfFile): paramsList = [] argsList = [] flagsList = [] + defineList = [] if args.vcd: paramsList.append("MAKE_VCD=1") if args.rvvi: @@ -95,15 +96,19 @@ def prepSim(args, ElfFile): flagsList.append("--ccov") if args.fcov: flagsList.append("--fcov") + defineList.append("+define+INCLUDE_TRACE2COV", "+define+IDV_INCLUDE_TRACE2COV", "+define+COVER_BASE_RV32I") # COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but does not affect tests + argsList.append("+TRACE2COV_ENABLE=1", "+IDV_TRACE2COV=1") if args.gui: flagsList.append("--gui") if args.lockstep or args.lockstepverbose: flagsList.append("--lockstep") if args.lockstep or args.lockstepverbose or args.fcov: prefix = lockstepSetup(args) + defineList.append("+define+USE_IMPERAS_DV") # Combine into a single string args.args += " ".join(argsList) args.params += " ".join(paramsList) + args.define += " ".join(defineList) flags = " ".join(flagsList) return flags, prefix @@ -140,7 +145,7 @@ def runQuesta(args, flags, prefix): if args.define != "": args.define = fr'--define \"{args.define}\"' # Questa cannot accept more than 9 arguments. fcov implies lockstep - cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {flags}" + cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {args.define} {flags}" cmd = f'cd $WALLY/sim/questa; {prefix} vsim {"-c" if not args.gui else ""} -do "{cmd}"' print(f"Running Questa with command: {cmd}") os.system(cmd) @@ -157,13 +162,13 @@ def runVCS(args, flags, prefix): args.params = f'--params "{args.params}"' if args.define != "": args.define = f'--define "{args.define}"' - cmd = f"cd $WALLY/sim/vcs; {prefix} ./run_vcs {args.config} {args.testsuite} --tb {args.tb} {args.args} {args.params} {flags}" + cmd = f"cd $WALLY/sim/vcs; {prefix} ./run_vcs {args.config} {args.testsuite} --tb {args.tb} {args.args} {args.params} {args.define} {flags}" print(cmd) os.system(cmd) def main(args): validateArgs(args) - print(f"Config={args.config} tests={args.testsuite} sim={args.sim} gui={args.gui} args='{args.args}' params='{args.params}'") + print(f"Config={args.config} tests={args.testsuite} sim={args.sim} gui={args.gui} args='{args.args}' params='{args.params}' define='{args.define}'") ElfFile = elfFileCheck(args) flags, prefix = prepSim(args, ElfFile) createDirs(args.sim) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 639539e02..34cafeb77 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -62,7 +62,6 @@ set CoverageVsimArg "" set FunctCoverage 0 set FCvlog "" -set FCvopt "" set lockstep 0 set lockstepvlog "" @@ -105,20 +104,14 @@ if {[lcheck lst "--ccov"]} { # if --fcov found set flag and remove from list if {[lcheck lst "--fcov"]} { set FunctCoverage 1 - # COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but no longer affects tests - set FCvlog "+define+INCLUDE_TRACE2COV \ - +define+IDV_INCLUDE_TRACE2COV \ - +define+COVER_BASE_RV32I \ - +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source" - set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1" + set FCvlog "+incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source" } # if --lockstep or --fcov found set flag and remove from list if {[lcheck lst "--lockstep"] || $FunctCoverage == 1} { set IMPERAS_HOME $::env(IMPERAS_HOME) set lockstep 1 - set lockstepvlog "+define+USE_IMPERAS_DV \ - +incdir+${IMPERAS_HOME}/ImpPublic/include/host \ + set lockstepvlog "+incdir+${IMPERAS_HOME}/ImpPublic/include/host \ +incdir+${IMPERAS_HOME}/ImpProprietary/include/host \ ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/*.sv \ ${IMPERAS_HOME}/ImpProprietary/source/host/idv/*.sv" @@ -174,7 +167,7 @@ vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}{$DefineArgs} {*}${FCvlo # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} {*}${ExpandedParamArgs} -o testbenchopt ${CoverageVoptArg} -vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} {*}${PlusArgs} -fatal 7 {*}${SVLib} {*}${FCvopt} -suppress 3829 ${CoverageVsimArg} +vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} {*}${PlusArgs} -fatal 7 {*}${SVLib} -suppress 3829 ${CoverageVsimArg} # power add generates the logging necessary for saif generation. # power add -r /dut/core/* diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs index 7e2c7aca8..e062205ae 100755 --- a/sim/vcs/run_vcs +++ b/sim/vcs/run_vcs @@ -59,7 +59,7 @@ INCLUDE_PATH="+incdir+" + cfgdir + "/" + args.config + " +incdir+" + cfgdir + "/ # lockstep mode if (args.lockstep): - LOCKSTEP_OPTIONS = " +define+USE_IMPERAS_DV +incdir+$IMPERAS_HOME/ImpPublic/include/host +incdir+$IMPERAS_HOME/ImpProprietary/include/host $IMPERAS_HOME/ImpPublic/source/host/rvvi/*.sv $IMPERAS_HOME/ImpProprietary/source/host/idv/*.sv " + tbdir + "/common/wallyTracer.sv" + LOCKSTEP_OPTIONS = " +incdir+$IMPERAS_HOME/ImpPublic/include/host +incdir+$IMPERAS_HOME/ImpProprietary/include/host $IMPERAS_HOME/ImpPublic/source/host/rvvi/*.sv $IMPERAS_HOME/ImpProprietary/source/host/idv/*.sv " + tbdir + "/common/wallyTracer.sv" LOCKSTEP_SIMV = "-sv_lib $IMPERAS_HOME/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model" else: LOCKSTEP_OPTIONS = "" From 922bdb5cca695ce5ff73948981de26a67a7e1767 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 8 Dec 2024 02:50:25 -0800 Subject: [PATCH 177/212] Fix typo --- sim/questa/wally.do | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 34cafeb77..31599fcdd 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -161,7 +161,7 @@ if {$DEBUG > 0} { # because vsim will run vopt set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv32_priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}" set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv" -vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}{$DefineArgs} {*}${FCvlog} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 +vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${DefineArgs} {*}${FCvlog} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals From b58ab831e7f1c23f69e0d67ab0eea58c3bc7a476 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 8 Dec 2024 14:20:55 -0800 Subject: [PATCH 178/212] more cleanup --- bin/wsim | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/bin/wsim b/bin/wsim index 3c7bdc554..051d32ce2 100755 --- a/bin/wsim +++ b/bin/wsim @@ -55,7 +55,7 @@ def elfFileCheck(args): ElfFile = "" if os.path.isfile(args.elf): ElfFile = f"+ElfFile={os.path.abspath(args.elf)}" - elif args.elf != "": + elif args.elf: print(f"ELF file not found: {args.elf}") sys.exit(1) elif args.testsuite.endswith('.elf'): # No --elf argument; check if testsuite has a .elf extension and use that instead @@ -138,11 +138,11 @@ def runSim(args, flags, prefix): def runQuesta(args, flags, prefix): # Force Questa to use 64-bit mode, sometimes it defaults to 32-bit even on 64-bit machines prefix = "MTI_VCO_MODE=64 " + prefix - if args.args != "": + if args.args: args.args = fr'--args \"{args.args}\"' - if args.params != "": + if args.params: args.params = fr'--params \"{args.params}\"' - if args.define != "": + if args.define: args.define = fr'--define \"{args.define}\"' # Questa cannot accept more than 9 arguments. fcov implies lockstep cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {args.define} {flags}" @@ -156,11 +156,11 @@ def runVerilator(args): def runVCS(args, flags, prefix): print(f"Running VCS on {args.config} {args.testsuite}") - if args.args != "": + if args.args: args.args = f'--args "{args.args}"' - if args.params != "": + if args.params: args.params = f'--params "{args.params}"' - if args.define != "": + if args.define: args.define = f'--define "{args.define}"' cmd = f"cd $WALLY/sim/vcs; {prefix} ./run_vcs {args.config} {args.testsuite} --tb {args.tb} {args.args} {args.params} {args.define} {flags}" print(cmd) From 33904cffe27a97013d98923da469b258afa91fd0 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 8 Dec 2024 17:05:44 -0800 Subject: [PATCH 179/212] Fix wsim fcov --- bin/wsim | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wsim b/bin/wsim index 051d32ce2..a89a546b7 100755 --- a/bin/wsim +++ b/bin/wsim @@ -96,8 +96,8 @@ def prepSim(args, ElfFile): flagsList.append("--ccov") if args.fcov: flagsList.append("--fcov") - defineList.append("+define+INCLUDE_TRACE2COV", "+define+IDV_INCLUDE_TRACE2COV", "+define+COVER_BASE_RV32I") # COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but does not affect tests - argsList.append("+TRACE2COV_ENABLE=1", "+IDV_TRACE2COV=1") + defineList.extend(["+define+INCLUDE_TRACE2COV", "+define+IDV_INCLUDE_TRACE2COV", "+define+COVER_BASE_RV32I"]) # COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but does not affect tests + argsList.extend(["+TRACE2COV_ENABLE=1", "+IDV_TRACE2COV=1"]) if args.gui: flagsList.append("--gui") if args.lockstep or args.lockstepverbose: From 9c19321bdb4a078c843475b84db17b115411753a Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 8 Dec 2024 17:13:31 -0800 Subject: [PATCH 180/212] Update fcov incdirs for wally.do --- sim/questa/wally.do | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 31599fcdd..be47abb4f 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -104,7 +104,10 @@ if {[lcheck lst "--ccov"]} { # if --fcov found set flag and remove from list if {[lcheck lst "--fcov"]} { set FunctCoverage 1 - set FCvlog "+incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source" + set FCvlog "+incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source \ + +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 \ + +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/rv32_priv \ + +incdir+${FCRVVI}/common +incdir+${FCRVVI}" } # if --lockstep or --fcov found set flag and remove from list @@ -159,7 +162,7 @@ if {$DEBUG > 0} { # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv32_priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}" +set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared" set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv" vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${DefineArgs} {*}${FCvlog} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 From 19136c0851a77ad8a1589fb897b42e925a4631bc Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 8 Dec 2024 04:50:22 -0800 Subject: [PATCH 181/212] Begin refactoring run_vcs script --- sim/questa/wally.do | 2 +- sim/vcs/run_vcs | 42 +++++++++++++++++++++--------------------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index be47abb4f..3c7046a37 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -3,7 +3,7 @@ # # Modification by Oklahoma State University & Harvey Mudd College # Use with Testbench -# James Stine, 2008; David Harris 2021 +# James Stine, 2008; David Harris 2021; Jordan Carlin 2024 # Go Cowboys!!!!!! # # Takes 1:10 to run RV64IC tests using gui diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs index e062205ae..7aa0a44e6 100755 --- a/sim/vcs/run_vcs +++ b/sim/vcs/run_vcs @@ -2,6 +2,7 @@ # run_vcs # David_Harris@hmc.edu 2 July 2024 +# Modified Jordan Carlin jcarlin@hmc.edu Dec 9 2024 # Run VCS on a given file, passing appropriate flags # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 @@ -33,7 +34,7 @@ parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and comp # GUI not yet implemented #parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true") args = parser.parse_args() -print("run_vcs Config=" + args.config + " tests=" + args.testsuite + " lockstep=" + str(args.lockstep) + " args='" + args.args + "' params='" + args.params + "'" + " define='" + args.define + "'") +print(f"run_vcs Config={args.config} tests={args.testsuite} lockstep={args.lockstep} args='{args.args}' params='{args.params}' define='{args.define}'") cfgdir = "$WALLY/config" srcdir = "$WALLY/src" @@ -42,20 +43,20 @@ wkdir = "$WALLY/sim/vcs/wkdir/" + args.config + "_" + args.testsuite covdir = "$WALLY/sim/vcs/cov/" + args.config + "_" + args.testsuite logdir = "$WALLY/sim/vcs/logs" -os.system("mkdir -p " + wkdir) -os.system("mkdir -p " + covdir) -os.system("mkdir -p " + logdir) +os.makedirs(wkdir, exist_ok=True) +os.makedirs(covdir, exist_ok=True) +os.makedirs(logdir, exist_ok=True) # Find RTL source files -rtlsrc_cmd = "find " + srcdir + ' -name "*.sv" ! -path "' + srcdir + '/generic/mem/rom1p1r_128x64.sv" ! -path "' + srcdir + '/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "' + srcdir + '/generic/mem/rom1p1r_128x32.sv" ! -path "' + srcdir + '/generic/mem/ram2p1r1wbe_2048x64.sv"' +rtlsrc_cmd = f'find {srcdir} -name "*.sv" ! -path "{srcdir}/generic/mem/rom1p1r_128x64.sv" ! -path "{srcdir}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "{srcdir}/generic/mem/rom1p1r_128x32.sv" ! -path "{srcdir}/generic/mem/ram2p1r1wbe_2048x64.sv"' rtlsrc_files = runfindcmd(rtlsrc_cmd) -tbcommon_cmd = 'find ' + tbdir+'/common -name "*.sv" ! -path "' + tbdir+'/common/wallyTracer.sv"' +tbcommon_cmd = f'find {tbdir}/common -name "*.sv" ! -path "{tbdir}/common/wallyTracer.sv"' tbcommon_files = runfindcmd(tbcommon_cmd) -tb_file = tbdir + "/" + args.tb + ".sv" -RTL_FILES = tb_file + ' ' + str(rtlsrc_files) + ' ' + str(tbcommon_files) +tb_file = f'{tbdir}/{args.tb}.sv' +RTL_FILES = f"{tb_file} {rtlsrc_files} {tbcommon_files}" # Include directories -INCLUDE_PATH="+incdir+" + cfgdir + "/" + args.config + " +incdir+" + cfgdir + "/deriv/" + args.config + " +incdir+" + cfgdir + "/shared +incdir+$WALLY/tests +incdir+" + tbdir + " +incdir+" + srcdir +INCLUDE_PATH=f"+incdir+{cfgdir}/{args.config} +incdir+{cfgdir}/deriv/{args.config} +incdir+{cfgdir}/shared +incdir+$WALLY/tests +incdir+{tbdir} +incdir+{srcdir}" # lockstep mode if (args.lockstep): @@ -67,7 +68,7 @@ else: # coverage mode if (args.ccov): - COV_OPTIONS = "-cm line+cond+branch+fsm+tgl -cm_log " + wkdir + "/coverage.log -cm_dir " + wkdir + "/coverage" + COV_OPTIONS = f"-cm line+cond+branch+fsm+tgl -cm_log {wkdir}/coverage.log -cm_dir {wkdir}/coverage" else: COV_OPTIONS = "" @@ -75,25 +76,24 @@ else: f = open(os.path.expandvars(wkdir) + "/param_overrides.txt", "w") for param in args.params.split(): [param, value] = param.split("=") - if "\\'" in value: # for bit values - value = value.replace("\\'", "'") + if fr"\'" in value: # for bit values + value = value.replace(rf"\'", "'") else: # for strings - value = "\"" + value + "\"" - # print("param=" + param + " value=" + value) - f.write("assign " + value + " " + args.tb + "/" + param + "\n") + value = f'"{value}"' + f.write(f"assign {value} {args.tb}/{param}\n") f.close() -PARAM_OVERRIDES=" -parameters " + wkdir + "/param_overrides.txt " +PARAM_OVERRIDES=f" -parameters {wkdir}/param_overrides.txt " # Simulation commands OUTPUT="sim_out" -VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF -suppress +warn -sverilog +vc -Mupdate -line -full64 -lca -ntb_opts sensitive_dyn " + "-top " + args.tb + " " + args.define + " " + PARAM_OVERRIDES + INCLUDE_PATH # Disabled Debug flags; add them back for a GUI mode -debug_access+all+reverse -kdb +vcs+vcdpluson -VCS = VCS_CMD + " -Mdir=" + wkdir + " " + srcdir + "/cvw.sv " + LOCKSTEP_OPTIONS + " " + COV_OPTIONS + " " + RTL_FILES + " -o " + wkdir + "/" + OUTPUT + " -work " + wkdir + " -Mlib=" + wkdir + " -l " + logdir + "/" + args.config + "_" + args.testsuite + ".log" -SIMV_CMD= wkdir + "/" + OUTPUT + " +TEST=" + args.testsuite + " " + args.args + " -no_save " + LOCKSTEP_SIMV +VCS_CMD=f"vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF -suppress +warn -sverilog +vc -Mupdate -line -full64 -lca -ntb_opts sensitive_dyn -top {args.tb} {args.define} {PARAM_OVERRIDES} {INCLUDE_PATH}" # Disabled Debug flags; add them back for a GUI mode -debug_access+all+reverse -kdb +vcs+vcdpluson +VCS = f'{VCS_CMD} -Mdir={wkdir} {srcdir}/cvw.sv {LOCKSTEP_OPTIONS} {COV_OPTIONS} {RTL_FILES} -o {wkdir}/{OUTPUT} -work {wkdir} -Mlib={wkdir} -l {logdir}/{args.config}_{args.testsuite}.log' +SIMV_CMD= f'wkdir/{OUTPUT} +TEST={args.testsuite} {args.args} -no_save {LOCKSTEP_SIMV}' # Run simulation -print("Executing: " + str(VCS) ) +print(f"Executing: {VCS}") subprocess.run(VCS, shell=True) subprocess.run(SIMV_CMD, shell=True) if (args.ccov): - COV_RUN = "urg -dir " + wkdir + "/coverage.vdb -format text -report IndividualCovReport/" + args.config + "_" + args.testsuite + COV_RUN = f"urg -dir {wkdir}/coverage.vdb -format text -report IndividualCovReport/{args.config}_{args.testsuite}" subprocess.run(COV_RUN, shell=True) From 12966c33b5b9437178832021751a3b7d5fc65534 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 8 Dec 2024 18:18:34 -0800 Subject: [PATCH 182/212] initial attempt at totally refactored run_vcs script --- sim/vcs/run_vcs | 165 +++++++++++++++++++++++++++--------------------- 1 file changed, 93 insertions(+), 72 deletions(-) diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs index 7aa0a44e6..a9041e650 100755 --- a/sim/vcs/run_vcs +++ b/sim/vcs/run_vcs @@ -6,94 +6,115 @@ # Run VCS on a given file, passing appropriate flags # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 - import argparse import os import subprocess +import sys + +# Global variables +WALLY = os.environ.get('WALLY') +simdir = f"{WALLY}/sim/vcs" +cfgdir = f"{WALLY}/config" +srcdir = f"{WALLY}/src" +tbdir = f"{WALLY}/testbench" +logdir = f"{simdir}/logs" # run a Linux command and return the result as a string in a form that VCS can use -def runfindcmd(cmd): -# print("Executing: " + str(cmd) ) - res = subprocess.check_output(cmd, shell=True) +def runFindCommand(cmd): + res = subprocess.check_output(cmd, shell=True, ) res = str(res) res = res.replace("\\n", " ") # replace newline with space res = res.replace("\'", "") # strip off quotation marks res = res[1:] # strip off leading b from byte string return res -parser = argparse.ArgumentParser() -parser.add_argument("config", help="Configuration file") -parser.add_argument("testsuite", help="Test suite (or none, when running a single ELF file) ") -parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench") -parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true") -parser.add_argument("--fcov", "-f", help="Functional Coverage", action="store_true") -parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="") -parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="") -parser.add_argument("--define", "-d", help="Optional define macros passed to simulator", default="") -parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true") -# GUI not yet implemented -#parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true") -args = parser.parse_args() -print(f"run_vcs Config={args.config} tests={args.testsuite} lockstep={args.lockstep} args='{args.args}' params='{args.params}' define='{args.define}'") +def parseArgs(): + parser = argparse.ArgumentParser() + parser.add_argument("config", help="Configuration file") + parser.add_argument("testsuite", help="Test suite (or none, when running a single ELF file) ") + parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench") + parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true") + parser.add_argument("--fcov", "-f", help="Functional Coverage", action="store_true") + parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="") + parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="") + parser.add_argument("--define", "-d", help="Optional define macros passed to simulator", default="") + parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true") + #parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true") # GUI not yet implemented + return parser.parse_args() -cfgdir = "$WALLY/config" -srcdir = "$WALLY/src" -tbdir = "$WALLY/testbench" -wkdir = "$WALLY/sim/vcs/wkdir/" + args.config + "_" + args.testsuite -covdir = "$WALLY/sim/vcs/cov/" + args.config + "_" + args.testsuite -logdir = "$WALLY/sim/vcs/logs" +def createDirs(args): + wkdir = f"{simdir}/wkdir/{args.config}_{args.testsuite}" + covdir = f"{simdir}/cov/{args.config}_{args.testsuite}" + os.makedirs(wkdir, exist_ok=True) + os.makedirs(covdir, exist_ok=True) + os.makedirs(logdir, exist_ok=True) + return wkdir, covdir -os.makedirs(wkdir, exist_ok=True) -os.makedirs(covdir, exist_ok=True) -os.makedirs(logdir, exist_ok=True) +def generateFileList(): + rtlsrc_cmd = f'find {srcdir} -name "*.sv" ! -path "{srcdir}/generic/mem/rom1p1r_128x64.sv" ! -path "{srcdir}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "{srcdir}/generic/mem/rom1p1r_128x32.sv" ! -path "{srcdir}/generic/mem/ram2p1r1wbe_2048x64.sv"' + rtlsrc_files = runFindCommand(rtlsrc_cmd) + tbcommon_cmd = f'find {tbdir}/common -name "*.sv" ! -path "{tbdir}/common/wallyTracer.sv"' + tbcommon_files = runFindCommand(tbcommon_cmd) + tb_file = f'{tbdir}/{args.tb}.sv' + return f"{tb_file} {rtlsrc_files} {tbcommon_files}" -# Find RTL source files -rtlsrc_cmd = f'find {srcdir} -name "*.sv" ! -path "{srcdir}/generic/mem/rom1p1r_128x64.sv" ! -path "{srcdir}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "{srcdir}/generic/mem/rom1p1r_128x32.sv" ! -path "{srcdir}/generic/mem/ram2p1r1wbe_2048x64.sv"' -rtlsrc_files = runfindcmd(rtlsrc_cmd) -tbcommon_cmd = f'find {tbdir}/common -name "*.sv" ! -path "{tbdir}/common/wallyTracer.sv"' -tbcommon_files = runfindcmd(tbcommon_cmd) -tb_file = f'{tbdir}/{args.tb}.sv' -RTL_FILES = f"{tb_file} {rtlsrc_files} {tbcommon_files}" +def processArgs(wkdir, args): + compileOptions = [] + simvOptions = [] + if args.lockstep: + compileOptions.extend(["+incdir+$IMPERAS_HOME/ImpPublic/include/host", + "+incdir+$IMPERAS_HOME/ImpProprietary/include/host", + "$IMPERAS_HOME/ImpPublic/source/host/rvvi/*.sv", + "$IMPERAS_HOME/ImpProprietary/source/host/idv/*.sv", + f"{tbdir}/common/wallyTracer.sv"]) + simvOptions.append("-sv_lib $IMPERAS_HOME/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model") + if args.ccov: + compileOptions.extend(["-cm line+cond+branch+fsm+tgl", f"-cm_log {wkdir}/coverage.log", f"-cm_dir {wkdir}/coverage"]) + if args.params: + compileOptions.append(setupParamOverrides(wkdir, args)) + if args.define: + compileOptions.append(args.define) + # if args.gui: + # compileOptions.append("-debug_access+all+reverse -kdb +vcs+vcdpluson") + compileOptions = " ".join(compileOptions) + simvOptions = " ".join(simvOptions) + return compileOptions, simvOptions -# Include directories -INCLUDE_PATH=f"+incdir+{cfgdir}/{args.config} +incdir+{cfgdir}/deriv/{args.config} +incdir+{cfgdir}/shared +incdir+$WALLY/tests +incdir+{tbdir} +incdir+{srcdir}" +def setupParamOverrides(wkdir, args): + paramOverrideFile = os.path.join(wkdir, "param_overrides.txt") + with open(paramOverrideFile, "w") as f: + for param in args.params.split(): + [param, value] = param.split("=") + if fr"\'" in value: # for bit values + value = value.replace(fr"\'", "'") + else: # for strings + value = f'"{value}"' + f.write(f"assign {value} {args.tb}/{param}\n") + return f" -parameters {wkdir}/param_overrides.txt " -# lockstep mode -if (args.lockstep): - LOCKSTEP_OPTIONS = " +incdir+$IMPERAS_HOME/ImpPublic/include/host +incdir+$IMPERAS_HOME/ImpProprietary/include/host $IMPERAS_HOME/ImpPublic/source/host/rvvi/*.sv $IMPERAS_HOME/ImpProprietary/source/host/idv/*.sv " + tbdir + "/common/wallyTracer.sv" - LOCKSTEP_SIMV = "-sv_lib $IMPERAS_HOME/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model" -else: - LOCKSTEP_OPTIONS = "" - LOCKSTEP_SIMV = "" +def setupCommands(wkdir, rtlFiles, compileOptions, simvOptions, args): + includePath=f"+incdir+{cfgdir}/{args.config} +incdir+{cfgdir}/deriv/{args.config} +incdir+{cfgdir}/shared +incdir+$WALLY/tests +incdir+{tbdir} +incdir+{srcdir}" + vcsStandardFlags = "+lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF -suppress +warn -sverilog +vc -Mupdate -line -full64 -lca -ntb_opts sensitive_dyn" + vcsCMD = f"vcs {vcsStandardFlags} -top {args.tb} {compileOptions} -Mdir={wkdir} {includePath} {srcdir}/cvw.sv {rtlFiles} -o {wkdir}/sim_out -work {wkdir} -Mlib={wkdir} -l {logdir}/{args.config}_{args.testsuite}.log" + simvCMD = f"{wkdir}/sim_out +TEST={args.testsuite} {args.args} -no_save {simvOptions}" + return vcsCMD, simvCMD -# coverage mode -if (args.ccov): - COV_OPTIONS = f"-cm line+cond+branch+fsm+tgl -cm_log {wkdir}/coverage.log -cm_dir {wkdir}/coverage" -else: - COV_OPTIONS = "" +def runVCS(wkdir, vcsCMD, simvCMD): + print(f"Executing: {vcsCMD}") + subprocess.run(vcsCMD, shell=True) + subprocess.run(simvCMD, shell=True) + if (args.ccov): + COV_RUN = f"urg -dir {wkdir}/coverage.vdb -format text -report IndividualCovReport/{args.config}_{args.testsuite}" + subprocess.run(COV_RUN, shell=True) -# Write parameter overrides to a file -f = open(os.path.expandvars(wkdir) + "/param_overrides.txt", "w") -for param in args.params.split(): - [param, value] = param.split("=") - if fr"\'" in value: # for bit values - value = value.replace(rf"\'", "'") - else: # for strings - value = f'"{value}"' - f.write(f"assign {value} {args.tb}/{param}\n") -f.close() -PARAM_OVERRIDES=f" -parameters {wkdir}/param_overrides.txt " +def main(args): + print(f"run_vcs Config={args.config} tests={args.testsuite} lockstep={args.lockstep} args='{args.args}' params='{args.params}' define='{args.define}'") + wkdir, covdir = createDirs(args) + rtlFiles = generateFileList() + compileOptions, simvOptions = processArgs(wkdir, args) + vcsCMD, simvCMD = setupCommands(wkdir, rtlFiles, compileOptions, simvOptions) + runVCS(wkdir, vcsCMD, simvCMD) -# Simulation commands -OUTPUT="sim_out" -VCS_CMD=f"vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF -suppress +warn -sverilog +vc -Mupdate -line -full64 -lca -ntb_opts sensitive_dyn -top {args.tb} {args.define} {PARAM_OVERRIDES} {INCLUDE_PATH}" # Disabled Debug flags; add them back for a GUI mode -debug_access+all+reverse -kdb +vcs+vcdpluson -VCS = f'{VCS_CMD} -Mdir={wkdir} {srcdir}/cvw.sv {LOCKSTEP_OPTIONS} {COV_OPTIONS} {RTL_FILES} -o {wkdir}/{OUTPUT} -work {wkdir} -Mlib={wkdir} -l {logdir}/{args.config}_{args.testsuite}.log' -SIMV_CMD= f'wkdir/{OUTPUT} +TEST={args.testsuite} {args.args} -no_save {LOCKSTEP_SIMV}' - -# Run simulation -print(f"Executing: {VCS}") -subprocess.run(VCS, shell=True) -subprocess.run(SIMV_CMD, shell=True) -if (args.ccov): - COV_RUN = f"urg -dir {wkdir}/coverage.vdb -format text -report IndividualCovReport/{args.config}_{args.testsuite}" - subprocess.run(COV_RUN, shell=True) +if __name__ == "__main__": + args = parseArgs() + sys.exit(main(args)) From a9aefc01054c4fcc48f1b709e090b8db98b969fc Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 8 Dec 2024 20:50:08 -0800 Subject: [PATCH 183/212] Small VCS fixes after refactor --- sim/vcs/run_vcs | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs index a9041e650..7437d2725 100755 --- a/sim/vcs/run_vcs +++ b/sim/vcs/run_vcs @@ -53,7 +53,7 @@ def createDirs(args): def generateFileList(): rtlsrc_cmd = f'find {srcdir} -name "*.sv" ! -path "{srcdir}/generic/mem/rom1p1r_128x64.sv" ! -path "{srcdir}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "{srcdir}/generic/mem/rom1p1r_128x32.sv" ! -path "{srcdir}/generic/mem/ram2p1r1wbe_2048x64.sv"' rtlsrc_files = runFindCommand(rtlsrc_cmd) - tbcommon_cmd = f'find {tbdir}/common -name "*.sv" ! -path "{tbdir}/common/wallyTracer.sv"' + tbcommon_cmd = f'find {tbdir}/common -name "*.sv"' tbcommon_files = runFindCommand(tbcommon_cmd) tb_file = f'{tbdir}/{args.tb}.sv' return f"{tb_file} {rtlsrc_files} {tbcommon_files}" @@ -65,8 +65,7 @@ def processArgs(wkdir, args): compileOptions.extend(["+incdir+$IMPERAS_HOME/ImpPublic/include/host", "+incdir+$IMPERAS_HOME/ImpProprietary/include/host", "$IMPERAS_HOME/ImpPublic/source/host/rvvi/*.sv", - "$IMPERAS_HOME/ImpProprietary/source/host/idv/*.sv", - f"{tbdir}/common/wallyTracer.sv"]) + "$IMPERAS_HOME/ImpProprietary/source/host/idv/*.sv"]) simvOptions.append("-sv_lib $IMPERAS_HOME/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model") if args.ccov: compileOptions.extend(["-cm line+cond+branch+fsm+tgl", f"-cm_log {wkdir}/coverage.log", f"-cm_dir {wkdir}/coverage"]) @@ -112,7 +111,7 @@ def main(args): wkdir, covdir = createDirs(args) rtlFiles = generateFileList() compileOptions, simvOptions = processArgs(wkdir, args) - vcsCMD, simvCMD = setupCommands(wkdir, rtlFiles, compileOptions, simvOptions) + vcsCMD, simvCMD = setupCommands(wkdir, rtlFiles, compileOptions, simvOptions, args) runVCS(wkdir, vcsCMD, simvCMD) if __name__ == "__main__": From 421da19b8fd07e64ed87a4466ea8347422fc68b9 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 9 Dec 2024 13:20:11 +0000 Subject: [PATCH 184/212] Bump addins/cvw-arch-verif from `b37edba` to `95f849e` Bumps [addins/cvw-arch-verif](https://github.com/openhwgroup/cvw-arch-verif) from `b37edba` to `95f849e`. - [Commits](https://github.com/openhwgroup/cvw-arch-verif/compare/b37edba7f625cc3bc2b161d03bc1cd90df0fa2e3...95f849e42ef81562376fdc8fc4b91824fe7b5a36) --- updated-dependencies: - dependency-name: addins/cvw-arch-verif dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- addins/cvw-arch-verif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index b37edba7f..95f849e42 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit b37edba7f625cc3bc2b161d03bc1cd90df0fa2e3 +Subproject commit 95f849e42ef81562376fdc8fc4b91824fe7b5a36 From 798f026ae5f0c14087b5f31b4b870e9ac7603a60 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 9 Dec 2024 08:19:57 -0800 Subject: [PATCH 185/212] Added Hello to the README --- README.md | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 0f560f63a..441b277ec 100644 --- a/README.md +++ b/README.md @@ -59,7 +59,18 @@ Then fork and clone the repo, source setup, make the tests and run regression fi ``` -9. Build the tests and run a regression simulation to prove everything is installed. Building tests may take a while. +9. Try compiling the HelloWally program and simulating it on the SystemVerilog with Verilator and on the Spike simulator. + ``` cd examples/C/hello + $ make + $ wsim --sim verilator rv64gc --elf hello + Hello Wally! + 0 1 2 3 4 5 6 7 8 9 + $ spike hello + Hello Wally! + 0 1 2 3 4 5 6 7 8 9 + ``` + +10. Build the tests and run a regression simulation to prove everything is installed. Building tests may take a while. ```bash $ make --jobs From 8cbf73a8bc955ac5c6d307798c4a8d8dde1d9104 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 9 Dec 2024 08:39:00 -0800 Subject: [PATCH 186/212] Cleanup README --- README.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 441b277ec..8b20d6d8f 100644 --- a/README.md +++ b/README.md @@ -60,7 +60,8 @@ Then fork and clone the repo, source setup, make the tests and run regression ``` 9. Try compiling the HelloWally program and simulating it on the SystemVerilog with Verilator and on the Spike simulator. - ``` cd examples/C/hello + ``` + $ cd examples/C/hello $ make $ wsim --sim verilator rv64gc --elf hello Hello Wally! From 66a4655cb9663ed0c52a0969812ef29211b20a7a Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 9 Dec 2024 09:07:35 -0800 Subject: [PATCH 187/212] Initial attempt at Ubuntu derivative distro support, focusing on Linux Mint --- bin/wally-distro-check.sh | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/bin/wally-distro-check.sh b/bin/wally-distro-check.sh index 7a519478a..2f24c3daf 100755 --- a/bin/wally-distro-check.sh +++ b/bin/wally-distro-check.sh @@ -76,10 +76,28 @@ if [[ "$ID" == rhel || "$ID_LIKE" == *rhel* ]]; then elif [[ "$ID" == ubuntu || "$ID_LIKE" == *ubuntu* ]]; then export FAMILY=ubuntu if [ "$ID" != ubuntu ]; then - printf "${WARNING_COLOR}%s%s\n${ENDC}" "For Ubuntu family distros, the Wally installation script has only been tested on standard Ubuntu. Your distro " \ + printf "${WARNING_COLOR}%s%s\n${ENDC}" "For Ubuntu family distros, the Wally installation script is only tested on standard Ubuntu. Your distro " \ "is $PRETTY_NAME. The regular Ubuntu install will be attempted, but there may be issues." + # Ubuntu derivates may use different version numbers. Attempt to derive version from Ubuntu codename + case "$UBUNTU_CODENAME" in + noble) + export UBUNTU_VERSION=24 + ;; + jammy) + export UBUNTU_VERSION=22 + ;; + focal) + export UBUNTU_VERSION=20 + ;; + *) + printf "${FAIL_COLOR}%s\n${ENDC}" "Unable to determine which base Ubuntu version you are using." + exit 1 + ;; + esac + echo "Detected Ubuntu derivative baesd on Ubuntu $UBUNTU_VERSION.04." + else + export UBUNTU_VERSION="${VERSION_ID:0:2}" fi - export UBUNTU_VERSION="${VERSION_ID:0:2}" if (( UBUNTU_VERSION < 20 )); then printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally installation script has only been tested with Ubuntu versions 20.04 LTS, 22.04 LTS, and 24.04 LTS. You have version $VERSION." exit 1 From d592e92575827526993aa3bb0a6d39f565dceac3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 10 Dec 2024 15:53:04 -0800 Subject: [PATCH 188/212] Update platform.yaml --- sim/questa/wally.do | 1 - testbench/trek_files/platform.yaml | 11 +++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 925889350..6c7a422c4 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -140,7 +140,6 @@ if {[lcheck lst "--breker"]} { +incdir+${WALLY}/testbench/trek_files \ ${WALLY}/testbench/trek_files/uvm_output/trek_uvm_pkg.sv" set brekervopt "${WKDIR}.trek_uvm" - # may need to change this path set brekervsim "+TREK_TBX_FILE=${WALLY}/tests/breker/work/${TESTSUITE_NO_ELF}/${TESTSUITE_NO_ELF}.tbx" append SVLib " -sv_lib ${BREKER_HOME}/linux64/lib/libtrek " } diff --git a/testbench/trek_files/platform.yaml b/testbench/trek_files/platform.yaml index 376a25857..7d262f4f0 100644 --- a/testbench/trek_files/platform.yaml +++ b/testbench/trek_files/platform.yaml @@ -159,6 +159,17 @@ trek: doc: >- Verbatim code that will be put into the declaration section of the test. value: |- + volatile uint64_t tohost; + + void __attribute__((noreturn)) tohost_exit(uintptr_t code) + { + tohost = (code << 1) | 1; + while (1); + } + + #undef trek_exit + #define trek_exit(status) tohost_exit(status); + int main(void) { return trek_main(); From 6cff03bd33779d6f4110a2af963cb678d5d68649 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 11 Dec 2024 11:54:39 -0800 Subject: [PATCH 189/212] Breker tests working --- bin/wsim | 3 +++ sim/questa/wally.do | 4 +--- testbench/testbench.sv | 7 ++++++- testbench/trek_files/platform.yaml | 8 +------- tests/breker/Makefile | 10 ++++++++-- 5 files changed, 19 insertions(+), 13 deletions(-) diff --git a/bin/wsim b/bin/wsim index bf346f348..9798be167 100755 --- a/bin/wsim +++ b/bin/wsim @@ -111,7 +111,10 @@ def prepSim(args, ElfFile): prefix = lockstepSetup(args) defineList.append("+define+USE_IMPERAS_DV") if "breker" in ElfFile: + ElfFileNoExtension = os.path.splitext(args.testsuite)[0] flagsList.append("--breker") + defineList.append("+define+USE_TREK_DV") + argsList.append(f"+TREK_TBX_FILE={WALLY}/tests/breker/work/{ElfFileNoExtension}/{ElfFileNoExtension}.tbx") # Combine into a single string args.args += " ".join(argsList) args.params += " ".join(paramsList) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 93ad81842..9647e1946 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -132,11 +132,9 @@ if {[lcheck lst "--lockstep"] || $FunctCoverage == 1} { if {[lcheck lst "--breker"]} { set breker 1 set BREKER_HOME $::env(BREKER_HOME) - set brekervlog "+define+USE_TREK_DV \ - +incdir+${WALLY}/testbench/trek_files \ + set brekervlog "+incdir+${WALLY}/testbench/trek_files \ ${WALLY}/testbench/trek_files/uvm_output/trek_uvm_pkg.sv" set brekervopt "${WKDIR}.trek_uvm" - set brekervsim "+TREK_TBX_FILE=${WALLY}/tests/breker/work/${TESTSUITE_NO_ELF}/${TESTSUITE_NO_ELF}.tbx" append SVLib " -sv_lib ${BREKER_HOME}/linux64/lib/libtrek " } diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 4ee405a22..43a01e5c8 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -419,7 +419,11 @@ module testbench; end else if (TEST == "coverage64gc") begin $display("%s ran. Coverage tests don't get checked", tests[test]); end else if (ElfFile != "none") begin - $display("Single Elf file tests are not signatured verified."); + `ifdef USE_TREK_DV + $display("Breker test is done."); + `else + $display("Single Elf file tests are not signatured verified."); + `endif `ifdef QUESTA $stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug `else @@ -696,6 +700,7 @@ module testbench; always @(posedge clk) begin // if (reset) PrevPCZero <= 0; // else if (dut.core.InstrValidM) PrevPCZero <= (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0); + // $display("PCE: %0h IEUAdrM: %0h Label (tohost): %0h instruction: %s", dut.core.ifu.PCE, dut.core.lsu.IEUAdrM, ProgramAddrLabelArray["tohost"], InstrMName); TestComplete <= ((InstrM == 32'h6f) & dut.core.InstrValidM ) | ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"] & dut.core.lsu.IEUAdrM != 0) & InstrMName == "SW"); // | // (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero)); diff --git a/testbench/trek_files/platform.yaml b/testbench/trek_files/platform.yaml index 7d262f4f0..44a965789 100644 --- a/testbench/trek_files/platform.yaml +++ b/testbench/trek_files/platform.yaml @@ -159,13 +159,7 @@ trek: doc: >- Verbatim code that will be put into the declaration section of the test. value: |- - volatile uint64_t tohost; - - void __attribute__((noreturn)) tohost_exit(uintptr_t code) - { - tohost = (code << 1) | 1; - while (1); - } + extern void tohost_exit(int status); #undef trek_exit #define trek_exit(status) tohost_exit(status); diff --git a/tests/breker/Makefile b/tests/breker/Makefile index bd21b8b22..77002dfb1 100644 --- a/tests/breker/Makefile +++ b/tests/breker/Makefile @@ -11,10 +11,15 @@ CONSTRAINT_FILES := $(shell find $(CONSTRAINTS_DIR) -type f) TREKEXE_FLAGS += --seed 0x # free (0x) or lock (0x1) the seed used for test generation TREKSVIP = source $(TREKFILES)/breker-setup.sh && treksvip -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) $(TREKEXE_FLAGS) +EXAMPLES_LIB = $(WALLY)/examples/C/common + +# -nostdlib -static -lm -fno-tree-loop-distribute-patterns + # Compilation paths and variables MARCH :=-march=rv64gc_zcb_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh_svinval MABI :=-mabi=lp64d -LINKER := $(WALLY)/tests/custom/linker8000-0000.x +LINKER := $(EXAMPLES_LIB)/test.ld +# $(WALLY)/tests/custom/linker8000-0000.x LINK_FLAGS := -nostartfiles CFLAGS := -Wa,-alhs -Wa,-L -mcmodel=medany -Og -DSINGLE_CPU CRT0_DIR := $(WALLY)/tests/custom/crt0 @@ -33,7 +38,8 @@ $(TESTDIR)/%: $(CONSTRAINTS_DIR)/%.yaml | $(TESTDIR) # Compile c code .PRECIOUS: %.elf %.elf: %.c $(CRT0_DIR)/libcrt0.a - riscv64-unknown-elf-gcc $(MARCH) $(MABI) $(CFLAGS) $(LINK_FLAGS) -g -o $@ $< -L$(CRT0_DIR) -lcrt0 -T $(LINKER) > /dev/null + riscv64-unknown-elf-gcc $(MARCH) $(MABI) $(CFLAGS) $(LINK_FLAGS) -g -o $@ $< -T $(LINKER) -I$(EXAMPLES_LIB) $(EXAMPLES_LIB)/crt.S $(EXAMPLES_LIB)/syscalls.c> /dev/null +# riscv64-unknown-elf-gcc $(MARCH) $(MABI) $(CFLAGS) $(LINK_FLAGS) -g -o $@ $< -L$(CRT0_DIR) -lcrt0 -T $(LINKER) > /dev/null # Convert elf to hex %.elf.memfile: %.elf From d10082113c5e564407f18e3fb5a0137fea335b77 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 11 Dec 2024 15:26:10 -0800 Subject: [PATCH 190/212] Update wsim commands in README --- README.md | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/README.md b/README.md index 8b20d6d8f..32b93d36d 100644 --- a/README.md +++ b/README.md @@ -227,26 +227,28 @@ This utility will take up approximately 100 GB on your hard drive. You can also wsim runs one of multiple simulators, Questa, VCS, or Verilator using a specific configuration and either a suite of tests or a specific elf file. The general syntax is -`wsim [--options]` +`wsim [--options]` Parameters and options: ``` -h, --help show this help message and exit +--elf ELF, -e ELF ELF File name; use if name does not end in .elf --sim {questa,verilator,vcs}, -s {questa,verilator,vcs} Simulator --tb {testbench,testbench_fp}, -t {testbench,testbench_fp} Testbench --gui, -g Simulate with GUI ---coverage, -c Code & Functional Coverage ---fcov, -f Code & Functional Coverage +--ccov, -c Code Coverage +--fcov, -f Functional Coverage with cvw-arch-verif, implies lockstep --args ARGS, -a ARGS Optional arguments passed to simulator via $value$plusargs +--params PARAMS, -p PARAMS Optional top-level parameter overrides of the form param=value +--define DEFINE, -d DEFINE Optional define macros passed to simulator --vcd, -v Generate testbench.vcd --lockstep, -l Run ImperasDV lock, step, and compare. ---locksteplog LOCKSTEPLOG, -b LOCKSTEPLOG Retired instruction number to be begin logging. ---covlog COVLOG, -d COVLOG Log coverage after n instructions. ---elfext ELFEXT, -e ELFEXT When searching for elf files only includes ones which end in this extension +--lockstepverbose, -lv Run ImperasDV lock, step, and compare with tracing enabled +--rvvi, -r Simulate rvvi hardware interface and ethernet. ``` -Run basic test with questa +Run basic test with Questa ```bash wsim rv64gc arch64i @@ -258,26 +260,26 @@ Run Questa with gui wsim rv64gc wally64priv --gui ``` -Run lockstep against ImperasDV with a single elf file in the gui. Lockstep requires single elf. +Run basic test with Verilator ```bash -wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --gui +wsim rv32i arch32i --sim verilator ``` -Run lockstep against ImperasDV with a single elf file. Compute coverage. +Run lockstep against ImperasDV with a single elf file in the gui. Lockstep requires single elf. ```bash -wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --coverage +wsim rv64gc $WALLY/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --gui ``` -Run lockstep against ImperasDV with directory file. +Run lockstep against ImperasDV with a single elf file. Collect functional coverage. ```bash -wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep +wsim rv64gc $WALLY/addins/cvw-arch-verif/tests/rv64/Zicsr/WALLY-COV-ALL.elf --fcov ``` -Run lockstep against ImperasDV with directory file and specify specific extension. +Run Linux boot simulation in lock step between Wally and ImperasDV ```bash -wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep --elfext ref.elf +wsim buildroot buildroot --args +INSTR_LIMIT=600000000 --lockstep ``` From 5c8455261b27d98ad924c2135a5d232fb5bf9ce1 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 11 Dec 2024 17:50:43 -0800 Subject: [PATCH 191/212] Point to new merged RV32/RV64 unprivileged coverpoints --- sim/questa/wally.do | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index f42bf4930..8b41e9502 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -160,7 +160,7 @@ if {$DEBUG > 0} { # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv32_priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}" +set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/unpriv +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv32_priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}" set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv" vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 From 78e6c43f6af6ec5565c2b7867ba0b1728964565f Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 11 Dec 2024 18:37:01 -0800 Subject: [PATCH 192/212] Enabled coverage for all extensions --- config/rv32gc/coverage.svh | 50 ++++++++++++++++++++++---------------- config/rv64gc/coverage.svh | 50 ++++++++++++++++++++++---------------- 2 files changed, 58 insertions(+), 42 deletions(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 90593e0f5..ccc194a27 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -13,27 +13,35 @@ `define CLINT_BASE 64'h02000000 // Unprivileged extensions -`include "RV32I_coverage.svh" -`include "RV32M_coverage.svh" -`include "RV32F_coverage.svh" -`include "RV32D_coverage.svh" -`include "RV32Zba_coverage.svh" -`include "RV32Zbb_coverage.svh" -`include "RV32Zbc_coverage.svh" -`include "RV32Zbs_coverage.svh" -`include "RV32ZfaF_coverage.svh" -`include "RV32ZfaD_coverage.svh" -`include "RV32ZfaZfh_coverage.svh" -`include "RV32ZfhD_coverage.svh" -`include "RV32Zfh_coverage.svh" -`include "RV32Zicond_coverage.svh" -`include "RV32Zca_coverage.svh" -`include "RV32Zcb_coverage.svh" -`include "RV32ZcbM_coverage.svh" -`include "RV32ZcbZbb_coverage.svh" -`include "RV32Zcf_coverage.svh" -`include "RV32Zcd_coverage.svh" -`include "RV32Zicsr_coverage.svh" +`include "I_coverage.svh" +`include "M_coverage.svh" +`include "F_coverage.svh" +`include "D_coverage.svh" +`include "Zba_coverage.svh" +`include "Zbb_coverage.svh" +`include "Zbc_coverage.svh" +`include "Zbs_coverage.svh" +`include "ZfaF_coverage.svh" +`include "ZfaD_coverage.svh" +`include "ZfaZfh_coverage.svh" +`include "Zfh_coverage.svh" +`include "ZfhD_coverage.svh" +`include "Zicond_coverage.svh" +`include "Zca_coverage.svh" +`include "Zcb_coverage.svh" +`include "ZcbM_coverage.svh" +`include "ZcbZbb_coverage.svh" +`include "Zcf_coverage.svh" +`include "Zcd_coverage.svh" +`include "Zicsr_coverage.svh" +`include "Zbkb_coverage.svh" +`include "Zbkc_coverage.svh" +`include "Zbkx_coverage.svh" +`include "Zknd_coverage.svh" +`include "Zkne_coverage.svh" +`include "Zknh_coverage.svh" +`include "Zaamo_coverage.svh" +`include "Zalrsc_coverage.svh" // Privileged extensions `include "ZicsrM_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 6aba1ac9a..d0ec96fb8 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -13,27 +13,35 @@ `define CLINT_BASE 64'h02000000 // Unprivileged extensions -`include "RV64I_coverage.svh" -`include "RV64M_coverage.svh" -`include "RV64F_coverage.svh" -`include "RV64D_coverage.svh" -`include "RV64Zba_coverage.svh" -`include "RV64Zbb_coverage.svh" -`include "RV64Zbc_coverage.svh" -`include "RV64Zbs_coverage.svh" -`include "RV64ZfaF_coverage.svh" -`include "RV64ZfaD_coverage.svh" -`include "RV64ZfaZfh_coverage.svh" -`include "RV64ZfhD_coverage.svh" -`include "RV64Zfh_coverage.svh" -`include "RV64Zicond_coverage.svh" -`include "RV64Zca_coverage.svh" -`include "RV64Zcb_coverage.svh" -`include "RV64ZcbM_coverage.svh" -`include "RV64ZcbZbb_coverage.svh" -`include "RV64ZcbZba_coverage.svh" -`include "RV64Zcd_coverage.svh" -`include "RV64Zicsr_coverage.svh" +`include "I_coverage.svh" +`include "M_coverage.svh" +`include "F_coverage.svh" +`include "D_coverage.svh" +`include "Zba_coverage.svh" +`include "Zbb_coverage.svh" +`include "Zbc_coverage.svh" +`include "Zbs_coverage.svh" +`include "ZfaF_coverage.svh" +`include "ZfaD_coverage.svh" +`include "ZfaZfh_coverage.svh" +`include "ZfhD_coverage.svh" +`include "Zfh_coverage.svh" +`include "Zicond_coverage.svh" +`include "Zca_coverage.svh" +`include "Zcb_coverage.svh" +`include "ZcbM_coverage.svh" +`include "ZcbZbb_coverage.svh" +`include "ZcbZba_coverage.svh" +`include "Zcd_coverage.svh" +`include "Zicsr_coverage.svh" +`include "Zbkb_coverage.svh" +`include "Zbkc_coverage.svh" +`include "Zbkx_coverage.svh" +`include "Zknd_coverage.svh" +`include "Zkne_coverage.svh" +`include "Zknh_coverage.svh" +`include "Zaamo_coverage.svh" +`include "Zalrsc_coverage.svh" // Privileged extensions `include "RV64VM_coverage.svh" From 2d3ff200b4c76dce1a74926938e579c2393b727d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 11 Dec 2024 21:56:40 -0800 Subject: [PATCH 193/212] Fix regression-wally --fcov --- sim/questa/wally.do | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 3c7046a37..1b3c19393 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -104,10 +104,10 @@ if {[lcheck lst "--ccov"]} { # if --fcov found set flag and remove from list if {[lcheck lst "--fcov"]} { set FunctCoverage 1 - set FCvlog "+incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source \ - +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 \ + set FCvlog "+incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 \ +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/rv32_priv \ - +incdir+${FCRVVI}/common +incdir+${FCRVVI}" + +incdir+${FCRVVI}/common +incdir+${FCRVVI} \ + +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source" } # if --lockstep or --fcov found set flag and remove from list @@ -164,7 +164,7 @@ if {$DEBUG > 0} { # because vsim will run vopt set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared" set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv" -vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${DefineArgs} {*}${FCvlog} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 +vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${DefineArgs} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals From d525cc25d8cda1239802b0c5ebca477462cdc8e1 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 11 Dec 2024 13:57:51 -0800 Subject: [PATCH 194/212] Cleanup --- sim/questa/wally.do | 4 +--- testbench/testbench.sv | 1 - tests/breker/Makefile | 35 +++++++++++++---------------------- 3 files changed, 14 insertions(+), 26 deletions(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 9647e1946..f3977e167 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -37,7 +37,6 @@ onerror {quit -f} # Initialize variables set CFG ${1} set TESTSUITE ${2} -set TESTSUITE_NO_ELF [file rootname ${TESTSUITE}] set TESTBENCH ${3} set WKDIR wkdir/${CFG}_${TESTSUITE} set WALLY $::env(WALLY) @@ -67,7 +66,6 @@ set FCvlog "" set breker 0 set brekervlog "" set brekervopt "" -set brekervsim "" set lockstep 0 set lockstepvlog "" @@ -188,7 +186,7 @@ vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${DefineArgs} {*}${FCvlo # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt $accFlag ${WKDIR}.${TESTBENCH} ${brekervopt} -work ${WKDIR} {*}${ExpandedParamArgs} -o testbenchopt ${CoverageVoptArg} -vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} {*}${PlusArgs} -fatal 7 {*}${SVLib} {*}${brekervsim} -suppress 3829 ${CoverageVsimArg} +vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} {*}${PlusArgs} -fatal 7 {*}${SVLib} -suppress 3829 ${CoverageVsimArg} # power add generates the logging necessary for saif generation. # power add -r /dut/core/* diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 43a01e5c8..3acd42f1e 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -700,7 +700,6 @@ module testbench; always @(posedge clk) begin // if (reset) PrevPCZero <= 0; // else if (dut.core.InstrValidM) PrevPCZero <= (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0); - // $display("PCE: %0h IEUAdrM: %0h Label (tohost): %0h instruction: %s", dut.core.ifu.PCE, dut.core.lsu.IEUAdrM, ProgramAddrLabelArray["tohost"], InstrMName); TestComplete <= ((InstrM == 32'h6f) & dut.core.InstrValidM ) | ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"] & dut.core.lsu.IEUAdrM != 0) & InstrMName == "SW"); // | // (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero)); diff --git a/tests/breker/Makefile b/tests/breker/Makefile index 77002dfb1..6fe052277 100644 --- a/tests/breker/Makefile +++ b/tests/breker/Makefile @@ -9,21 +9,17 @@ CUSTOMER_YAML := $(TREKFILES)/customer.yaml TREKSVIP_YAML := $(BREKER_HOME)/examples/tutorials/svip/treksvip/yaml/treksvip.yaml CONSTRAINT_FILES := $(shell find $(CONSTRAINTS_DIR) -type f) TREKEXE_FLAGS += --seed 0x # free (0x) or lock (0x1) the seed used for test generation -TREKSVIP = source $(TREKFILES)/breker-setup.sh && treksvip -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) $(TREKEXE_FLAGS) - -EXAMPLES_LIB = $(WALLY)/examples/C/common - -# -nostdlib -static -lm -fno-tree-loop-distribute-patterns +TREKSVIP := source $(TREKFILES)/breker-setup.sh && treksvip -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) $(TREKEXE_FLAGS) # Compilation paths and variables -MARCH :=-march=rv64gc_zcb_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh_svinval -MABI :=-mabi=lp64d -LINKER := $(EXAMPLES_LIB)/test.ld -# $(WALLY)/tests/custom/linker8000-0000.x -LINK_FLAGS := -nostartfiles -CFLAGS := -Wa,-alhs -Wa,-L -mcmodel=medany -Og -DSINGLE_CPU -CRT0_DIR := $(WALLY)/tests/custom/crt0 -WIDTH := 64 +START_LIB_DIR := $(WALLY)/examples/C/common +START_LIB := $(START_LIB_DIR)/crt.S $(START_LIB_DIR)/syscalls.c +MARCH :=-march=rv64gc_zcb_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh_svinval +MABI :=-mabi=lp64d +LINKER := $(START_LIB_DIR)/test.ld +LINK_FLAGS := -nostartfiles +CFLAGS := -Wa,-alhs -Wa,-L -mcmodel=medany -Og -DSINGLE_CPU +WIDTH := 64 # Find all constraint files and generate tests for each one TESTS = $(patsubst $(CONSTRAINTS_DIR)/%.yaml,$(TESTDIR)/%,$(CONSTRAINT_FILES)) @@ -37,9 +33,8 @@ $(TESTDIR)/%: $(CONSTRAINTS_DIR)/%.yaml | $(TESTDIR) # Compile c code .PRECIOUS: %.elf -%.elf: %.c $(CRT0_DIR)/libcrt0.a - riscv64-unknown-elf-gcc $(MARCH) $(MABI) $(CFLAGS) $(LINK_FLAGS) -g -o $@ $< -T $(LINKER) -I$(EXAMPLES_LIB) $(EXAMPLES_LIB)/crt.S $(EXAMPLES_LIB)/syscalls.c> /dev/null -# riscv64-unknown-elf-gcc $(MARCH) $(MABI) $(CFLAGS) $(LINK_FLAGS) -g -o $@ $< -L$(CRT0_DIR) -lcrt0 -T $(LINKER) > /dev/null +%.elf: %.c + riscv64-unknown-elf-gcc $(MARCH) $(MABI) $(CFLAGS) $(LINK_FLAGS) -T$(LINKER) -I$(START_LIB_DIR) $(START_LIB) -g -o $@ $< > /dev/null # Convert elf to hex %.elf.memfile: %.elf @@ -48,12 +43,8 @@ $(TESTDIR)/%: $(CONSTRAINTS_DIR)/%.yaml | $(TESTDIR) extractFunctionRadix.sh $<.objdump # View the model graph TODO: What does this do? Move to another makefile? -%.view_graph:% - $(TREKSVIP) -p ../tests/test_$^.yaml -p $(CUSTOMER_YAML) -t pss_top.entry - -# Library needed for C code -$(CRT0_DIR)/libcrt0.a: - make -C $(CRT0_DIR) +%.view_graph: $(CONSTRAINTS_DIR)/%.yaml + $(TREKSVIP) -p $(CONSTRAINTS_DIR)/$^.yaml -p $(CUSTOMER_YAML) -t pss_top.entry $(TESTDIR): mkdir -p $(TESTDIR) From 785b817f93d047796e53e7079946fad128d19ebf Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 14 Dec 2024 21:08:33 -0800 Subject: [PATCH 195/212] Update platform.yaml --- testbench/trek_files/platform.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/testbench/trek_files/platform.yaml b/testbench/trek_files/platform.yaml index 44a965789..d7f7b8dad 100644 --- a/testbench/trek_files/platform.yaml +++ b/testbench/trek_files/platform.yaml @@ -55,7 +55,7 @@ trek: doc: >- Name of the memory region base: - value: 0x82000000 + value: 0x83000000 doc: >- Base address of memory region. Ignored for `static` initialized memory @@ -108,13 +108,13 @@ trek: - backdoor - frontdoor c2t_base: - value: 0x83000000 + value: 0x82000000 doc: >- Fixed base address of C to trekbox mailbox region. Allow 64 bytes per processor. Used for init_type of `backdoor` and `frontdoor` only. t2c_base: - value: 0x83001000 + value: 0x82001000 doc: >- Fixed base address of trekbox to C mailbox region. Allow 64 bytes per processor. From 1025548a3aaa1b200dab62f8ee3a1f32356fab7b Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 16 Dec 2024 14:02:24 +0000 Subject: [PATCH 196/212] Bump addins/cvw-arch-verif from `95f849e` to `efd70ce` Bumps [addins/cvw-arch-verif](https://github.com/openhwgroup/cvw-arch-verif) from `95f849e` to `efd70ce`. - [Commits](https://github.com/openhwgroup/cvw-arch-verif/compare/95f849e42ef81562376fdc8fc4b91824fe7b5a36...efd70ce71a352eb8c4ca3d3b63d06a7b076078cb) --- updated-dependencies: - dependency-name: addins/cvw-arch-verif dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- addins/cvw-arch-verif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index 95f849e42..efd70ce71 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit 95f849e42ef81562376fdc8fc4b91824fe7b5a36 +Subproject commit efd70ce71a352eb8c4ca3d3b63d06a7b076078cb From 036e0e0727f602e978fd2634b97c39c383827ad6 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 18 Dec 2024 11:49:51 -0800 Subject: [PATCH 197/212] Update wally.do to handle more arguments --- sim/questa/wally.do | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 218be69bc..626d02837 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -8,7 +8,7 @@ # # Takes 1:10 to run RV64IC tests using gui -# Usage: do wally.do [--ccov] [--fcov] [--gui] [--args "any number of +value"] [--params "any number of VAR=VAL parameter overrides"] +# Usage: do wally.do [--ccov] [--fcov] [--gui] [--args "any number of +value"] [--params "any number of VAR=VAL parameter overrides"] [--define "any number of +define+VAR=VAL"] # Example: do wally.do rv64gc arch64i testbench # Use this wally.do file to run this example. @@ -72,20 +72,23 @@ set accFlag "" # Need to be able to pass arguments to vopt. Unforunately argv does not work because # it takes on different values if vsim and the do file are called from the command line or -# if the do file is called from questa sim directly. This chunk of code uses the $4 through $n -# variables and compacts into a single list for passing to vopt. -set from 4 -set step 1 +# if the do file is called from questa sim directly. This chunk of code uses the $n variables +# and compacts them into a single list for passing to vopt. Shift is used to move the arguments +# through the list. set lst {} +echo "number of args = $argc" -for {set i 0} true {incr i} { - set x [expr {$i*$step + $from}] - if {$x > $argc} break - set arg [expr "$$x"] - lappend lst $arg +# Shift off the first three arguments (config, testcases, testbench) +shift +shift +shift + +# Copy the remaining arguments into a list +while {$argc > 0} { + lappend lst [expr "\$1"] + shift } -echo "number of args = $argc" echo "lst = $lst" # if +acc found set flag and remove from list From 5b666e4c5c34d0bcbe329b1258a4b7a076c5e0f1 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 18 Dec 2024 23:33:29 -0800 Subject: [PATCH 198/212] Fix makefile SHELL directive --- testbench/trek_files/Makefile | 1 + tests/breker/Makefile | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/testbench/trek_files/Makefile b/testbench/trek_files/Makefile index 34409e0ae..08c916ced 100644 --- a/testbench/trek_files/Makefile +++ b/testbench/trek_files/Makefile @@ -1,3 +1,4 @@ +SHELL := /bin/bash TREKFILES := $(WALLY)/testbench/trek_files PLATFORM_YAML := $(TREKFILES)/platform.yaml TREKSVIP_YAML := $(BREKER_HOME)/examples/tutorials/svip/treksvip/yaml/treksvip.yaml diff --git a/tests/breker/Makefile b/tests/breker/Makefile index 6fe052277..bdb26bf87 100644 --- a/tests/breker/Makefile +++ b/tests/breker/Makefile @@ -1,4 +1,4 @@ -shell := /bin/bash +SHELL := /bin/bash # Breker/Trek paths and variables TESTDIR := $(WALLY)/tests/breker/work From 53b5c9557a1c85442cb533f0d97ec40ccb929517 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 19 Dec 2024 12:40:31 -0800 Subject: [PATCH 199/212] Suppress warnings in Breker simulations --- sim/questa/wally.do | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 211a1e3ff..bb3ba8a4b 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -183,7 +183,7 @@ if {$DEBUG > 0} { # because vsim will run vopt set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared" set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv" -vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${DefineArgs} {*}${lockstepvlog} {*}${brekervlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 +vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${DefineArgs} {*}${lockstepvlog} {*}${brekervlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286,2605,2250 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals From 2818bdbaa83453310bc5fe3acf431d843ec8cd26 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 19 Dec 2024 12:51:51 -0800 Subject: [PATCH 200/212] Refactor Elf eile handling for better Breker compatibility --- bin/wsim | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/bin/wsim b/bin/wsim index 9798be167..c7c0bc508 100755 --- a/bin/wsim +++ b/bin/wsim @@ -57,13 +57,13 @@ def validateArgs(args): def elfFileCheck(args): ElfFile = "" if os.path.isfile(args.elf): - ElfFile = f"+ElfFile={os.path.abspath(args.elf)}" + ElfFile = os.path.abspath(args.elf) elif args.elf: print(f"ELF file not found: {args.elf}") sys.exit(1) elif args.testsuite.endswith('.elf'): # No --elf argument; check if testsuite has a .elf extension and use that instead if os.path.isfile(args.testsuite): - ElfFile = f"+ElfFile={os.path.abspath(args.testsuite)}" + ElfFile = os.path.abspath(args.testsuite) # extract the elf name from the path to be the test suite fields = args.testsuite.rsplit('/', 3) # if the name is just ref.elf in a deep path (riscv-arch-test/wally-riscv-arch-test), then use the directory name as the test suite to make it unique; otherwise work directory will have duplicates. @@ -94,7 +94,7 @@ def prepSim(args, ElfFile): if args.tb == "testbench_fp": paramsList.append(f'TEST="{args.testsuite}"') if ElfFile: - argsList.append(f"{ElfFile}") + argsList.append(f"+ElfFile={ElfFile}") if args.gui and args.tb == "testbench": paramsList.append("DEBUG=1") if args.ccov: @@ -110,11 +110,11 @@ def prepSim(args, ElfFile): if args.lockstep or args.lockstepverbose or args.fcov: prefix = lockstepSetup(args) defineList.append("+define+USE_IMPERAS_DV") - if "breker" in ElfFile: - ElfFileNoExtension = os.path.splitext(args.testsuite)[0] + if args.config == "breker": + ElfFileNoExtension = os.path.splitext(ElfFile)[0] flagsList.append("--breker") defineList.append("+define+USE_TREK_DV") - argsList.append(f"+TREK_TBX_FILE={WALLY}/tests/breker/work/{ElfFileNoExtension}/{ElfFileNoExtension}.tbx") + argsList.append(f"+TREK_TBX_FILE={ElfFileNoExtension}.tbx") # Combine into a single string args.args += " ".join(argsList) args.params += " ".join(paramsList) From 7c297af0eb37f777f34ee778e378c347a421e016 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 19 Dec 2024 13:04:42 -0800 Subject: [PATCH 201/212] Cleanup --- bin/wsim | 2 +- testbench/trek_files/Makefile | 2 +- tests/breker/Makefile | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/bin/wsim b/bin/wsim index c7c0bc508..7dca19edd 100755 --- a/bin/wsim +++ b/bin/wsim @@ -50,7 +50,7 @@ def validateArgs(args): elif (args.tb == "testbench_fp" and args.sim != "questa"): print("Error: testbench_fp presently only supported by Questa, not VCS or Verilator, because of a touchy testbench") sys.exit(1) - elif ("breker" in args.elf or "breker" in args.testsuite) and args.sim != "questa": + elif (args.config == "breker" and args.sim != "questa"): print("Error: Breker tests currently only supported by Questa") sys.exit(1) diff --git a/testbench/trek_files/Makefile b/testbench/trek_files/Makefile index 08c916ced..62a045af2 100644 --- a/testbench/trek_files/Makefile +++ b/testbench/trek_files/Makefile @@ -1,4 +1,4 @@ -SHELL := /bin/bash +SHELL := /bin/bash TREKFILES := $(WALLY)/testbench/trek_files PLATFORM_YAML := $(TREKFILES)/platform.yaml TREKSVIP_YAML := $(BREKER_HOME)/examples/tutorials/svip/treksvip/yaml/treksvip.yaml diff --git a/tests/breker/Makefile b/tests/breker/Makefile index bdb26bf87..fc56d8805 100644 --- a/tests/breker/Makefile +++ b/tests/breker/Makefile @@ -18,7 +18,7 @@ MARCH :=-march=rv64gc_zcb_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_z MABI :=-mabi=lp64d LINKER := $(START_LIB_DIR)/test.ld LINK_FLAGS := -nostartfiles -CFLAGS := -Wa,-alhs -Wa,-L -mcmodel=medany -Og -DSINGLE_CPU +CFLAGS := -Wa,-alhs -Wa,-L -mcmodel=medany -Og -DSINGLE_CPU WIDTH := 64 # Find all constraint files and generate tests for each one From 73e90847d977ddfd4a0c0c89d771d3a8857ab733 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 19 Dec 2024 14:09:42 -0800 Subject: [PATCH 202/212] Update Breker documentation --- Makefile | 1 + bin/regression-wally | 2 +- bin/wsim | 2 +- config/derivlist.txt | 2 ++ sim/questa/wally.do | 1 + testbench/testbench.sv | 1 + testbench/trek_files/README.md | 9 +++++++++ tests/breker/README.md | 18 ++++++++++++++++++ 8 files changed, 34 insertions(+), 2 deletions(-) create mode 100644 testbench/trek_files/README.md create mode 100644 tests/breker/README.md diff --git a/Makefile b/Makefile index f52fd943d..b03edea98 100644 --- a/Makefile +++ b/Makefile @@ -39,6 +39,7 @@ coverage: cvw-arch-verif: $(MAKE) -C ${WALLY}/addins/cvw-arch-verif +# Requires a license for the Breker tool. See tests/breker/README.md for details breker: $(MAKE) -C ${WALLY}/testbench/trek_files $(MAKE) -C ${WALLY}/tests/breker diff --git a/bin/regression-wally b/bin/regression-wally index e119422b1..c89e80dcd 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -401,7 +401,7 @@ parser.add_argument("--nightly", help="Run large nightly regression", action="st parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true") parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true") parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true") # Currently not used -parser.add_argument("--breker", help="Run Breker tests", action="store_true") +parser.add_argument("--breker", help="Run Breker tests", action="store_true") # Requires a license for the breker tool. See tests/breker/README.md for details parser.add_argument("--dryrun", help="Print commands invoked to console without running regression", action="store_true") args = parser.parse_args() diff --git a/bin/wsim b/bin/wsim index 7dca19edd..843d4cfe6 100755 --- a/bin/wsim +++ b/bin/wsim @@ -110,7 +110,7 @@ def prepSim(args, ElfFile): if args.lockstep or args.lockstepverbose or args.fcov: prefix = lockstepSetup(args) defineList.append("+define+USE_IMPERAS_DV") - if args.config == "breker": + if args.config == "breker": # Requires a license for the breker tool. See tests/breker/README.md for details ElfFileNoExtension = os.path.splitext(ElfFile)[0] flagsList.append("--breker") defineList.append("+define+USE_TREK_DV") diff --git a/config/derivlist.txt b/config/derivlist.txt index 76f09ebf4..c83fd60ec 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -1432,6 +1432,8 @@ UART_SUPPORTED 0 PLIC_SUPPORTED 0 SPI_SUPPORTED 0 +# Breker tests require a different memory configuration +# See tests/breker/README.md for details on the testsuite derive breker rv64gc EXT_MEM_SUPPORTED 1 EXT_MEM_BASE 64'h90000000 diff --git a/sim/questa/wally.do b/sim/questa/wally.do index bb3ba8a4b..945cb6ef4 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -130,6 +130,7 @@ if {[lcheck lst "--lockstep"] || $FunctCoverage == 1} { } # if --breker found set flag and remove from list +# Requires a license for the breker tool. See tests/breker/README.md for details if {[lcheck lst "--breker"]} { set breker 1 set BREKER_HOME $::env(BREKER_HOME) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 3acd42f1e..4a40e1e87 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -46,6 +46,7 @@ module testbench; parameter RVVI_SYNTH_SUPPORTED=0; parameter MAKE_VCD=0; + // TREK Requires a license for the Breker tool. See tests/breker/README.md for details `ifdef USE_TREK_DV event trek_start; always @(testbench.trek_start) begin diff --git a/testbench/trek_files/README.md b/testbench/trek_files/README.md new file mode 100644 index 000000000..1c7c14b38 --- /dev/null +++ b/testbench/trek_files/README.md @@ -0,0 +1,9 @@ +Jordan Carlin, jcarlin@hmc.edu, December 2024 + +# Breker Trek Tests Support Files for CVW + +[Breker's Trek Test Suite](https://brekersystems.com/products/trek-suite/) is a proprietary set of tests that require a license to use (this license is not generally available to noncommercial users). + +This directory contains the support files necessary to run Breker's Trek Tests on CVW. For additional details on the tests see [`$WALLY/tests/breker/README.md`](../../tests/breker/README.md) + +To generate the Breker support files (with a license), run `make` in the `testbench/trek_files` directory (this one). Before running, make sure to set `$BREKER_HOME` in your system's `site-setup.sh` file. This Makefile only needs to be run once. diff --git a/tests/breker/README.md b/tests/breker/README.md new file mode 100644 index 000000000..300ebc16e --- /dev/null +++ b/tests/breker/README.md @@ -0,0 +1,18 @@ +Jordan Carlin, jcarlin@hmc.edu, December 2024 + +# Breker Tests for CVW + +[Breker's Trek Test Suite](https://brekersystems.com/products/trek-suite/) is a proprietary set of tests that require a license to use (this license is not generally available to noncommercial users). + +To generate the Breker tests (with a license), run `make` in both the `tests/breker` and `testbench/trek_files` directories. Alternatively, running `make breker` from the top-level `$WALLY` directory will run both of these. Before running, make sure to set `$BREKER_HOME` in your system's `site-setup.sh` file. The `testbench/trek_files` Makefile only needs to be run once, but the tests that are generated can be different each time so rerunning the `tests/breker` Makefile is worthwhile. + +This will generate a testsuite for each of the constraint yaml files in the `constraints` directory. These generated tests are produced in the `tests/breker/work` directory. To run a single test use `wsim` to run the elf. The `breker` configuration must be used. For example, + +```bash +$ wsim breker $WALLY/tests/breker/riscv/riscv.elf +``` + +To run all of the generated Breker tests use +```bash +$ regression-wally --breker +``` From ab663e5bc87e94b5b394fe6905f15dacc91d9d8c Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Fri, 20 Dec 2024 02:14:57 -0800 Subject: [PATCH 203/212] Updating WallyTracer for VM signals --- testbench/common/wallyTracer.sv | 75 ++++++++++++++++++++------------- 1 file changed, 46 insertions(+), 29 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index f74fb3d06..b59ba14b7 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -45,6 +45,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic InstrValidM, InstrValidW; logic StallE, StallM, StallW; logic GatedStallW; + logic SelHPTW; logic FlushD, FlushE, FlushM, FlushW; logic TrapM, TrapW; logic HaltM, HaltW; @@ -66,11 +67,11 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic InterruptM, InterruptW; //For VM Verification - logic [(P.XLEN-1):0] VAdrIM,VAdrDM,VAdrIW,VAdrDW; - logic [(P.XLEN-1):0] PTE_iM,PTE_dM,PTE_iW,PTE_dW; - logic [(P.PA_BITS-1):0] PAIM,PADM,PAIW,PADW; - logic [(P.PPN_BITS-1):0] PPN_iM,PPN_dM,PPN_iW,PPN_dW; - logic [1:0] PageType_iM, PageType_iW, PageType_dM, PageType_dW; + logic [(P.XLEN-1):0] VAdr_iF,VAdr_iD,VAdr_iE,VAdr_iM,VAdr_iW,VAdr_dM,VAdr_dW; + logic [(P.XLEN-1):0] PTE_iF,PTE_iD,PTE_iE,PTE_iM,PTE_iW,PTE_dM,PTE_dW; + logic [(P.PA_BITS-1):0] PA_iF,PA_iD,PA_iE,PA_iM,PA_iW,PA_dM,PA_dW; + logic [(P.PPN_BITS-1):0] PPN_iF,PPN_iD,PPN_iE,PPN_iM,PPN_iW,PPN_dM,PPN_dW; + logic [1:0] PageType_iF, PageType_iD, PageType_iE, PageType_iM, PageType_iW, PageType_dM, PageType_dW; logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW; logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW; @@ -91,7 +92,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign StallE = testbench.dut.core.StallE; assign StallM = testbench.dut.core.StallM; assign StallW = testbench.dut.core.StallW; - assign GatedStallW = testbench.dut.core.lsu.GatedStallW; + assign GatedStallW = testbench.dut.core.lsu.GatedStallW; + assign SelHPTW = testbench.dut.core.lsu.hptw.hptw.SelHPTW; assign FlushD = testbench.dut.core.FlushD; assign FlushE = testbench.dut.core.FlushE; assign FlushM = testbench.dut.core.FlushM; @@ -113,18 +115,18 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end //For VM Verification - assign VAdrIM = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr; - assign VAdrDM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr; - assign PAIM = testbench.dut.core.ifu.immu.immu.PhysicalAddress; - assign PADM = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress; + assign VAdr_iF = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr; + assign VAdr_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr; + assign PA_iF = testbench.dut.core.ifu.immu.immu.PhysicalAddress; + assign PA_dM = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress; assign ReadAccessM = testbench.dut.core.lsu.dmmu.dmmu.ReadAccessM; assign WriteAccessM = testbench.dut.core.lsu.dmmu.dmmu.WriteAccessM; assign ExecuteAccessF = testbench.dut.core.ifu.immu.immu.ExecuteAccessF; - assign PTE_iM = testbench.dut.core.ifu.immu.immu.PTE; + assign PTE_iF = testbench.dut.core.ifu.immu.immu.PTE; assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE; - assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; + assign PPN_iF = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; - assign PageType_iM = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal; + assign PageType_iF = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal; assign PageType_dM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal; logic valid; @@ -360,28 +362,43 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(1) CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW); //for VM Verification - flopenrc #(P.XLEN) VAdrIWReg (clk, reset, FlushW, ~StallW, VAdrIM, VAdrIW); //Virtual Address for IMMU - flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW); //Virtual Address for DMMU + flopenrc #(P.XLEN) VAdr_iDReg (clk, reset, 1'b0, SelHPTW, VAdr_iF, VAdr_iD); //Virtual Address for IMMU + flopenrc #(P.XLEN) VAdr_iEReg (clk, reset, 1'b0, ~StallE, VAdr_iD, VAdr_iE); //Virtual Address for IMMU + flopenrc #(P.XLEN) VAdr_iMReg (clk, reset, 1'b0, ~StallM, VAdr_iE, VAdr_iM); //Virtual Address for IMMU + flopenrc #(P.XLEN) VAdr_iWReg (clk, reset, 1'b0, SelHPTW, VAdr_iM, VAdr_iW); //Virtual Address for IMMU + flopenrc #(P.XLEN) VAdr_dWReg (clk, reset, 1'b0, SelHPTW, VAdr_dM, VAdr_dW); //Virtual Address for DMMU - flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW); //Physical Address for IMMU - flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW); //Physical Address for DMMU + flopenrc #(P.PA_BITS) PA_iDReg (clk, reset, 1'b0, SelHPTW, PA_iF, PA_iD); //Physical Address for IMMU + flopenrc #(P.PA_BITS) PA_iEReg (clk, reset, 1'b0, ~StallE, PA_iD, PA_iE); //Physical Address for IMMU + flopenrc #(P.PA_BITS) PA_iMReg (clk, reset, 1'b0, ~StallM, PA_iE, PA_iM); //Physical Address for IMMU + flopenrc #(P.PA_BITS) PA_iWReg (clk, reset, 1'b0, SelHPTW, PA_iM, PA_iW); //Physical Address for IMMU + flopenrc #(P.PA_BITS) PA_dWReg (clk, reset, 1'b0, SelHPTW, PA_dM, PA_dW); //Physical Address for DMMU - flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~GatedStallW, PTE_iM, PTE_iW); //PTE for IMMU - flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~GatedStallW, PTE_dM, PTE_dW); //PTE for DMMU + flopenrc #(P.XLEN) PTE_iDReg (clk, reset, 1'b0, SelHPTW, PTE_iF, PTE_iD); //PTE for IMMU + flopenrc #(P.XLEN) PTE_iEReg (clk, reset, 1'b0, ~StallE, PTE_iD, PTE_iE); //PTE for IMMU + flopenrc #(P.XLEN) PTE_iMReg (clk, reset, 1'b0, ~StallM, PTE_iE, PTE_iM); //PTE for IMMU + flopenrc #(P.XLEN) PTE_iWReg (clk, reset, 1'b0, SelHPTW, PTE_iM, PTE_iW); //PTE for IMMU + flopenrc #(P.XLEN) PTE_dWReg (clk, reset, 1'b0, SelHPTW, PTE_dM, PTE_dW); //PTE for DMMU - flopenrc #(2) PageType_iWReg (clk, reset, FlushW, ~GatedStallW, PageType_iM, PageType_iW); //Page Type (kilo, mega, giga, tera) from IMMU - flopenrc #(2) PageType_dWReg (clk, reset, FlushW, ~GatedStallW, PageType_dM, PageType_dW); //Page Type (kilo, mega, giga, tera) from DMMU + flopenrc #(2) PageType_iDReg (clk, reset, 1'b0, SelHPTW, PageType_iF, PageType_iD); //PageType (kilo, mega, giga, tera) from IMMU + flopenrc #(2) PageType_iEReg (clk, reset, 1'b0, ~StallE, PageType_iD, PageType_iE); //PageType (kilo, mega, giga, tera) from IMMU + flopenrc #(2) PageType_iMReg (clk, reset, 1'b0, ~StallM, PageType_iE, PageType_iM); //PageType (kilo, mega, giga, tera) from IMMU + flopenrc #(2) PageType_iWReg (clk, reset, 1'b0, SelHPTW, PageType_iM, PageType_iW); //PageType (kilo, mega, giga, tera) from IMMU + flopenrc #(2) PageType_dWReg (clk, reset, 1'b0, SelHPTW, PageType_dM, PageType_dW); //PageType (kilo, mega, giga, tera) from DMMU - flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~GatedStallW, PPN_iM, PPN_iW); //Physical Page Number for IMMU - flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~GatedStallW, PPN_dM, PPN_dW); //Physical Page Number for DMMU + flopenrc #(P.PPN_BITS) PPN_iDReg (clk, reset, 1'b0, ~StallD, PPN_iF, PPN_iD); //Physical Page Number for IMMU + flopenrc #(P.PPN_BITS) PPN_iEReg (clk, reset, 1'b0, ~StallE, PPN_iD, PPN_iE); //Physical Page Number for IMMU + flopenrc #(P.PPN_BITS) PPN_iMReg (clk, reset, 1'b0, ~StallM, PPN_iE, PPN_iM); //Physical Page Number for IMMU + flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, 1'b0, ~StallW, PPN_iM, PPN_iW); //Physical Page Number for IMMU + flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, 1'b0, ~StallW, PPN_dM, PPN_dW); //Physical Page Number for DMMU - flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~GatedStallW, ReadAccessM, ReadAccessW); //LoadAccess - flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~GatedStallW, WriteAccessM, WriteAccessW); //StoreAccess + flopenrc #(1) ReadAccessWReg (clk, reset, 1'b0, ~GatedStallW, ReadAccessM, ReadAccessW); //LoadAccess + flopenrc #(1) WriteAccessWReg (clk, reset, 1'b0, ~GatedStallW, WriteAccessM, WriteAccessW); //StoreAccess - flopenrc #(1) ExecuteAccessDReg (clk, reset, FlushE, ~StallD, ExecuteAccessF, ExecuteAccessD); //Instruction Fetch Access - flopenrc #(1) ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE); //Instruction Fetch Access - flopenrc #(1) ExecuteAccessMReg (clk, reset, FlushM, ~StallM, ExecuteAccessE, ExecuteAccessM); //Instruction Fetch Access - flopenrc #(1) ExecuteAccessWReg (clk, reset, FlushW, ~StallW, ExecuteAccessM, ExecuteAccessW); //Instruction Fetch Access + flopenrc #(1) ExecuteAccessDReg (clk, reset, 1'b0, ~StallD, ExecuteAccessF, ExecuteAccessD); //Instruction Fetch Access + flopenrc #(1) ExecuteAccessEReg (clk, reset, 1'b0, ~StallE, ExecuteAccessD, ExecuteAccessE); //Instruction Fetch Access + flopenrc #(1) ExecuteAccessMReg (clk, reset, 1'b0, ~StallM, ExecuteAccessE, ExecuteAccessM); //Instruction Fetch Access + flopenrc #(1) ExecuteAccessWReg (clk, reset, 1'b0, ~StallW, ExecuteAccessM, ExecuteAccessW); //Instruction Fetch Access // Initially connecting the writeback stage signals, but may need to use M stage // and gate on ~FlushW. From f4779534af9b067aa74f1ef3e7768582ab2ae9ac Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 21 Dec 2024 16:03:16 -0800 Subject: [PATCH 204/212] Update a few single bit config parameters to specify type logic --- config/rv32e/config.vh | 6 +++--- config/rv32gc/config.vh | 6 +++--- config/rv32i/config.vh | 6 +++--- config/rv32imc/config.vh | 6 +++--- config/rv64gc/config.vh | 6 +++--- config/rv64i/config.vh | 6 +++--- 6 files changed, 18 insertions(+), 18 deletions(-) diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index db0838550..2ef57632d 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -31,7 +31,7 @@ localparam XLEN = 32'd32; // IEEE 754 compliance -localparam IEEE754 = 0; +localparam logic IEEE754 = 0; // RISC-V configuration per specification // Base instruction set (defaults to I if E is not supported) @@ -156,11 +156,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; localparam logic BOOTROM_SUPPORTED = 1; localparam logic [63:0] BOOTROM_BASE = 64'h00001000; localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b0; +localparam logic BOOTROM_PRELOAD = 1'b0; localparam logic UNCORE_RAM_SUPPORTED = 1; localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam logic UNCORE_RAM_PRELOAD = 1'b0; localparam logic EXT_MEM_SUPPORTED = 0; localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index af2032937..475d3b04b 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -31,7 +31,7 @@ localparam XLEN = 32'd32; // IEEE 754 compliance -localparam IEEE754 = 0; +localparam logic IEEE754 = 0; // RISC-V configuration per specification // Base instruction set (defaults to I if E is not supported) @@ -156,11 +156,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; localparam logic BOOTROM_SUPPORTED = 1; localparam logic [63:0] BOOTROM_BASE = 64'h00001000; localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b0; +localparam logic BOOTROM_PRELOAD = 1'b0; localparam logic UNCORE_RAM_SUPPORTED = 1; localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam logic UNCORE_RAM_PRELOAD = 1'b0; localparam logic EXT_MEM_SUPPORTED = 0; localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index ede534f0b..664256736 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -31,7 +31,7 @@ localparam XLEN = 32'd32; // IEEE 754 compliance -localparam IEEE754 = 0; +localparam logic IEEE754 = 0; // RISC-V configuration per specification // Base instruction set (defaults to I if E is not supported) @@ -156,11 +156,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; localparam logic BOOTROM_SUPPORTED = 0; localparam logic [63:0] BOOTROM_BASE = 64'h00001000; localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b0; +localparam logic BOOTROM_PRELOAD = 1'b0; localparam logic UNCORE_RAM_SUPPORTED = 0; localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam logic UNCORE_RAM_PRELOAD = 1'b0; localparam logic EXT_MEM_SUPPORTED = 0; localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index e9f986a07..4e4751bd8 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -31,7 +31,7 @@ localparam XLEN = 32'd32; // IEEE 754 compliance -localparam IEEE754 = 0; +localparam logic IEEE754 = 0; // RISC-V configuration per specification // Base instruction set (defaults to I if E is not supported) @@ -156,11 +156,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; localparam logic BOOTROM_SUPPORTED = 0; localparam logic [63:0] BOOTROM_BASE = 64'h00001000; localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b0; +localparam logic BOOTROM_PRELOAD = 1'b0; localparam logic UNCORE_RAM_SUPPORTED = 0; localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam logic UNCORE_RAM_PRELOAD = 1'b0; localparam logic EXT_MEM_SUPPORTED = 0; localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index 4f833178a..80b0e9ebd 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -31,7 +31,7 @@ localparam XLEN = 32'd64; // IEEE 754 compliance -localparam IEEE754 = 0; +localparam logic IEEE754 = 0; // RISC-V configuration per specification // Base instruction set (defaults to I if E is not supported) @@ -156,11 +156,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; localparam logic BOOTROM_SUPPORTED = 1; localparam logic [63:0] BOOTROM_BASE = 64'h00001000; localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b0; +localparam logic BOOTROM_PRELOAD = 1'b0; localparam logic UNCORE_RAM_SUPPORTED = 1; localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam logic UNCORE_RAM_PRELOAD = 1'b0; localparam logic EXT_MEM_SUPPORTED = 0; localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 3a8bae1bc..3fdecb458 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -31,7 +31,7 @@ localparam XLEN = 32'd64; // IEEE 754 compliance -localparam IEEE754 = 0; +localparam logic IEEE754 = 0; // RISC-V configuration per specification // Base instruction set (defaults to I if E is not supported) @@ -156,11 +156,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; localparam logic BOOTROM_SUPPORTED = 0; localparam logic [63:0] BOOTROM_BASE = 64'h00001000; localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b0; +localparam logic BOOTROM_PRELOAD = 1'b0; localparam logic UNCORE_RAM_SUPPORTED = 0; localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam logic UNCORE_RAM_PRELOAD = 1'b0; localparam logic EXT_MEM_SUPPORTED = 0; localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; From f7eecdc56e1a178d123917a3ad480a511924ed43 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Sun, 22 Dec 2024 08:40:16 -0800 Subject: [PATCH 205/212] Updating wallyTracer syntax to match wally style --- testbench/common/wallyTracer.sv | 80 ++++++++++++++++----------------- 1 file changed, 40 insertions(+), 40 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index b59ba14b7..3010cfbd9 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -67,11 +67,11 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic InterruptM, InterruptW; //For VM Verification - logic [(P.XLEN-1):0] VAdr_iF,VAdr_iD,VAdr_iE,VAdr_iM,VAdr_iW,VAdr_dM,VAdr_dW; - logic [(P.XLEN-1):0] PTE_iF,PTE_iD,PTE_iE,PTE_iM,PTE_iW,PTE_dM,PTE_dW; - logic [(P.PA_BITS-1):0] PA_iF,PA_iD,PA_iE,PA_iM,PA_iW,PA_dM,PA_dW; - logic [(P.PPN_BITS-1):0] PPN_iF,PPN_iD,PPN_iE,PPN_iM,PPN_iW,PPN_dM,PPN_dW; - logic [1:0] PageType_iF, PageType_iD, PageType_iE, PageType_iM, PageType_iW, PageType_dM, PageType_dW; + logic [(P.XLEN-1):0] IVAdrF,IVAdrD,IVAdrE,IVAdrM,IVAdrW,DVAdrM,DVAdrW; + logic [(P.XLEN-1):0] IPTEF,IPTED,IPTEE,IPTEM,IPTEW,DPTEM,DPTEW; + logic [(P.PA_BITS-1):0] IPAF,IPAD,IPAE,IPAM,IPAW,DPAM,DPAW; + logic [(P.PPN_BITS-1):0] IPPNF,IPPND,IPPNE,IPPNM,IPPNW,DPPNM,DPPNW; + logic [1:0] IPageTypeF, IPageTypeD, IPageTypeE, IPageTypeM, IPageTypeW, DPageTypeM, DPageTypeW; logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW; logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW; @@ -115,19 +115,19 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end //For VM Verification - assign VAdr_iF = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr; - assign VAdr_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr; - assign PA_iF = testbench.dut.core.ifu.immu.immu.PhysicalAddress; - assign PA_dM = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress; + assign IVAdrF = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr; + assign DVAdrM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr; + assign IPAF = testbench.dut.core.ifu.immu.immu.PhysicalAddress; + assign DPAM = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress; assign ReadAccessM = testbench.dut.core.lsu.dmmu.dmmu.ReadAccessM; assign WriteAccessM = testbench.dut.core.lsu.dmmu.dmmu.WriteAccessM; assign ExecuteAccessF = testbench.dut.core.ifu.immu.immu.ExecuteAccessF; - assign PTE_iF = testbench.dut.core.ifu.immu.immu.PTE; - assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE; - assign PPN_iF = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; - assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; - assign PageType_iF = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal; - assign PageType_dM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal; + assign IPTEF = testbench.dut.core.ifu.immu.immu.PTE; + assign DPTEM = testbench.dut.core.lsu.dmmu.dmmu.PTE; + assign IPPNF = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; + assign DPPNM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; + assign IPageTypeF = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal; + assign DPageTypeM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal; logic valid; @@ -362,35 +362,35 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(1) CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW); //for VM Verification - flopenrc #(P.XLEN) VAdr_iDReg (clk, reset, 1'b0, SelHPTW, VAdr_iF, VAdr_iD); //Virtual Address for IMMU - flopenrc #(P.XLEN) VAdr_iEReg (clk, reset, 1'b0, ~StallE, VAdr_iD, VAdr_iE); //Virtual Address for IMMU - flopenrc #(P.XLEN) VAdr_iMReg (clk, reset, 1'b0, ~StallM, VAdr_iE, VAdr_iM); //Virtual Address for IMMU - flopenrc #(P.XLEN) VAdr_iWReg (clk, reset, 1'b0, SelHPTW, VAdr_iM, VAdr_iW); //Virtual Address for IMMU - flopenrc #(P.XLEN) VAdr_dWReg (clk, reset, 1'b0, SelHPTW, VAdr_dM, VAdr_dW); //Virtual Address for DMMU + flopenrc #(P.XLEN) IVAdrDReg (clk, reset, 1'b0, SelHPTW, IVAdrF, IVAdrD); //Virtual Address for IMMU + flopenrc #(P.XLEN) IVAdrEReg (clk, reset, 1'b0, ~StallE, IVAdrD, IVAdrE); //Virtual Address for IMMU + flopenrc #(P.XLEN) IVAdrMReg (clk, reset, 1'b0, ~StallM, IVAdrE, IVAdrM); //Virtual Address for IMMU + flopenrc #(P.XLEN) IVAdrWReg (clk, reset, 1'b0, SelHPTW, IVAdrM, IVAdrW); //Virtual Address for IMMU + flopenrc #(P.XLEN) DVAdrWReg (clk, reset, 1'b0, SelHPTW, DVAdrM, DVAdrW); //Virtual Address for DMMU - flopenrc #(P.PA_BITS) PA_iDReg (clk, reset, 1'b0, SelHPTW, PA_iF, PA_iD); //Physical Address for IMMU - flopenrc #(P.PA_BITS) PA_iEReg (clk, reset, 1'b0, ~StallE, PA_iD, PA_iE); //Physical Address for IMMU - flopenrc #(P.PA_BITS) PA_iMReg (clk, reset, 1'b0, ~StallM, PA_iE, PA_iM); //Physical Address for IMMU - flopenrc #(P.PA_BITS) PA_iWReg (clk, reset, 1'b0, SelHPTW, PA_iM, PA_iW); //Physical Address for IMMU - flopenrc #(P.PA_BITS) PA_dWReg (clk, reset, 1'b0, SelHPTW, PA_dM, PA_dW); //Physical Address for DMMU + flopenrc #(P.PA_BITS) IPADReg (clk, reset, 1'b0, SelHPTW, IPAF, IPAD); //Physical Address for IMMU + flopenrc #(P.PA_BITS) IPAEReg (clk, reset, 1'b0, ~StallE, IPAD, IPAE); //Physical Address for IMMU + flopenrc #(P.PA_BITS) IPAMReg (clk, reset, 1'b0, ~StallM, IPAE, IPAM); //Physical Address for IMMU + flopenrc #(P.PA_BITS) IPAWReg (clk, reset, 1'b0, SelHPTW, IPAM, IPAW); //Physical Address for IMMU + flopenrc #(P.PA_BITS) DPAWReg (clk, reset, 1'b0, SelHPTW, DPAM, DPAW); //Physical Address for DMMU - flopenrc #(P.XLEN) PTE_iDReg (clk, reset, 1'b0, SelHPTW, PTE_iF, PTE_iD); //PTE for IMMU - flopenrc #(P.XLEN) PTE_iEReg (clk, reset, 1'b0, ~StallE, PTE_iD, PTE_iE); //PTE for IMMU - flopenrc #(P.XLEN) PTE_iMReg (clk, reset, 1'b0, ~StallM, PTE_iE, PTE_iM); //PTE for IMMU - flopenrc #(P.XLEN) PTE_iWReg (clk, reset, 1'b0, SelHPTW, PTE_iM, PTE_iW); //PTE for IMMU - flopenrc #(P.XLEN) PTE_dWReg (clk, reset, 1'b0, SelHPTW, PTE_dM, PTE_dW); //PTE for DMMU + flopenrc #(P.XLEN) IPTEDReg (clk, reset, 1'b0, SelHPTW, IPTEF, IPTED); //PTE for IMMU + flopenrc #(P.XLEN) IPTEEReg (clk, reset, 1'b0, ~StallE, IPTED, IPTEE); //PTE for IMMU + flopenrc #(P.XLEN) IPTEMReg (clk, reset, 1'b0, ~StallM, IPTEE, IPTEM); //PTE for IMMU + flopenrc #(P.XLEN) IPTEWReg (clk, reset, 1'b0, SelHPTW, IPTEM, IPTEW); //PTE for IMMU + flopenrc #(P.XLEN) DPTEWReg (clk, reset, 1'b0, SelHPTW, DPTEM, DPTEW); //PTE for DMMU - flopenrc #(2) PageType_iDReg (clk, reset, 1'b0, SelHPTW, PageType_iF, PageType_iD); //PageType (kilo, mega, giga, tera) from IMMU - flopenrc #(2) PageType_iEReg (clk, reset, 1'b0, ~StallE, PageType_iD, PageType_iE); //PageType (kilo, mega, giga, tera) from IMMU - flopenrc #(2) PageType_iMReg (clk, reset, 1'b0, ~StallM, PageType_iE, PageType_iM); //PageType (kilo, mega, giga, tera) from IMMU - flopenrc #(2) PageType_iWReg (clk, reset, 1'b0, SelHPTW, PageType_iM, PageType_iW); //PageType (kilo, mega, giga, tera) from IMMU - flopenrc #(2) PageType_dWReg (clk, reset, 1'b0, SelHPTW, PageType_dM, PageType_dW); //PageType (kilo, mega, giga, tera) from DMMU + flopenrc #(2) IPageTypeDReg (clk, reset, 1'b0, SelHPTW, IPageTypeF, IPageTypeD); //PageType (kilo, mega, giga, tera) from IMMU + flopenrc #(2) IPageTypeEReg (clk, reset, 1'b0, ~StallE, IPageTypeD, IPageTypeE); //PageType (kilo, mega, giga, tera) from IMMU + flopenrc #(2) IPageTypeMReg (clk, reset, 1'b0, ~StallM, IPageTypeE, IPageTypeM); //PageType (kilo, mega, giga, tera) from IMMU + flopenrc #(2) IPageTypeWReg (clk, reset, 1'b0, SelHPTW, IPageTypeM, IPageTypeW); //PageType (kilo, mega, giga, tera) from IMMU + flopenrc #(2) DPageTypeWReg (clk, reset, 1'b0, SelHPTW, DPageTypeM, DPageTypeW); //PageType (kilo, mega, giga, tera) from DMMU - flopenrc #(P.PPN_BITS) PPN_iDReg (clk, reset, 1'b0, ~StallD, PPN_iF, PPN_iD); //Physical Page Number for IMMU - flopenrc #(P.PPN_BITS) PPN_iEReg (clk, reset, 1'b0, ~StallE, PPN_iD, PPN_iE); //Physical Page Number for IMMU - flopenrc #(P.PPN_BITS) PPN_iMReg (clk, reset, 1'b0, ~StallM, PPN_iE, PPN_iM); //Physical Page Number for IMMU - flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, 1'b0, ~StallW, PPN_iM, PPN_iW); //Physical Page Number for IMMU - flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, 1'b0, ~StallW, PPN_dM, PPN_dW); //Physical Page Number for DMMU + flopenrc #(P.PPN_BITS) IPPNDReg (clk, reset, 1'b0, ~StallD, IPPNF, IPPND); //Physical Page Number for IMMU + flopenrc #(P.PPN_BITS) IPPNEReg (clk, reset, 1'b0, ~StallE, IPPND, IPPNE); //Physical Page Number for IMMU + flopenrc #(P.PPN_BITS) IPPNMReg (clk, reset, 1'b0, ~StallM, IPPNE, IPPNM); //Physical Page Number for IMMU + flopenrc #(P.PPN_BITS) IPPNWReg (clk, reset, 1'b0, ~StallW, IPPNM, IPPNW); //Physical Page Number for IMMU + flopenrc #(P.PPN_BITS) DPPNWReg (clk, reset, 1'b0, ~StallW, DPPNM, DPPNW); //Physical Page Number for DMMU flopenrc #(1) ReadAccessWReg (clk, reset, 1'b0, ~GatedStallW, ReadAccessM, ReadAccessW); //LoadAccess flopenrc #(1) WriteAccessWReg (clk, reset, 1'b0, ~GatedStallW, WriteAccessM, WriteAccessW); //StoreAccess From fb642c7f35ba853bfb538e83a2c6c022abf342c6 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 23 Dec 2024 13:50:07 +0000 Subject: [PATCH 206/212] Bump addins/cvw-arch-verif from `efd70ce` to `f04bcd7` Bumps [addins/cvw-arch-verif](https://github.com/openhwgroup/cvw-arch-verif) from `efd70ce` to `f04bcd7`. - [Commits](https://github.com/openhwgroup/cvw-arch-verif/compare/efd70ce71a352eb8c4ca3d3b63d06a7b076078cb...f04bcd729f46d66ff42c31ee8112cd447a5aa0a3) --- updated-dependencies: - dependency-name: addins/cvw-arch-verif dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- addins/cvw-arch-verif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index efd70ce71..f04bcd729 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit efd70ce71a352eb8c4ca3d3b63d06a7b076078cb +Subproject commit f04bcd729f46d66ff42c31ee8112cd447a5aa0a3 From 19495af18a0b9db9e24fb7bd98c57d1ced8624d4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 23 Dec 2024 06:21:22 -0800 Subject: [PATCH 207/212] Added Zfhmin support for functional coverage --- config/rv32gc/coverage.svh | 2 ++ config/rv64gc/coverage.svh | 2 ++ 2 files changed, 4 insertions(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index ccc194a27..789f6ae70 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -26,6 +26,8 @@ `include "ZfaZfh_coverage.svh" `include "Zfh_coverage.svh" `include "ZfhD_coverage.svh" +// Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used. When Zfhmin and D are supported, ZfhD should also be enabled +`include "Zfhmin_coverage.svh" `include "Zicond_coverage.svh" `include "Zca_coverage.svh" `include "Zcb_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index d0ec96fb8..f86f0882f 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -26,6 +26,8 @@ `include "ZfaZfh_coverage.svh" `include "ZfhD_coverage.svh" `include "Zfh_coverage.svh" +// Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used. When Zfhmin and D are supported, ZfhD should also be enabled +`include "Zfhmin_coverage.svh" `include "Zicond_coverage.svh" `include "Zca_coverage.svh" `include "Zcb_coverage.svh" From 45d4bf0f60c7a1046a9fea3cdad0a267ecd848aa Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 23 Dec 2024 06:22:11 -0800 Subject: [PATCH 208/212] Typo fix --- src/mmu/tlb/tlbram.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mmu/tlb/tlbram.sv b/src/mmu/tlb/tlbram.sv index 3b329705d..a252bbd23 100644 --- a/src/mmu/tlb/tlbram.sv +++ b/src/mmu/tlb/tlbram.sv @@ -51,6 +51,6 @@ module tlbram import cvw::*; #(parameter cvw_t P, or_rows #(TLB_ENTRIES, P.XLEN) PTEOr(RamRead, PageTableEntry); // Rename the bits read from the TLB RAM - assign PTEAccessBits = {PageTableEntry[P.XLEN-1:P.XLEN-4] & {4{P.XLEN == 64}}, PageTableEntry[7:0]}; // for RV64 include N and PBMT bits and OR of reserved bitss + assign PTEAccessBits = {PageTableEntry[P.XLEN-1:P.XLEN-4] & {4{P.XLEN == 64}}, PageTableEntry[7:0]}; // for RV64 include N and PBMT bits and OR of reserved bits assign PPN = PageTableEntry[P.PPN_BITS+9:10]; endmodule From 7041d27a46d26263a4dac4526421d6c809202bcd Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 23 Dec 2024 11:03:23 -0600 Subject: [PATCH 209/212] Possible bugs in wallyTracer marked. --- testbench/common/wallyTracer.sv | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 3010cfbd9..77ad800dd 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -362,29 +362,29 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(1) CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW); //for VM Verification - flopenrc #(P.XLEN) IVAdrDReg (clk, reset, 1'b0, SelHPTW, IVAdrF, IVAdrD); //Virtual Address for IMMU + flopenrc #(P.XLEN) IVAdrDReg (clk, reset, 1'b0, SelHPTW, IVAdrF, IVAdrD); //Virtual Address for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD flopenrc #(P.XLEN) IVAdrEReg (clk, reset, 1'b0, ~StallE, IVAdrD, IVAdrE); //Virtual Address for IMMU flopenrc #(P.XLEN) IVAdrMReg (clk, reset, 1'b0, ~StallM, IVAdrE, IVAdrM); //Virtual Address for IMMU - flopenrc #(P.XLEN) IVAdrWReg (clk, reset, 1'b0, SelHPTW, IVAdrM, IVAdrW); //Virtual Address for IMMU - flopenrc #(P.XLEN) DVAdrWReg (clk, reset, 1'b0, SelHPTW, DVAdrM, DVAdrW); //Virtual Address for DMMU + flopenrc #(P.XLEN) IVAdrWReg (clk, reset, 1'b0, SelHPTW, IVAdrM, IVAdrW); //Virtual Address for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW + flopenrc #(P.XLEN) DVAdrWReg (clk, reset, 1'b0, SelHPTW, DVAdrM, DVAdrW); //Virtual Address for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW - flopenrc #(P.PA_BITS) IPADReg (clk, reset, 1'b0, SelHPTW, IPAF, IPAD); //Physical Address for IMMU + flopenrc #(P.PA_BITS) IPADReg (clk, reset, 1'b0, SelHPTW, IPAF, IPAD); //Physical Address for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD flopenrc #(P.PA_BITS) IPAEReg (clk, reset, 1'b0, ~StallE, IPAD, IPAE); //Physical Address for IMMU flopenrc #(P.PA_BITS) IPAMReg (clk, reset, 1'b0, ~StallM, IPAE, IPAM); //Physical Address for IMMU - flopenrc #(P.PA_BITS) IPAWReg (clk, reset, 1'b0, SelHPTW, IPAM, IPAW); //Physical Address for IMMU - flopenrc #(P.PA_BITS) DPAWReg (clk, reset, 1'b0, SelHPTW, DPAM, DPAW); //Physical Address for DMMU + flopenrc #(P.PA_BITS) IPAWReg (clk, reset, 1'b0, SelHPTW, IPAM, IPAW); //Physical Address for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW + flopenrc #(P.PA_BITS) DPAWReg (clk, reset, 1'b0, SelHPTW, DPAM, DPAW); //Physical Address for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW - flopenrc #(P.XLEN) IPTEDReg (clk, reset, 1'b0, SelHPTW, IPTEF, IPTED); //PTE for IMMU + flopenrc #(P.XLEN) IPTEDReg (clk, reset, 1'b0, SelHPTW, IPTEF, IPTED); //PTE for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD flopenrc #(P.XLEN) IPTEEReg (clk, reset, 1'b0, ~StallE, IPTED, IPTEE); //PTE for IMMU flopenrc #(P.XLEN) IPTEMReg (clk, reset, 1'b0, ~StallM, IPTEE, IPTEM); //PTE for IMMU - flopenrc #(P.XLEN) IPTEWReg (clk, reset, 1'b0, SelHPTW, IPTEM, IPTEW); //PTE for IMMU - flopenrc #(P.XLEN) DPTEWReg (clk, reset, 1'b0, SelHPTW, DPTEM, DPTEW); //PTE for DMMU + flopenrc #(P.XLEN) IPTEWReg (clk, reset, 1'b0, SelHPTW, IPTEM, IPTEW); //PTE for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW + flopenrc #(P.XLEN) DPTEWReg (clk, reset, 1'b0, SelHPTW, DPTEM, DPTEW); //PTE for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW - flopenrc #(2) IPageTypeDReg (clk, reset, 1'b0, SelHPTW, IPageTypeF, IPageTypeD); //PageType (kilo, mega, giga, tera) from IMMU + flopenrc #(2) IPageTypeDReg (clk, reset, 1'b0, SelHPTW, IPageTypeF, IPageTypeD); //PageType (kilo, mega, giga, tera) from IMMU // *** RT: possible bug SelHPTW probably should be ~StallD flopenrc #(2) IPageTypeEReg (clk, reset, 1'b0, ~StallE, IPageTypeD, IPageTypeE); //PageType (kilo, mega, giga, tera) from IMMU flopenrc #(2) IPageTypeMReg (clk, reset, 1'b0, ~StallM, IPageTypeE, IPageTypeM); //PageType (kilo, mega, giga, tera) from IMMU - flopenrc #(2) IPageTypeWReg (clk, reset, 1'b0, SelHPTW, IPageTypeM, IPageTypeW); //PageType (kilo, mega, giga, tera) from IMMU - flopenrc #(2) DPageTypeWReg (clk, reset, 1'b0, SelHPTW, DPageTypeM, DPageTypeW); //PageType (kilo, mega, giga, tera) from DMMU + flopenrc #(2) IPageTypeWReg (clk, reset, 1'b0, SelHPTW, IPageTypeM, IPageTypeW); //PageType (kilo, mega, giga, tera) from IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW + flopenrc #(2) DPageTypeWReg (clk, reset, 1'b0, SelHPTW, DPageTypeM, DPageTypeW); //PageType (kilo, mega, giga, tera) from DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW flopenrc #(P.PPN_BITS) IPPNDReg (clk, reset, 1'b0, ~StallD, IPPNF, IPPND); //Physical Page Number for IMMU flopenrc #(P.PPN_BITS) IPPNEReg (clk, reset, 1'b0, ~StallE, IPPND, IPPNE); //Physical Page Number for IMMU From 809b76da22989717f95e28169ee738f961ce326e Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 23 Dec 2024 12:09:57 -0600 Subject: [PATCH 210/212] Updated SDC_RANGE to match FU540 specification. --- config/rv32e/config.vh | 2 +- config/rv32gc/config.vh | 2 +- config/rv32i/config.vh | 2 +- config/rv32imc/config.vh | 2 +- config/rv64gc/config.vh | 2 +- config/rv64i/config.vh | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 2ef57632d..7b0f43913 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -178,7 +178,7 @@ localparam logic [63:0] PLIC_BASE = 64'h0C000000; localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; localparam logic SDC_SUPPORTED = 0; localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam logic [63:0] SDC_RANGE = 64'h00000FFF; localparam logic SPI_SUPPORTED = 0; localparam logic [63:0] SPI_BASE = 64'h10040000; localparam logic [63:0] SPI_RANGE = 64'h00000FFF; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 475d3b04b..14c100a49 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -178,7 +178,7 @@ localparam logic [63:0] PLIC_BASE = 64'h0C000000; localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; localparam logic SDC_SUPPORTED = 0; localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam logic [63:0] SDC_RANGE = 64'h00000FFF; localparam logic SPI_SUPPORTED = 1; localparam logic [63:0] SPI_BASE = 64'h10040000; localparam logic [63:0] SPI_RANGE = 64'h00000FFF; diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 664256736..2eb40c8d4 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -178,7 +178,7 @@ localparam logic [63:0] PLIC_BASE = 64'h0C000000; localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; localparam logic SDC_SUPPORTED = 0; localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam logic [63:0] SDC_RANGE = 64'h00000FFF; localparam logic SPI_SUPPORTED = 0; localparam logic [63:0] SPI_BASE = 64'h10040000; localparam logic [63:0] SPI_RANGE = 64'h00000FFF; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index 4e4751bd8..ec0563316 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -178,7 +178,7 @@ localparam logic [63:0] PLIC_BASE = 64'h0C000000; localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; localparam logic SDC_SUPPORTED = 0; localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam logic [63:0] SDC_RANGE = 64'h00000FFF; localparam logic SPI_SUPPORTED = 1; localparam logic [63:0] SPI_BASE = 64'h10040000; localparam logic [63:0] SPI_RANGE = 64'h00000FFF; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index 80b0e9ebd..9c0bef1a1 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -178,7 +178,7 @@ localparam logic [63:0] PLIC_BASE = 64'h0C000000; localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; localparam logic SDC_SUPPORTED = 0; localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam logic [63:0] SDC_RANGE = 64'h00000FFF; localparam logic SPI_SUPPORTED = 1; localparam logic [63:0] SPI_BASE = 64'h10040000; localparam logic [63:0] SPI_RANGE = 64'h00000FFF; diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 3fdecb458..1779d764d 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -178,7 +178,7 @@ localparam logic [63:0] PLIC_BASE = 64'h0C000000; localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; localparam logic SDC_SUPPORTED = 0; localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam logic [63:0] SDC_RANGE = 64'h00000FFF; localparam logic SPI_SUPPORTED = 0; localparam logic [63:0] SPI_BASE = 64'h10040000; localparam logic [63:0] SPI_RANGE = 64'h00000FFF; From 7d57d83224a0ca2f2268f4a2e200d7c338d5a3ea Mon Sep 17 00:00:00 2001 From: Zain2050 Date: Tue, 24 Dec 2024 01:38:03 -0800 Subject: [PATCH 211/212] made changes for ResEnc in tlbcontrol --- src/mmu/tlb/tlbcontrol.sv | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv index 9bd3b8148..f957e2cf6 100644 --- a/src/mmu/tlb/tlbcontrol.sv +++ b/src/mmu/tlb/tlbcontrol.sv @@ -61,6 +61,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) ( logic TLBAccess; logic ImproperPrivilege; logic BadPBMT, BadNAPOT, BadReserved; + logic ReservedEncoding; logic InvalidAccess; logic PreUpdateDA, PrePageFault; @@ -88,6 +89,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) ( assign BadPBMT = ((PTE_PBMT != 0) & ~(P.SVPBMT_SUPPORTED & ENVCFG_PBMTE)) | PTE_PBMT == 3; // PBMT must be zero if not supported; value of 3 is reserved assign BadNAPOT = PTE_N & (~P.SVNAPOT_SUPPORTED | ~NAPOT4); // N must be be 0 if CVNAPOT is not supported or not 64 KiB contiguous region assign BadReserved = PTE_RESERVED; // Reserved bits must be zero + assign ReservedEncoding = PTE_W & ~PTE_R; // fault on reserved encoding with R=0, W=1 to match ImperasDV behavior // Check whether the access is allowed, page faulting if not. if (ITLB == 1) begin:itlb // Instruction TLB fault checking @@ -95,9 +97,9 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) ( // only execute non-user mode pages. assign ImproperPrivilege = ((PrivilegeModeW == P.U_MODE) & ~PTE_U) | ((PrivilegeModeW == P.S_MODE) & PTE_U); assign PreUpdateDA = ~PTE_A; - assign InvalidAccess = ~PTE_X; + assign InvalidAccess = ~PTE_X | ReservedEncoding; end else begin:dtlb // Data TLB fault checking - logic InvalidRead, InvalidWrite, ReservedEncoding; + logic InvalidRead, InvalidWrite; logic InvalidCBOM, InvalidCBOZ; // User mode may only load/store from user mode pages, and supervisor mode @@ -112,7 +114,6 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) ( assign InvalidWrite = WriteAccess & ~PTE_W; assign InvalidCBOM = (|CMOpM[2:0]) & (~PTE_R & (~STATUS_MXR | ~PTE_X)); assign InvalidCBOZ = CMOpM[3] & ~PTE_W; - assign ReservedEncoding = PTE_W & ~PTE_R; // fault on reserved encoding with R=0, W=1 to match ImperasDV behavior assign InvalidAccess = InvalidRead | InvalidWrite | InvalidCBOM | InvalidCBOZ | ReservedEncoding; assign PreUpdateDA = ~PTE_A | WriteAccess & ~PTE_D; end From 5f68d6d58598c6e91eb15a3bd7e09ab077bea971 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 30 Dec 2024 13:26:46 +0000 Subject: [PATCH 212/212] Bump addins/cvw-arch-verif from `f04bcd7` to `acf99b1` Bumps [addins/cvw-arch-verif](https://github.com/openhwgroup/cvw-arch-verif) from `f04bcd7` to `acf99b1`. - [Commits](https://github.com/openhwgroup/cvw-arch-verif/compare/f04bcd729f46d66ff42c31ee8112cd447a5aa0a3...acf99b1df40b4c90090f17ce1448a7d6a6fde1f5) --- updated-dependencies: - dependency-name: addins/cvw-arch-verif dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- addins/cvw-arch-verif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index f04bcd729..acf99b1df 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit f04bcd729f46d66ff42c31ee8112cd447a5aa0a3 +Subproject commit acf99b1df40b4c90090f17ce1448a7d6a6fde1f5