From eb38d07568ac76d4ee5b8fe57caddb2e86aba7ea Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Wed, 29 Jan 2025 00:11:13 -0800
Subject: [PATCH 1/6] Use macro for CSR connections in wallyTracer

---
 testbench/common/wallyTracer.sv | 565 +++++++-------------------------
 1 file changed, 119 insertions(+), 446 deletions(-)

diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 093b72de2..91367e230 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -29,6 +29,18 @@
 `define PRINT_ALL 0
 `define PRINT_CSRS 0
 
+// Since we are detecting the CSR change by comparing the old value, we need to
+// ensure the CSR is detected when the pipeline's Writeback stage is not
+// stalled.  If it is stalled we want CSRArray to hold the old value.
+`define CONNECT_CSR(addr, val) \
+  always_comb \
+    if (valid) CSRArray[addr] = val; \
+    else CSRArray[addr] = CSRArrayOld[addr]; \
+  always_ff @(posedge clk) \
+    CSRArrayOld[addr] = CSRArray[addr]; \
+  assign CSR_W[addr] = (CSRArrayOld[addr] != CSRArray[addr]) ? 1 : 0; \
+  assign rvvi.csr_wb[0][0][addr] = CSR_W[addr]; \
+  assign rvvi.csr[0][0][addr]    = CSRArray[addr];
 
 module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
 
@@ -65,6 +77,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   logic [11:0]           CSRAdrM, CSRAdrW;
   logic                  wfiM;
   logic                  InterruptM, InterruptW;
+  logic                  valid;
 
   //For VM Verification
   logic [(P.XLEN-1):0]     IVAdrF,IVAdrD,IVAdrE,IVAdrM,IVAdrW,DVAdrM,DVAdrW;
@@ -129,32 +142,97 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   assign IPageTypeF    = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal;
   assign DPageTypeM    = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal;
 
-  logic valid;
-  
+  // CSR connections
   if (P.ZICSR_SUPPORTED) begin
+    // M-mode trap CSRs
+    `CONNECT_CSR(12'h300, testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW);
+    `CONNECT_CSR(12'h302, testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW);
+    `CONNECT_CSR(12'h303, testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW);
+    `CONNECT_CSR(12'h304, testbench.dut.core.priv.priv.csr.csrm.MIE_REGW);
+    `CONNECT_CSR(12'h305, testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW);
+    `CONNECT_CSR(12'h340, testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW);
+    `CONNECT_CSR(12'h341, testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW);
+    `CONNECT_CSR(12'h342, testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW);
+    `CONNECT_CSR(12'h343, testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW);
+    `CONNECT_CSR(12'h344, testbench.dut.core.priv.priv.csr.csrm.MIP_REGW);
+
+    // S-mode trap CSRs
+    `CONNECT_CSR(12'h100, testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW);
+    `CONNECT_CSR(12'h104, testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222);
+    `CONNECT_CSR(12'h105, testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW);
+    `CONNECT_CSR(12'h140, testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW);
+    `CONNECT_CSR(12'h141, testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW);
+    `CONNECT_CSR(12'h142, testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW);
+    `CONNECT_CSR(12'h143, testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW);
+    `CONNECT_CSR(12'h144, testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW);
+
+    // Virtual Memory CSRs
+    `CONNECT_CSR(12'h180, testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW);
+
+    // Floating-Point CSRs
+    `CONNECT_CSR(12'h001, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW);
+    `CONNECT_CSR(12'h002, testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW);
+    `CONNECT_CSR(12'h003, {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW});
+
+    // Counters / Performance Monitoring CSRs
+    `CONNECT_CSR(12'h306, testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW);
+    `CONNECT_CSR(12'h106, testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW);
+    `CONNECT_CSR(12'h320, testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW);
+    // mhpmevent3-31 not connected (232-33F)
+    `CONNECT_CSR(12'hB00, testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]); // MCYCLE
+    `CONNECT_CSR(12'hB02, testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]); // MINSTRET
+    // mhpmcounter3-31 not connected (B03-B1F)
+    // cycle, time, instret not connected (C00-C02)
+    // hpmcounter3-31 not connected (C03-C1F)
+
+    // Machine Information Registers and Configuration CSRs
+    `CONNECT_CSR(12'h301, testbench.dut.core.priv.priv.csr.csrm.MISA_REGW);
+    `CONNECT_CSR(12'h30A, testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW);
+    `CONNECT_CSR(12'h10A, testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW);
+    `CONNECT_CSR(12'h747, 0); // mseccfg
+    `CONNECT_CSR(12'hF11, 0); //mvendorid
+    `CONNECT_CSR(12'hF12, 0); // marchid
+    `CONNECT_CSR(12'hF13, {{P.XLEN-12{1'b0}}, 12'h100}); // mimpid
+    `CONNECT_CSR(12'hF14, testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW);
+    `CONNECT_CSR(12'hF15, 0); //mconfigptr
+
+    // Sstc CSRs
+    `CONNECT_CSR(12'h14D, testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0]);
+    
+    // Zkr CSRs
+    // seed not connected (015)
+
+    // extra CSRs for RV32
+    if (P.XLEN == 32) begin
+      `CONNECT_CSR(12'h310, testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW);
+      `CONNECT_CSR(12'h31A, testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW);
+      `CONNECT_CSR(12'h757, 0); // mseccfgh
+      `CONNECT_CSR(12'h15D, testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32]);
+    end
+  end
+
+
+// PMP CSRs
+  if (P.PMP_ENTRIES > 0) begin
     always_comb begin
-      // Since we are detected the CSR change by comparing the old value we need to
-      // ensure the CSR is detected when the pipeline's Writeback stage is not
-      // stalled.  If it is stalled we want CSRArray to hold the old value.
       if(valid) begin 
         // PMPCFG CSRs (space is 0-15 3a0 - 3af)
         localparam inc = P.XLEN == 32 ? 4 : 8;
-        int i, i4, i8, csrid;
+        int i, i4, csrid;
         logic [P.XLEN-1:0] pmp;
 
         for (i=0; i<P.PMP_ENTRIES; i+=inc) begin
           i4 = i / 4;
-          i8 = (i / inc) * inc;
           csrid = 12'h3A0 + i4;
           pmp = 0;
-          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+0] << 0;
-          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+1] << 8;
-          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+2] << 16;
-          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+3] << 24;
-          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+4] << 32;
-          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+5] << 40;
-          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+6] << 48;
-          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+7] << 56;
+          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+0] << 0;
+          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+1] << 8;
+          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+2] << 16;
+          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+3] << 24;
+          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+4] << 32;
+          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+5] << 40;
+          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+6] << 48;
+          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+7] << 56;
           
           CSRArray[csrid] = pmp;
         end
@@ -166,71 +244,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
           CSRArray[csrid] = pmp;
         end
 
-        // M-mode trap CSRs
-        CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW;
-        CSRArray[12'h302] = testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW;
-        CSRArray[12'h303] = testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
-        CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW;
-        CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW;
-        CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW;
-        CSRArray[12'h341] = testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW;
-        CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW;
-        CSRArray[12'h343] = testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW;
-        CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW;
-        
-        // S-mode trap CSRs
-        CSRArray[12'h100] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW;
-        CSRArray[12'h104] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222;
-        CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW;
-        CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW;
-        CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW;
-        CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW;
-        CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
-        CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
-
-        // Virtual Memory CSRs
-        CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW;
-
-        // Floating-Point CSRs
-        CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;
-        CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW;
-        CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW};
-
-        // Counters / Performance Monitoring CSRs
-        CSRArray[12'h306] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW;
-        CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW;
-        CSRArray[12'h320] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW;
-        // mhpmevent3-31 not connected (232-33F)
-        CSRArray[12'hB00] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]; // MCYCLE
-        CSRArray[12'hB02] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; // MINSTRET
-        // mhpmcounter3-31 not connected (B03-B1F)
-        // cycle, time, instret not connected (C00-C02)
-        // hpmcounter3-31 not connected (C03-C1F)
-
-        // Machine Information Registers and Configuration CSRs
-        CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW;
-        CSRArray[12'h30A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW;
-        CSRArray[12'h10A] = testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW;
-        CSRArray[12'h747] = 0; // mseccfg
-        CSRArray[12'hF11] = 0; //mvendorid
-        CSRArray[12'hF12] = 0; // marchid
-        CSRArray[12'hF13] = {{P.XLEN-12{1'b0}}, 12'h100}; // mimpid
-        CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW;
-        CSRArray[12'hF15] = 0; //mconfigptr
-
-        // Sstc CSRs
-        CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0];
-        
-        // Zkr CSRs
-        // seed not connected (015)
-
-        // extra CSRs for RV32
-        if (P.XLEN == 32) begin
-          CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW;
-          CSRArray[12'h31A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW;
-          CSRArray[12'h757] = 0; // mseccfgh
-          CSRArray[12'h15D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32];
-        end
       end else begin // hold the old value if the pipeline is stalled.
         // PMP CFG 3A0 to 3AF
         int csrid;
@@ -240,79 +253,37 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
         // PMP ADDR 3B0 to 3EF
         for(csrid='h3B0; csrid<='h3EF; csrid++)
           CSRArray[csrid] = CSRArrayOld[csrid];
-
-        // M-mode trap CSRs
-        CSRArray[12'h300] = CSRArrayOld[12'h300];
-        CSRArray[12'h302] = CSRArrayOld[12'h302];
-        CSRArray[12'h303] = CSRArrayOld[12'h303];
-        CSRArray[12'h304] = CSRArrayOld[12'h304];
-        CSRArray[12'h305] = CSRArrayOld[12'h305];
-        CSRArray[12'h340] = CSRArrayOld[12'h340];
-        CSRArray[12'h341] = CSRArrayOld[12'h341];
-        CSRArray[12'h342] = CSRArrayOld[12'h342];
-        CSRArray[12'h343] = CSRArrayOld[12'h343];
-        CSRArray[12'h344] = CSRArrayOld[12'h344];
-
-        // S-mode trap CSRs
-        CSRArray[12'h100] = CSRArrayOld[12'h100];
-        CSRArray[12'h104] = CSRArrayOld[12'h104];
-        CSRArray[12'h105] = CSRArrayOld[12'h105];
-        CSRArray[12'h140] = CSRArrayOld[12'h140];
-        CSRArray[12'h141] = CSRArrayOld[12'h141];
-        CSRArray[12'h142] = CSRArrayOld[12'h142];
-        CSRArray[12'h143] = CSRArrayOld[12'h143];
-        CSRArray[12'h144] = CSRArrayOld[12'h144];
-
-        // Virtual Memory CSRs
-        CSRArray[12'h180] = CSRArrayOld[12'h180] ;
-
-        // Floating-Point CSRs
-        CSRArray[12'h001] = CSRArrayOld[12'h001];
-        CSRArray[12'h002] = CSRArrayOld[12'h002];
-        CSRArray[12'h003] = CSRArrayOld[12'h003];
-
-        // Counters / Performance Monitoring CSRs
-        CSRArray[12'h306] = CSRArrayOld[12'h306];
-        CSRArray[12'h106] = CSRArrayOld[12'h106];
-        CSRArray[12'h320] = CSRArrayOld[12'h320];
-        // mhpmevent3-31 not connected (232-33F)
-        CSRArray[12'hB00] = CSRArrayOld[12'hB00];
-        CSRArray[12'hB02] = CSRArrayOld[12'hB02];
-        // mhpmcounter3-31 not connected (B03-B1F)
-        // cycle, time, instret not connected (C00-C02)
-        // hpmcounter3-31 not connected (C03-C1F)
-
-        // Machine Information Registers and Configuration CSRs
-        CSRArray[12'h301] = CSRArrayOld[12'h301];
-        CSRArray[12'h30A] = CSRArrayOld[12'h30A];
-        CSRArray[12'h10A] = CSRArrayOld[12'h10A];
-        CSRArray[12'h747] = CSRArrayOld[12'h747];
-        CSRArray[12'hF11] = CSRArrayOld[12'hF11];
-        CSRArray[12'hF12] = CSRArrayOld[12'hF12];
-        CSRArray[12'hF13] = CSRArrayOld[12'hF13];
-        CSRArray[12'hF14] = CSRArrayOld[12'hF14];
-        CSRArray[12'hF15] = CSRArrayOld[12'hF15];
-
-        // Sstc CSRs
-        CSRArray[12'h14D] = CSRArrayOld[12'h14D];
-        
-        // Zkr CSRs
-        // seed not connected (015)
-
-        // extra CSRs for RV32
-        if (P.XLEN == 32) begin
-          CSRArray[12'h310] = CSRArrayOld[12'h310];
-          CSRArray[12'h31A] = CSRArrayOld[12'h31A];
-          CSRArray[12'h757] = CSRArrayOld[12'h757];
-          CSRArray[12'h15D] = CSRArrayOld[12'h15D];
-        end
       end    
     end
-  end else begin
-    // no CSRArray
   end
 
+  // record previous csr value.
+  always_ff @(posedge clk) begin
+    int csrid;
+    // PMP CFG 3A0 to 3AF
+    for(csrid='h3A0; csrid<='h3AF; csrid++)
+      CSRArrayOld[csrid] = CSRArray[csrid];
+    
+    // PMP ADDR 3B0 to 3EF
+    for(csrid='h3B0; csrid<='h3EF; csrid++)
+      CSRArrayOld[csrid] = CSRArray[csrid];
+  end
+
+  // PMP CFG 3A0 to 3AF
   genvar index;
+  for(index='h3A0; index<='h3AF; index++) begin
+    assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0;
+    assign rvvi.csr_wb[0][0][index] = CSR_W[index];
+    assign rvvi.csr[0][0][index] = CSRArray[index];  
+  end
+
+  // PMP ADDR 3B0 to 3EF
+  for(index='h3B0; index<='h3EF; index++) begin
+    assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0;
+    assign rvvi.csr_wb[0][0][index] = CSR_W[index];
+    assign rvvi.csr[0][0][index] = CSRArray[index];  
+  end
+
   assign rf[0] = 0;
   for(index = 1; index < NUMREGS; index += 1) 
   assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index];
@@ -427,303 +398,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
     assign rvvi.f_wb[0][0][index]    = frf_wb[index];
   end
 
-  // record previous csr value.
-  integer index4;
-  always_ff @(posedge clk) begin
-    int csrid;
-    // PMP CFG 3A0 to 3AF
-    for(csrid='h3A0; csrid<='h3AF; csrid++)
-      CSRArrayOld[csrid] = CSRArray[csrid];
-    
-    // PMP ADDR 3B0 to 3EF
-    for(csrid='h3B0; csrid<='h3EF; csrid++)
-      CSRArrayOld[csrid] = CSRArray[csrid];
-
-    // M-mode trap CSRs
-    CSRArrayOld[12'h300] = CSRArray[12'h300];
-    CSRArrayOld[12'h302] = CSRArray[12'h302];
-    CSRArrayOld[12'h303] = CSRArray[12'h303];
-    CSRArrayOld[12'h304] = CSRArray[12'h304];
-    CSRArrayOld[12'h305] = CSRArray[12'h305];
-    CSRArrayOld[12'h340] = CSRArray[12'h340];
-    CSRArrayOld[12'h341] = CSRArray[12'h341];
-    CSRArrayOld[12'h342] = CSRArray[12'h342];
-    CSRArrayOld[12'h343] = CSRArray[12'h343];
-    CSRArrayOld[12'h344] = CSRArray[12'h344];
-
-    // S-mode trap CSRs
-    CSRArrayOld[12'h100] = CSRArray[12'h100];
-    CSRArrayOld[12'h104] = CSRArray[12'h104];
-    CSRArrayOld[12'h105] = CSRArray[12'h105];
-    CSRArrayOld[12'h140] = CSRArray[12'h140];
-    CSRArrayOld[12'h141] = CSRArray[12'h141];
-    CSRArrayOld[12'h142] = CSRArray[12'h142];
-    CSRArrayOld[12'h143] = CSRArray[12'h143];
-    CSRArrayOld[12'h144] = CSRArray[12'h144];
-
-    // Virtual Memory CSRs
-    CSRArrayOld[12'h180] = CSRArray[12'h180] ;
-
-    // Floating-Point CSRs
-    CSRArrayOld[12'h001] = CSRArray[12'h001];
-    CSRArrayOld[12'h002] = CSRArray[12'h002];
-    CSRArrayOld[12'h003] = CSRArray[12'h003];
-
-    // Counters / Performance Monitoring CSRs
-    CSRArrayOld[12'h306] = CSRArray[12'h306];
-    CSRArrayOld[12'h106] = CSRArray[12'h106];
-    CSRArrayOld[12'h320] = CSRArray[12'h320];
-    // mhpmevent3-31 not connected (232-33F)
-    CSRArrayOld[12'hB00] = CSRArray[12'hB00];
-    CSRArrayOld[12'hB02] = CSRArray[12'hB02];
-    // mhpmcounter3-31 not connected (B03-B1F)
-    // cycle, time, instret not connected (C00-C02)
-    // hpmcounter3-31 not connected (C03-C1F)
-
-    // Machine Information Registers and Configuration CSRs
-    CSRArrayOld[12'h301] = CSRArray[12'h301];
-    CSRArrayOld[12'h30A] = CSRArray[12'h30A];
-    CSRArrayOld[12'h10A] = CSRArray[12'h10A];
-    CSRArrayOld[12'h747] = CSRArray[12'h747];
-    CSRArrayOld[12'hF11] = CSRArray[12'hF11];
-    CSRArrayOld[12'hF12] = CSRArray[12'hF12];
-    CSRArrayOld[12'hF13] = CSRArray[12'hF13];
-    CSRArrayOld[12'hF14] = CSRArray[12'hF14];
-    CSRArrayOld[12'hF15] = CSRArray[12'hF15];
-
-    // Sstc CSRs
-    CSRArrayOld[12'h14D] = CSRArray[12'h14D];
-    
-    // Zkr CSRs
-    // seed not connected (015)
-
-    // extra CSRs for RV32
-    if (P.XLEN == 32) begin
-      CSRArrayOld[12'h310] = CSRArray[12'h310];
-      CSRArrayOld[12'h31A] = CSRArray[12'h31A];
-      CSRArrayOld[12'h757] = CSRArray[12'h757];
-      CSRArrayOld[12'h15D] = CSRArray[12'h15D];
-    end
-  end
-  
-  // check for csr value change.
-  // M-mode trap CSRs
-  assign CSR_W[12'h300] = (CSRArrayOld[12'h300] != CSRArray[12'h300]) ? 1 : 0;
-  assign CSR_W[12'h302] = (CSRArrayOld[12'h302] != CSRArray[12'h302]) ? 1 : 0;
-  assign CSR_W[12'h303] = (CSRArrayOld[12'h303] != CSRArray[12'h303]) ? 1 : 0;
-  assign CSR_W[12'h304] = (CSRArrayOld[12'h304] != CSRArray[12'h304]) ? 1 : 0;
-  assign CSR_W[12'h305] = (CSRArrayOld[12'h305] != CSRArray[12'h305]) ? 1 : 0;
-  assign CSR_W[12'h340] = (CSRArrayOld[12'h340] != CSRArray[12'h340]) ? 1 : 0;
-  assign CSR_W[12'h341] = (CSRArrayOld[12'h341] != CSRArray[12'h341]) ? 1 : 0;
-  assign CSR_W[12'h342] = (CSRArrayOld[12'h342] != CSRArray[12'h342]) ? 1 : 0;
-  assign CSR_W[12'h343] = (CSRArrayOld[12'h343] != CSRArray[12'h343]) ? 1 : 0;
-  assign CSR_W[12'h344] = (CSRArrayOld[12'h344] != CSRArray[12'h344]) ? 1 : 0;
-
-  // S-mode trap CSRs
-  assign CSR_W[12'h100] = (CSRArrayOld[12'h100] != CSRArray[12'h100]) ? 1 : 0;
-  assign CSR_W[12'h104] = (CSRArrayOld[12'h104] != CSRArray[12'h104]) ? 1 : 0;
-  assign CSR_W[12'h105] = (CSRArrayOld[12'h105] != CSRArray[12'h105]) ? 1 : 0;
-  assign CSR_W[12'h140] = (CSRArrayOld[12'h140] != CSRArray[12'h140]) ? 1 : 0;
-  assign CSR_W[12'h141] = (CSRArrayOld[12'h141] != CSRArray[12'h141]) ? 1 : 0;
-  assign CSR_W[12'h142] = (CSRArrayOld[12'h142] != CSRArray[12'h142]) ? 1 : 0;
-  assign CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0;
-  assign CSR_W[12'h144] = (CSRArrayOld[12'h144] != CSRArray[12'h144]) ? 1 : 0;
-
-  // Virtual Memory CSRs
-  assign CSR_W[12'h180] = (CSRArrayOld[12'h180] != CSRArray[12'h180]) ? 1 : 0;
-
-  // Floating-Point CSRs
-  assign CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0;
-  assign CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0;
-  assign CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0;
-
-  // Counters / Performance Monitoring CSRs
-  assign CSR_W[12'h306] = (CSRArrayOld[12'h306] != CSRArray[12'h306]) ? 1 : 0;
-  assign CSR_W[12'h106] = (CSRArrayOld[12'h106] != CSRArray[12'h106]) ? 1 : 0;
-  assign CSR_W[12'h320] = (CSRArrayOld[12'h320] != CSRArray[12'h320]) ? 1 : 0;
-  // mhpmevent3-31 not connected (232-33F)
-  assign CSR_W[12'hB00] = (CSRArrayOld[12'hB00] != CSRArray[12'hB00]) ? 1 : 0;
-  assign CSR_W[12'hB02] = (CSRArrayOld[12'hB02] != CSRArray[12'hB02]) ? 1 : 0;
-  // mhpmcounter3-31 not connected (B03-B1F)
-  // cycle, time, instret not connected (C00-C02)
-  // hpmcounter3-31 not connected (C03-C1F)
-
-  // Machine Information Registers and Configuration CSRs
-  assign CSR_W[12'h301] = (CSRArrayOld[12'h301] != CSRArray[12'h301]) ? 1 : 0;
-  assign CSR_W[12'h30A] = (CSRArrayOld[12'h30A] != CSRArray[12'h30A]) ? 1 : 0;
-  assign CSR_W[12'h10A] = (CSRArrayOld[12'h10A] != CSRArray[12'h10A]) ? 1 : 0;
-  assign CSR_W[12'h747] = (CSRArrayOld[12'h747] != CSRArray[12'h747]) ? 1 : 0;
-  assign CSR_W[12'hF11] = (CSRArrayOld[12'hF11] != CSRArray[12'hF11]) ? 1 : 0;
-  assign CSR_W[12'hF12] = (CSRArrayOld[12'hF12] != CSRArray[12'hF12]) ? 1 : 0;
-  assign CSR_W[12'hF13] = (CSRArrayOld[12'hF13] != CSRArray[12'hF13]) ? 1 : 0;
-  assign CSR_W[12'hF14] = (CSRArrayOld[12'hF14] != CSRArray[12'hF14]) ? 1 : 0;
-  assign CSR_W[12'hF15] = (CSRArrayOld[12'hF15] != CSRArray[12'hF15]) ? 1 : 0;
-
-  // Sstc CSRs
-  assign CSR_W[12'h14D] = (CSRArrayOld[12'h14D] != CSRArray[12'h14D]) ? 1 : 0;
-  
-  // Zkr CSRs
-  // seed not connected (015)
-
-  // extra CSRs for RV32
-  if (P.XLEN == 32) begin
-    assign CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0;
-    assign CSR_W[12'h31A] = (CSRArrayOld[12'h31A] != CSRArray[12'h31A]) ? 1 : 0;
-    assign CSR_W[12'h757] = (CSRArrayOld[12'h757] != CSRArray[12'h757]) ? 1 : 0;
-    assign CSR_W[12'h15D] = (CSRArrayOld[12'h15D] != CSRArray[12'h15D]) ? 1 : 0;
-  end
-
-
-
-  // M-mode trap CSRs
-  assign rvvi.csr_wb[0][0][12'h300] = CSR_W[12'h300];
-  assign rvvi.csr_wb[0][0][12'h302] = CSR_W[12'h302];
-  assign rvvi.csr_wb[0][0][12'h303] = CSR_W[12'h303];
-  assign rvvi.csr_wb[0][0][12'h304] = CSR_W[12'h304];
-  assign rvvi.csr_wb[0][0][12'h305] = CSR_W[12'h305];
-  assign rvvi.csr_wb[0][0][12'h340] = CSR_W[12'h340];
-  assign rvvi.csr_wb[0][0][12'h341] = CSR_W[12'h341];
-  assign rvvi.csr_wb[0][0][12'h342] = CSR_W[12'h342];
-  assign rvvi.csr_wb[0][0][12'h343] = CSR_W[12'h343];
-  assign rvvi.csr_wb[0][0][12'h344] = CSR_W[12'h344];
-
-  // S-mode trap CSRs
-  assign rvvi.csr_wb[0][0][12'h100] = CSR_W[12'h100];
-  assign rvvi.csr_wb[0][0][12'h104] = CSR_W[12'h104];
-  assign rvvi.csr_wb[0][0][12'h105] = CSR_W[12'h105];
-  assign rvvi.csr_wb[0][0][12'h140] = CSR_W[12'h140];
-  assign rvvi.csr_wb[0][0][12'h141] = CSR_W[12'h141];
-  assign rvvi.csr_wb[0][0][12'h142] = CSR_W[12'h142];
-  assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143];
-  assign rvvi.csr_wb[0][0][12'h144] = CSR_W[12'h144];
-
-  // Virtual Memory CSRs
-  assign rvvi.csr_wb[0][0][12'h180] = CSR_W[12'h180];
-
-  // Floating-Point CSRs
-  assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001];
-  assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002];
-  assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003];
-
-  // Counters / Performance Monitoring CSRs
-  assign rvvi.csr_wb[0][0][12'h306] = CSR_W[12'h306];
-  assign rvvi.csr_wb[0][0][12'h106] = CSR_W[12'h106];
-  assign rvvi.csr_wb[0][0][12'h320] = CSR_W[12'h320];
-  // mhpmevent3-31 not connected (232-33F)
-  assign rvvi.csr_wb[0][0][12'hB00] = CSR_W[12'hB00];
-  assign rvvi.csr_wb[0][0][12'hB02] = CSR_W[12'hB02];
-  // mhpmcounter3-31 not connected (B03-B1F)
-  // cycle, time, instret not connected (C00-C02)
-  // hpmcounter3-31 not connected (C03-C1F)
-
-  // Machine Information Registers and Configuration CSRs
-  assign rvvi.csr_wb[0][0][12'h301] = CSR_W[12'h301];
-  assign rvvi.csr_wb[0][0][12'h30A] = CSR_W[12'h30A];
-  assign rvvi.csr_wb[0][0][12'h10A] = CSR_W[12'h10A];
-  assign rvvi.csr_wb[0][0][12'h747] = CSR_W[12'h747];
-  assign rvvi.csr_wb[0][0][12'hF11] = CSR_W[12'hF11];
-  assign rvvi.csr_wb[0][0][12'hF12] = CSR_W[12'hF12];
-  assign rvvi.csr_wb[0][0][12'hF13] = CSR_W[12'hF13];
-  assign rvvi.csr_wb[0][0][12'hF14] = CSR_W[12'hF14];
-  assign rvvi.csr_wb[0][0][12'hF15] = CSR_W[12'hF15];
-
-  // Sstc CSRs
-  assign rvvi.csr_wb[0][0][12'h14D] = CSR_W[12'h14D];
-  
-  // Zkr CSRs
-  // seed not connected (015)
-
-  // extra CSRs for RV32
-  if (P.XLEN == 32) begin
-    assign rvvi.csr_wb[0][0][12'h310] = CSR_W[12'h310];
-    assign rvvi.csr_wb[0][0][12'h31A] = CSR_W[12'h31A];
-    assign rvvi.csr_wb[0][0][12'h757] = CSR_W[12'h757];
-    assign rvvi.csr_wb[0][0][12'h15D] = CSR_W[12'h15D];
-  end
-
-
-
-// M-mode trap CSRs
-  assign rvvi.csr[0][0][12'h300] = CSRArray[12'h300];
-  assign rvvi.csr[0][0][12'h302] = CSRArray[12'h302];
-  assign rvvi.csr[0][0][12'h303] = CSRArray[12'h303];
-  assign rvvi.csr[0][0][12'h304] = CSRArray[12'h304];
-  assign rvvi.csr[0][0][12'h305] = CSRArray[12'h305];
-  assign rvvi.csr[0][0][12'h340] = CSRArray[12'h340];
-  assign rvvi.csr[0][0][12'h341] = CSRArray[12'h341];
-  assign rvvi.csr[0][0][12'h342] = CSRArray[12'h342];
-  assign rvvi.csr[0][0][12'h343] = CSRArray[12'h343];
-  assign rvvi.csr[0][0][12'h344] = CSRArray[12'h344];
-
-  // S-mode trap CSRs
-  assign rvvi.csr[0][0][12'h100] = CSRArray[12'h100];
-  assign rvvi.csr[0][0][12'h104] = CSRArray[12'h104];
-  assign rvvi.csr[0][0][12'h105] = CSRArray[12'h105];
-  assign rvvi.csr[0][0][12'h140] = CSRArray[12'h140];
-  assign rvvi.csr[0][0][12'h141] = CSRArray[12'h141];
-  assign rvvi.csr[0][0][12'h142] = CSRArray[12'h142];
-  assign rvvi.csr[0][0][12'h143] = CSRArray[12'h143];
-  assign rvvi.csr[0][0][12'h144] = CSRArray[12'h144];
-
-  // Virtual Memory CSRs
-  assign rvvi.csr[0][0][12'h180] = CSRArray[12'h180];
-
-  // Floating-Point CSRs
-  assign rvvi.csr[0][0][12'h001] = CSRArray[12'h001];
-  assign rvvi.csr[0][0][12'h002] = CSRArray[12'h002];
-  assign rvvi.csr[0][0][12'h003] = CSRArray[12'h003];
-
-  // Counters / Performance Monitoring CSRs
-  assign rvvi.csr[0][0][12'h306] = CSRArray[12'h306];
-  assign rvvi.csr[0][0][12'h106] = CSRArray[12'h106];
-  assign rvvi.csr[0][0][12'h320] = CSRArray[12'h320];
-  // mhpmevent3-31 not connected (232-33F)
-  assign rvvi.csr[0][0][12'hB00] = CSRArray[12'hB00];
-  assign rvvi.csr[0][0][12'hB02] = CSRArray[12'hB02];
-  // mhpmcounter3-31 not connected (B03-B1F)
-  // cycle, time, instret not connected (C00-C02)
-  // hpmcounter3-31 not connected (C03-C1F)
-
-  // Machine Information Registers and Configuration CSRs
-  assign rvvi.csr[0][0][12'h301] = CSRArray[12'h301];
-  assign rvvi.csr[0][0][12'h30A] = CSRArray[12'h30A];
-  assign rvvi.csr[0][0][12'h10A] = CSRArray[12'h10A];
-  assign rvvi.csr[0][0][12'h747] = CSRArray[12'h747];
-  assign rvvi.csr[0][0][12'hF11] = CSRArray[12'hF11];
-  assign rvvi.csr[0][0][12'hF12] = CSRArray[12'hF12];
-  assign rvvi.csr[0][0][12'hF13] = CSRArray[12'hF13];
-  assign rvvi.csr[0][0][12'hF14] = CSRArray[12'hF14];
-  assign rvvi.csr[0][0][12'hF15] = CSRArray[12'hF15];
-
-  // Sstc CSRs
-  assign rvvi.csr[0][0][12'h14D] = CSRArray[12'h14D];
-  
-  // Zkr CSRs
-  // seed not connected (015)
-
-  // extra CSRs for RV32
-  if (P.XLEN == 32) begin
-    assign rvvi.csr[0][0][12'h310] = CSRArray[12'h310];
-    assign rvvi.csr[0][0][12'h31A] = CSRArray[12'h31A];
-    assign rvvi.csr[0][0][12'h757] = CSRArray[12'h757];
-    assign rvvi.csr[0][0][12'h15D] = CSRArray[12'h15D];
-  end
-
-
-  // PMP CFG 3A0 to 3AF
-  for(index='h3A0; index<='h3AF; index++) begin
-    assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0;
-    assign rvvi.csr_wb[0][0][index] = CSR_W[index];
-    assign rvvi.csr[0][0][index] = CSRArray[index];  
-  end
-
-  // PMP ADDR 3B0 to 3EF
-  for(index='h3B0; index<='h3EF; index++) begin
-    assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0;
-    assign rvvi.csr_wb[0][0][index] = CSR_W[index];
-    assign rvvi.csr[0][0][index] = CSRArray[index];  
-  end
-
   // *** implementation only cancel? so sc does not clear?
   assign rvvi.lrsc_cancel[0][0] = 0;
 
@@ -787,4 +461,3 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
     if(HaltW) $finish;
   end
 endmodule
-

From fdfef5a490a176f9f1cb11594b366b2ff1142a08 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Wed, 29 Jan 2025 18:53:11 -0800
Subject: [PATCH 2/6] Simplify macro

---
 testbench/common/wallyTracer.sv | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 2de52af3c..d2d192bfe 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -21,7 +21,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-
 `define STD_LOG 0
 `define PRINT_PC_INSTR 0
 `define PRINT_MOST 0
@@ -30,16 +29,12 @@
 
 // Since we are detecting the CSR change by comparing the old value, we need to
 // ensure the CSR is detected when the pipeline's Writeback stage is not
-// stalled.  If it is stalled we want CSRArray to hold the old value.
+// stalled.  If it is stalled we want to hold the old value.
 `define CONNECT_CSR(addr, val) \
-  always_comb \
-    if (valid) CSRArray[addr] = val; \
-    else CSRArray[addr] = CSRArrayOld[addr]; \
   always_ff @(posedge clk) \
-    CSRArrayOld[addr] = CSRArray[addr]; \
-  assign CSR_W[addr] = (CSRArrayOld[addr] != CSRArray[addr]) ? 1 : 0; \
-  assign rvvi.csr_wb[0][0][addr] = CSR_W[addr]; \
-  assign rvvi.csr[0][0][addr]    = CSRArray[addr];
+    CSRArrayOld[addr] = rvvi.csr[0][0][addr]; \
+  assign rvvi.csr_wb[0][0][addr] = (rvvi.csr[0][0][addr] != CSRArrayOld[addr]); \
+  assign rvvi.csr[0][0][addr] = valid ? val : CSRArrayOld[addr];
 
 module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
 

From 0b7b1f3c9aa1d9fd6b77e0375a7ff764a190691f Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Wed, 29 Jan 2025 19:15:52 -0800
Subject: [PATCH 3/6] Use macro concatenation instead of CSRArrayOld

---
 testbench/common/wallyTracer.sv | 99 +++++++++++++++++----------------
 1 file changed, 50 insertions(+), 49 deletions(-)

diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index d2d192bfe..8080101dc 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -30,11 +30,12 @@
 // Since we are detecting the CSR change by comparing the old value, we need to
 // ensure the CSR is detected when the pipeline's Writeback stage is not
 // stalled.  If it is stalled we want to hold the old value.
-`define CONNECT_CSR(addr, val) \
+`define CONNECT_CSR(name, addr, val) \
+  logic [P.XLEN-1:0] prev_csr_``name; \
   always_ff @(posedge clk) \
-    CSRArrayOld[addr] = rvvi.csr[0][0][addr]; \
-  assign rvvi.csr_wb[0][0][addr] = (rvvi.csr[0][0][addr] != CSRArrayOld[addr]); \
-  assign rvvi.csr[0][0][addr] = valid ? val : CSRArrayOld[addr];
+    prev_csr_``name <= rvvi.csr[0][0][addr]; \
+  assign rvvi.csr_wb[0][0][addr] = (rvvi.csr[0][0][addr] != prev_csr_``name); \
+  assign rvvi.csr[0][0][addr] = valid ? val : prev_csr_``name;
 
 module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
 
@@ -140,69 +141,69 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   // CSR connections
   if (P.ZICSR_SUPPORTED) begin
     // M-mode trap CSRs
-    `CONNECT_CSR(12'h300, testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW);
-    `CONNECT_CSR(12'h302, testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW);
-    `CONNECT_CSR(12'h303, testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW);
-    `CONNECT_CSR(12'h304, testbench.dut.core.priv.priv.csr.csrm.MIE_REGW);
-    `CONNECT_CSR(12'h305, testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW);
-    `CONNECT_CSR(12'h340, testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW);
-    `CONNECT_CSR(12'h341, testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW);
-    `CONNECT_CSR(12'h342, testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW);
-    `CONNECT_CSR(12'h343, testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW);
-    `CONNECT_CSR(12'h344, testbench.dut.core.priv.priv.csr.csrm.MIP_REGW);
+    `CONNECT_CSR(MSTATUS, 12'h300, testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW);
+    `CONNECT_CSR(MEDELEG, 12'h302, testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW);
+    `CONNECT_CSR(MIDELEG, 12'h303, testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW);
+    `CONNECT_CSR(MIE, 12'h304, testbench.dut.core.priv.priv.csr.csrm.MIE_REGW);
+    `CONNECT_CSR(MTVEC, 12'h305, testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW);
+    `CONNECT_CSR(MSCRATCH, 12'h340, testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW);
+    `CONNECT_CSR(MEPC, 12'h341, testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW);
+    `CONNECT_CSR(MCAUSE, 12'h342, testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW);
+    `CONNECT_CSR(MTVAL, 12'h343, testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW);
+    `CONNECT_CSR(MIP, 12'h344, testbench.dut.core.priv.priv.csr.csrm.MIP_REGW);
 
     // S-mode trap CSRs
-    `CONNECT_CSR(12'h100, testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW);
-    `CONNECT_CSR(12'h104, testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222);
-    `CONNECT_CSR(12'h105, testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW);
-    `CONNECT_CSR(12'h140, testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW);
-    `CONNECT_CSR(12'h141, testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW);
-    `CONNECT_CSR(12'h142, testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW);
-    `CONNECT_CSR(12'h143, testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW);
-    `CONNECT_CSR(12'h144, testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW);
+    `CONNECT_CSR(SSTATUS, 12'h100, testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW);
+    `CONNECT_CSR(SIE, 12'h104, testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222);
+    `CONNECT_CSR(STVEC, 12'h105, testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW);
+    `CONNECT_CSR(SSCRATCH, 12'h140, testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW);
+    `CONNECT_CSR(SEPC, 12'h141, testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW);
+    `CONNECT_CSR(SCAUSE, 12'h142, testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW);
+    `CONNECT_CSR(STVAL, 12'h143, testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW);
+    `CONNECT_CSR(SIP, 12'h144, testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW);
 
     // Virtual Memory CSRs
-    `CONNECT_CSR(12'h180, testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW);
+    `CONNECT_CSR(SATP, 12'h180, testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW);
 
     // Floating-Point CSRs
-    `CONNECT_CSR(12'h001, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW);
-    `CONNECT_CSR(12'h002, testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW);
-    `CONNECT_CSR(12'h003, {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW});
+    `CONNECT_CSR(FFLAGS, 12'h001, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW);
+    `CONNECT_CSR(FRM, 12'h002, testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW);
+    `CONNECT_CSR(FCSR, 12'h003, {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW});
 
     // Counters / Performance Monitoring CSRs
-    `CONNECT_CSR(12'h306, testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW);
-    `CONNECT_CSR(12'h106, testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW);
-    `CONNECT_CSR(12'h320, testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW);
+    `CONNECT_CSR(MCOUNTEREN, 12'h306, testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW);
+    `CONNECT_CSR(SCOUNTEREN, 12'h106, testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW);
+    `CONNECT_CSR(MCOUNTINHIBIT, 12'h320, testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW);
     // mhpmevent3-31 not connected (232-33F)
-    `CONNECT_CSR(12'hB00, testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]); // MCYCLE
-    `CONNECT_CSR(12'hB02, testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]); // MINSTRET
+    `CONNECT_CSR(MCYCLE, 12'hB00, testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]); // MCYCLE
+    `CONNECT_CSR(MINSTRET, 12'hB02, testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]); // MINSTRET
     // mhpmcounter3-31 not connected (B03-B1F)
     // cycle, time, instret not connected (C00-C02)
     // hpmcounter3-31 not connected (C03-C1F)
 
     // Machine Information Registers and Configuration CSRs
-    `CONNECT_CSR(12'h301, testbench.dut.core.priv.priv.csr.csrm.MISA_REGW);
-    `CONNECT_CSR(12'h30A, testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW);
-    `CONNECT_CSR(12'h10A, testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW);
-    `CONNECT_CSR(12'h747, 0); // mseccfg
-    `CONNECT_CSR(12'hF11, 0); //mvendorid
-    `CONNECT_CSR(12'hF12, 0); // marchid
-    `CONNECT_CSR(12'hF13, {{P.XLEN-12{1'b0}}, 12'h100}); // mimpid
-    `CONNECT_CSR(12'hF14, testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW);
-    `CONNECT_CSR(12'hF15, 0); //mconfigptr
+    `CONNECT_CSR(MISA, 12'h301, testbench.dut.core.priv.priv.csr.csrm.MISA_REGW);
+    `CONNECT_CSR(MENVCFG, 12'h30A, testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW);
+    `CONNECT_CSR(SENVCFG, 12'h10A, testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW);
+    `CONNECT_CSR(MSECCFG, 12'h747, 0); // mseccfg
+    `CONNECT_CSR(MVENDORID, 12'hF11, 0); //mvendorid
+    `CONNECT_CSR(MARCHID, 12'hF12, 0); // marchid
+    `CONNECT_CSR(MIMPID, 12'hF13, {{P.XLEN-12{1'b0}}, 12'h100}); // mimpid
+    `CONNECT_CSR(MHARTID, 12'hF14, testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW);
+    `CONNECT_CSR(MCONFIGPTR, 12'hF15, 0); //mconfigptr
 
     // Sstc CSRs
-    `CONNECT_CSR(12'h14D, testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0]);
+    `CONNECT_CSR(STIMECMP, 12'h14D, testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0]);
     
     // Zkr CSRs
     // seed not connected (015)
 
     // extra CSRs for RV32
     if (P.XLEN == 32) begin
-      `CONNECT_CSR(12'h310, testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW);
-      `CONNECT_CSR(12'h31A, testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW);
-      `CONNECT_CSR(12'h757, 0); // mseccfgh
-      `CONNECT_CSR(12'h15D, testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32]);
+      `CONNECT_CSR(MSTATUSH, 12'h310, testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW);
+      `CONNECT_CSR(MENVCFGH, 12'h31A, testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW);
+      `CONNECT_CSR(MSECCFGH, 12'h757, 0); // mseccfgh
+      `CONNECT_CSR(STIMECMPH, 12'h15D, testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32]);
     end
   end
 
@@ -374,7 +375,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   assign valid  = ((InstrValidW | TrapW) & ~StallW) & ~reset;
   assign rvvi.clk = clk;
   assign rvvi.valid[0][0]    = valid;
-  assign rvvi.order[0][0]    = CSRArray[12'hB02];  // TODO: IMPERAS Should be event order
+  assign rvvi.order[0][0]    = rvvi.csr[0][0][12'hB02];  // TODO: IMPERAS Should be event order
   assign rvvi.insn[0][0]     = InstrRawW;
   assign rvvi.pc_rdata[0][0] = PCW;
   assign rvvi.trap[0][0]     = TrapW;
@@ -414,7 +415,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   end
   
   always_ff @(posedge clk) begin
-	if(valid) begin
+  if(valid) begin
       if(`STD_LOG) begin
         $fwrite(file, "%016x, %08x, %s\t\t", rvvi.pc_rdata[0][0], rvvi.insn[0][0], instrWName);
         for(index2 = 0; index2 < NUM_REGS; index2 += 1) begin
@@ -451,8 +452,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
       end
       if (`PRINT_CSRS) begin
         for(index2 = 0; index2 < NUM_CSRS; index2 += 1) begin
-          if(CSR_W[index2]) begin
-            $display("%t: CSR %03x = %x", $time(), index2, CSRArray[index2]);
+          if((rvvi.csr[0][0][index2] != CSRArrayOld[index2])) begin
+            $display("%t: CSR %03x = %x", $time(), index2, rvvi.csr[0][0][index2]);
           end
         end
       end

From 6d3223fafe4cfe1aea79cc2748c1b4175fe29398 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Wed, 29 Jan 2025 19:58:06 -0800
Subject: [PATCH 4/6] Use macro for pmpcfg csrs

---
 testbench/common/wallyTracer.sv | 96 ++++++++-------------------------
 1 file changed, 23 insertions(+), 73 deletions(-)

diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 8080101dc..d5f0fcc41 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -207,82 +207,32 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
     end
   end
 
-
-// PMP CSRs
   if (P.PMP_ENTRIES > 0) begin
-    always_comb begin
-      if(valid) begin 
-        // PMPCFG CSRs (space is 0-15 3a0 - 3af)
-        localparam inc = P.XLEN == 32 ? 4 : 8;
-        int i, i4, csrid;
-        logic [P.XLEN-1:0] pmp;
-
-        for (i=0; i<P.PMP_ENTRIES; i+=inc) begin
-          i4 = i / 4;
-          csrid = 12'h3A0 + i4;
-          pmp = 0;
-          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+0] << 0;
-          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+1] << 8;
-          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+2] << 16;
-          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+3] << 24;
-          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+4] << 32;
-          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+5] << 40;
-          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+6] << 48;
-          pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+7] << 56;
-          
-          CSRArray[csrid] = pmp;
-        end
-
-        // PMPADDR CSRs (space is 0-63 3b0 - 3ef)
-        for (i=0; i<P.PMP_ENTRIES; i++) begin
-          csrid = 12'h3B0 + i;;
-          pmp = testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[i];
-          CSRArray[csrid] = pmp;
-        end
-
-      end else begin // hold the old value if the pipeline is stalled.
-        // PMP CFG 3A0 to 3AF
-        int csrid;
-        for(csrid='h3A0; csrid<='h3AF; csrid++)
-          CSRArray[csrid] = CSRArrayOld[csrid];
-        
-        // PMP ADDR 3B0 to 3EF
-        for(csrid='h3B0; csrid<='h3EF; csrid++)
-          CSRArray[csrid] = CSRArrayOld[csrid];
-      end    
+    localparam inc = P.XLEN == 32 ? 4 : 8;
+    // PMPCFG CSRs (space is 0-15 3a0 - 3af)
+    for (genvar pmpCfgID = 0; pmpCfgID < P.PMP_ENTRIES; pmpCfgID += inc) begin
+      logic [P.XLEN-1:0] pmp;
+      localparam int i4 = pmpCfgID / 4;
+      assign pmp = {testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+7],
+                    testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+6],
+                    testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+5],
+                    testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+4],
+                    testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+3],
+                    testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+2],
+                    testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+1],
+                    testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+0]};
+      `CONNECT_CSR(PMPCFG``i4, 12'h3A0 + i4, pmp);
     end
-  end
 
-  // record previous csr value.
-  always_ff @(posedge clk) begin
-    int csrid;
-    // PMP CFG 3A0 to 3AF
-    for(csrid='h3A0; csrid<='h3AF; csrid++)
-      CSRArrayOld[csrid] = CSRArray[csrid];
-    
-    // PMP ADDR 3B0 to 3EF
-    for(csrid='h3B0; csrid<='h3EF; csrid++)
-      CSRArrayOld[csrid] = CSRArray[csrid];
-  end
-
-  // PMP CFG 3A0 to 3AF
-  genvar index;
-  for(index='h3A0; index<='h3AF; index++) begin
-    assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0;
-    assign rvvi.csr_wb[0][0][index] = CSR_W[index];
-    assign rvvi.csr[0][0][index] = CSRArray[index];  
-  end
-
-  // PMP ADDR 3B0 to 3EF
-  for(index='h3B0; index<='h3EF; index++) begin
-    assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0;
-    assign rvvi.csr_wb[0][0][index] = CSR_W[index];
-    assign rvvi.csr[0][0][index] = CSRArray[index];  
+  // PMPADDR CSRs 3B0 to 3EF
+    for(genvar pmpAddrID = 0; pmpAddrID < P.PMP_ENTRIES; pmpAddrID++) begin
+      `CONNECT_CSR(PMPADDR``pmpAddrID, 12'h3B0 + pmpAddrID, testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[pmpAddrID]);
+    end
   end
 
   // Integer register file
   assign rf[0] = 0;
-  for(index = 1; index < NUM_REGS; index += 1) 
+  for(genvar index = 1; index < NUM_REGS; index += 1) 
     assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index];
 
   assign rf_a3  = testbench.dut.core.ieu.dp.regf.a3;
@@ -298,12 +248,12 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   if (P.F_SUPPORTED) begin
     assign frf_a4  = testbench.dut.core.fpu.fpu.fregfile.a4;
     assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4;
-    for(index = 0; index < 32; index += 1) 
+    for(genvar index = 0; index < 32; index += 1) 
       assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index];
   end else begin
     assign frf_a4  = '0;
     assign frf_we4 = 0;
-    for(index = 0; index < 32; index += 1) 
+    for(genvar index = 0; index < 32; index += 1) 
       assign frf[index] = '0;
   end
 
@@ -389,11 +339,11 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
                                ~FlushE ? PCD :
                                ~FlushD ? PCF : PCNextF;
 
-  for(index = 0; index < NUM_REGS; index += 1) begin
+  for(genvar index = 0; index < NUM_REGS; index += 1) begin
     assign rvvi.x_wdata[0][0][index] = rf[index];
     assign rvvi.x_wb[0][0][index]    = rf_wb[index];
   end
-  for(index = 0; index < 32; index += 1) begin
+  for(genvar index = 0; index < 32; index += 1) begin
     assign rvvi.f_wdata[0][0][index] = frf[index];
     assign rvvi.f_wb[0][0][index]    = frf_wb[index];
   end

From 587f7dcea759f954156309f5fdfbe1ff682e3cab Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Wed, 29 Jan 2025 21:32:24 -0800
Subject: [PATCH 5/6] Remove unused signals from wallyTracer

---
 testbench/common/wallyTracer.sv | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index d5f0fcc41..e3239772d 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -66,9 +66,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   logic [31:0]           frf_wb;
   logic [4:0]            frf_a4;
   logic                  frf_we4;
-  logic [P.XLEN-1:0]     CSRArray [4095:0];
-  logic [P.XLEN-1:0]     CSRArrayOld [4095:0];
-  logic [NUM_CSRS-1:0]  CSR_W;
   logic                  CSRWriteM, CSRWriteW;
   logic [11:0]           CSRAdrM, CSRAdrW;
   logic                  wfiM;
@@ -400,13 +397,14 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
           $display("f%02d = %08x", index2, rvvi.f_wdata[0][0][index2]);
         end
       end
-      if (`PRINT_CSRS) begin
-        for(index2 = 0; index2 < NUM_CSRS; index2 += 1) begin
-          if((rvvi.csr[0][0][index2] != CSRArrayOld[index2])) begin
-            $display("%t: CSR %03x = %x", $time(), index2, rvvi.csr[0][0][index2]);
-          end
-        end
-      end
+      // Need to figure out how to print values on change if they are not in a large array
+      // if (`PRINT_CSRS) begin
+      //   for(index2 = 0; index2 < NUM_CSRS; index2 += 1) begin
+      //     if((rvvi.csr[0][0][index2] != CSRArrayOld[index2])) begin
+      //       $display("%t: CSR %03x = %x", $time(), index2, rvvi.csr[0][0][index2]);
+      //     end
+      //   end
+      // end
     end
     if(HaltW) $finish;
   end

From 373855af0b8bef77c2dda9f569cf4b5c46617804 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Wed, 29 Jan 2025 21:32:42 -0800
Subject: [PATCH 6/6] Gate more CSRs in wallyTracer on supported extensions

---
 testbench/common/wallyTracer.sv | 54 +++++++++++++++++++++------------
 1 file changed, 34 insertions(+), 20 deletions(-)

diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index e3239772d..1f6af7b7a 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -150,33 +150,45 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
     `CONNECT_CSR(MIP, 12'h344, testbench.dut.core.priv.priv.csr.csrm.MIP_REGW);
 
     // S-mode trap CSRs
-    `CONNECT_CSR(SSTATUS, 12'h100, testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW);
-    `CONNECT_CSR(SIE, 12'h104, testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222);
-    `CONNECT_CSR(STVEC, 12'h105, testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW);
-    `CONNECT_CSR(SSCRATCH, 12'h140, testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW);
-    `CONNECT_CSR(SEPC, 12'h141, testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW);
-    `CONNECT_CSR(SCAUSE, 12'h142, testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW);
-    `CONNECT_CSR(STVAL, 12'h143, testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW);
-    `CONNECT_CSR(SIP, 12'h144, testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW);
+    if (P.S_SUPPORTED) begin
+      `CONNECT_CSR(SSTATUS, 12'h100, testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW);
+      `CONNECT_CSR(SIE, 12'h104, testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222);
+      `CONNECT_CSR(STVEC, 12'h105, testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW);
+      `CONNECT_CSR(SSCRATCH, 12'h140, testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW);
+      `CONNECT_CSR(SEPC, 12'h141, testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW);
+      `CONNECT_CSR(SCAUSE, 12'h142, testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW);
+      `CONNECT_CSR(STVAL, 12'h143, testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW);
+      `CONNECT_CSR(SIP, 12'h144, testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW);
+    end
 
     // Virtual Memory CSRs
-    `CONNECT_CSR(SATP, 12'h180, testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW);
+    if (P.VIRTMEM_SUPPORTED) begin
+      `CONNECT_CSR(SATP, 12'h180, testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW);
+    end
 
     // Floating-Point CSRs
-    `CONNECT_CSR(FFLAGS, 12'h001, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW);
-    `CONNECT_CSR(FRM, 12'h002, testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW);
-    `CONNECT_CSR(FCSR, 12'h003, {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW});
+    if (P.F_SUPPORTED) begin
+      `CONNECT_CSR(FFLAGS, 12'h001, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW);
+      `CONNECT_CSR(FRM, 12'h002, testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW);
+      `CONNECT_CSR(FCSR, 12'h003, {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW});
+    end
 
     // Counters / Performance Monitoring CSRs
-    `CONNECT_CSR(MCOUNTEREN, 12'h306, testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW);
-    `CONNECT_CSR(SCOUNTEREN, 12'h106, testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW);
+    if (P.U_SUPPORTED) begin
+      `CONNECT_CSR(MCOUNTEREN, 12'h306, testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW);
+    end
+    if (P.S_SUPPORTED) begin
+      `CONNECT_CSR(SCOUNTEREN, 12'h106, testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW);
+    end
     `CONNECT_CSR(MCOUNTINHIBIT, 12'h320, testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW);
     // mhpmevent3-31 not connected (232-33F)
-    `CONNECT_CSR(MCYCLE, 12'hB00, testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]); // MCYCLE
-    `CONNECT_CSR(MINSTRET, 12'hB02, testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]); // MINSTRET
-    // mhpmcounter3-31 not connected (B03-B1F)
-    // cycle, time, instret not connected (C00-C02)
-    // hpmcounter3-31 not connected (C03-C1F)
+    if (P.ZICNTR_SUPPORTED) begin
+      `CONNECT_CSR(MCYCLE, 12'hB00, testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]); // MCYCLE
+      `CONNECT_CSR(MINSTRET, 12'hB02, testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]); // MINSTRET
+      // mhpmcounter3-31 not connected (B03-B1F)
+      // cycle, time, instret not connected (C00-C02)
+      // hpmcounter3-31 not connected (C03-C1F)
+    end
 
     // Machine Information Registers and Configuration CSRs
     `CONNECT_CSR(MISA, 12'h301, testbench.dut.core.priv.priv.csr.csrm.MISA_REGW);
@@ -190,7 +202,9 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
     `CONNECT_CSR(MCONFIGPTR, 12'hF15, 0); //mconfigptr
 
     // Sstc CSRs
-    `CONNECT_CSR(STIMECMP, 12'h14D, testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0]);
+    if (P.SSTC_SUPPORTED) begin
+      `CONNECT_CSR(STIMECMP, 12'h14D, testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0]);
+    end
     
     // Zkr CSRs
     // seed not connected (015)