diff --git a/fpga/constraints/constraints-vcu118.xdc b/fpga/constraints/constraints-vcu118.xdc index 4d185f994..5de479951 100644 --- a/fpga/constraints/constraints-vcu118.xdc +++ b/fpga/constraints/constraints-vcu118.xdc @@ -117,10 +117,10 @@ set_property PULLUP true [get_ports {SDCCmd}] set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.500 [get_ports {SDCDat[*]}] -set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 21.000 [get_ports {SDCDat[*]}] +set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 10.000 [get_ports {SDCDat[*]}] set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.500 [get_ports {SDCCmd}] -set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 14.000 [get_ports {SDCCmd}] +set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 10.000 [get_ports {SDCCmd}] set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {SDCCmd}] diff --git a/fpga/generator/xlnx_ddr4-vcu118.tcl b/fpga/generator/xlnx_ddr4-vcu118.tcl index 510c68678..8041726ff 100644 --- a/fpga/generator/xlnx_ddr4-vcu118.tcl +++ b/fpga/generator/xlnx_ddr4-vcu118.tcl @@ -38,7 +38,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \ CONFIG.C0.DDR4_AxiNarrowBurst {false} \ CONFIG.Reference_Clock {Differential} \ CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \ - CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {71} \ CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \ CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \ diff --git a/linux/buildroot-packages/package-source/fpga-axi-sdc.c b/linux/buildroot-packages/package-source/fpga-axi-sdc.c index 15bd95a90..8bac2c9e5 100644 --- a/linux/buildroot-packages/package-source/fpga-axi-sdc.c +++ b/linux/buildroot-packages/package-source/fpga-axi-sdc.c @@ -272,6 +272,8 @@ static void sdc_reset(struct mmc_host * mmc) { struct sdc_host * host = mmc_priv(mmc); uint32_t card_detect = 0; + spin_lock_init(&host->lock); + spin_lock_irq(&host->lock); sdc_set_clock(host, 400000); @@ -462,7 +464,7 @@ static int axi_sdc_probe(struct platform_device * pdev) { return ret; } - spin_lock_init(&host->lock); + //spin_lock_init(&host->lock); platform_set_drvdata(pdev, host); return 0; diff --git a/linux/devicetree/wally-vcu118.dts b/linux/devicetree/wally-vcu118.dts index a4794f0d0..e0257c9a6 100644 --- a/linux/devicetree/wally-vcu118.dts +++ b/linux/devicetree/wally-vcu118.dts @@ -9,20 +9,20 @@ chosen { linux,initrd-end = <0x85c43a00>; linux,initrd-start = <0x84200000>; - bootargs = "root=/dev/vda ro"; + bootargs = "root=/dev/vda ro console=ttyS0,115200"; stdout-path = "/soc/uart@10000000"; }; memory@80000000 { device_type = "memory"; - reg = <0x00 0x80000000 0x00 0x08000000>; + reg = <0x00 0x80000000 0x00 0x10000000>; }; cpus { #address-cells = <0x01>; #size-cells = <0x00>; - clock-frequency = <0x2FAF080>; - timebase-frequency = <0x2FAF080>; + clock-frequency = <0x43B5FC0>; + timebase-frequency = <0x43B5FC0>; cpu@0 { phandle = <0x01>; @@ -51,7 +51,7 @@ uart@10000000 { interrupts = <0x0a>; interrupt-parent = <0x03>; - clock-frequency = <0x2FAF080>; + clock-frequency = <0x43B5FC0>; reg = <0x00 0x10000000 0x00 0x100>; compatible = "ns16550a"; }; @@ -74,10 +74,8 @@ fifo-depth = <256>; bus-width = <4>; interrupt-parent = <0x03>; - clock = <0x2FAF080>; - max-frequency = <0x989680>; - cap-sd-highspeed; - cap-mmc-highspeed; + clock = <0x43B5FC0>; + max-frequency = <0xF4240>; no-sdio; }; diff --git a/src/wrappers/wallypipelinedcorewrapper.sv b/src/wrappers/wallypipelinedcorewrapper.sv deleted file mode 100644 index 09309bf0e..000000000 --- a/src/wrappers/wallypipelinedcorewrapper.sv +++ /dev/null @@ -1,56 +0,0 @@ -/////////////////////////////////////////// -// wallypipelinedcorewrapper.sv -// -// Written: Kevin Kim kekim@hmc.edu 21 August 2023 -// Modified: -// -// Purpose: A wrapper to set parameters. Vivado cannot set the top level parameters because it only supports verilog, -// not system verilog. -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -//`include "BranchPredictorType.vh" -`include "config.vh" - -import cvw::*; - -`include "parameter-defs.vh" -module wallypipelinedcorewrapper ( - input logic clk, reset, - // Privileged - input logic MTimerInt, MExtInt, SExtInt, MSwInt, - input logic [63:0] MTIME_CLINT, - // Bus Interface - input logic [P.XLEN-1:0] HRDATA, - input logic HREADY, HRESP, - output logic HCLK, HRESETn, - output logic [P.PA_BITS-1:0] HADDR, - output logic [32-1:0] HWDATA, - output logic [32/8-1:0] HWSTRB, - output logic HWRITE, - output logic [2:0] HSIZE, - output logic [2:0] HBURST, - output logic [3:0] HPROT, - output logic [1:0] HTRANS, - output logic HMASTLOCK -); - - wallypipelinedcore #(P) core(.*); - -endmodule diff --git a/synthDC/Makefile b/synthDC/Makefile index 64dd497a7..57b478795 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -3,7 +3,6 @@ # Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022 # Madeleine Masser-Frye (mmasserfrye@hmc.edu) 1/27/2023 NAME := synth - # defaults export DESIGN ?= wallypipelinedcore export FREQ ?= 10000 @@ -18,9 +17,12 @@ export TECH ?= sky90 export MAXCORES ?= 1 # MAXOPT turns on flattening, boundary optimization, and retiming # The output netlist is hard to interpret, but significantly better PPA +# WRAPPER turns on wrapper generation export MAXOPT ?= 0 export DRIVE ?= FLOP export USESRAM ?= 0 +export WRAPPER ?= 0 + time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) @@ -119,6 +121,10 @@ ifeq ($(SAIFPOWER), 1) endif +mkwrapper: +ifeq ($(WRAPPER),1) + python3 $(WALLY)/synthDC/scripts/wrapperGen.py $(DESIGN) +endif mkdirecs: @echo "DC Synthesis" @mkdir -p $(OUTPUTDIR) @@ -128,7 +134,7 @@ mkdirecs: @mkdir -p $(OUTPUTDIR)/mapped @mkdir -p $(OUTPUTDIR)/unmapped -synth: mkdirecs configs rundc # clean +synth: mkwrapper mkdirecs configs rundc # clean rundc: ifeq ($(TECH), tsmc28psyn) @@ -148,3 +154,4 @@ clean: rm -f power.saif rm -f Synopsys_stack_trace_*.txt rm -f crte_*.txt + rm $(WALLY)/synthDC/wrappers/* \ No newline at end of file diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index e75557874..075bb5db9 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -16,6 +16,7 @@ suppress_message {VER-173} # Enable Multicore set_host_options -max_cores $::env(MAXCORES) + # get outputDir and configDir from environment (Makefile) set outputDir $::env(OUTPUTDIR) set cfg $::env(CONFIGDIR) @@ -23,12 +24,17 @@ set hdl_src "../src" set saifpower $::env(SAIFPOWER) set maxopt $::env(MAXOPT) set drive $::env(DRIVE) +set wrapper $::env(WRAPPER) eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/} #eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} +if {$wrapper ==1 } { + eval file copy -force [glob ${hdl_src}/../synthDC/wrappers/$::env(DESIGN)wrapper.sv] {$outputDir/hdl/} +} + # Only for FMA class project; comment out when done # eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/} @@ -42,7 +48,11 @@ if { $saifpower == 1 } { set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv] # Set toplevel -set my_toplevel $::env(DESIGN) +if { $wrapper == 1 } { + set my_toplevel $::env(DESIGN)wrapper +} else { + set my_toplevel $::env(DESIGN) +} # Set number of significant digits set report_default_significant_digits 6 @@ -403,4 +413,4 @@ set t2 [clock seconds] set t [expr $t2 - $t1] echo [expr $t/60] -quit +quit \ No newline at end of file diff --git a/synthDC/scripts/wrapperGen.py b/synthDC/scripts/wrapperGen.py old mode 100644 new mode 100755 index 84c04f1fd..aacdb0634 --- a/synthDC/scripts/wrapperGen.py +++ b/synthDC/scripts/wrapperGen.py @@ -1,3 +1,4 @@ +#!/usr/bin/python3 """ wrapperGen.py @@ -7,16 +8,19 @@ script that generates top-level wrappers for verilog modules to synthesize """ import argparse +import glob import os #create argument parser parser = argparse.ArgumentParser() -parser.add_argument("fin") +parser.add_argument("DESIGN") args=parser.parse_args() -fin = open(args.fin, "r") +fin_path = glob.glob(f"{os.getenv('WALLY')}/src/**/{args.DESIGN}.sv",recursive=True)[0] + +fin = open(fin_path, "r") lines = fin.readlines() @@ -55,12 +59,11 @@ for l in lines: # post-processing buffer: add DUT and endmodule lines buf += f"\t{moduleName} #(P) dut(.*);\nendmodule" - # path to wrapper -wrapperPath = f"{os.getenv('WALLY')}/src/wrappers/{moduleName}wrapper.sv" +wrapperPath = f"{os.getenv('WALLY')}/synthDC/wrappers/{moduleName}wrapper.sv" # clear wrappers directory -os.system(f"rm {os.getenv('WALLY')}/src/wrappers/*") +os.system(f"rm {os.getenv('WALLY')}/synthDC/wrappers/*") fout = open(wrapperPath, "w") diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv index 0ca45420a..41a6db450 100644 --- a/testbench/testbench_imperas.sv +++ b/testbench/testbench_imperas.sv @@ -60,6 +60,7 @@ module testbench; logic [P.AHBW-1:0] HRDATAEXT; logic HREADYEXT, HRESPEXT; + logic HSELEXTSDC; logic [P.PA_BITS-1:0] HADDR; logic [P.AHBW-1:0] HWDATA; logic [P.XLEN/8-1:0] HWSTRB; @@ -81,13 +82,7 @@ module testbench; logic [31:0] GPIOIN, GPIOOUT, GPIOEN; logic UARTSin, UARTSout; - logic SDCCLK; - logic SDCCmdIn; - logic SDCCmdOut; - logic SDCCmdOE; - logic [3:0] SDCDatIn; - tri1 [3:0] SDCDat; - tri1 SDCCmd; + logic SDCIntr; logic HREADY; logic HSELEXT; @@ -239,6 +234,8 @@ module testbench; end if(P.FPGA) begin : sdcard + // *** fix later +/* -----\/----- EXCLUDED -----\/----- sdModel sdcard (.sdClk(SDCCLK), .cmd(SDCCmd), @@ -247,15 +244,16 @@ module testbench; assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz; assign SDCCmdIn = SDCCmd; assign SDCDatIn = SDCDat; + -----/\----- EXCLUDED -----/\----- */ + assign SDCIntr = '0; end else begin - assign SDCCmd = '0; - assign SDCDat = '0; + assign SDCIntr = '0; end - wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, + wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); + .UARTSin, .UARTSout, .SDCIntr); // Track names of instructions instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,