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dc shell setup.

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This commit is contained in:
Ross Thompson 2023-02-16 11:06:53 -06:00
parent b62bacbac3
commit dd4064ea56
1 changed files with 18 additions and 33 deletions
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51
synthDC/.synopsys_dc.setup
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@ -3,39 +3,30 @@
set CURRENT_DIR [exec pwd]
set search_path [list "./" ]
set tech $::env(TECH)
if { [info exists ::env(RISCV)] } {
set timing_lib $::env(RISCV)/cad/lib
} else {
set timing_lib ../addins
}
if {$tech == "sky130"} {
set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib
lappend search_path $s8lib
} elseif {$tech == "sky90"} {
set s9lib $timing_lib/sky90/sky90_sc/V1.7.4/lib
lappend search_path $s9lib
} elseif {$tech == "tsmc28"} {
set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
lappend search_path $s10lib
}
set memory ../memory
set pdk /import/yukari1/pdk/TSMC/28/CMOS/HPC+/stclib/7-track/tcbn28hpcplusbwp7t30p140-set/
set tsmc28nlib $pdk/tcbn28hpcplusbwp7t30p140_190a_FE/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp7t30p140_180a
set iolib1p8 /import/yukari1/pdk/TSMC/28/CMOS/HPC+/IO1.8V/iolib/STAGGERED/tphn28hpcpgv18_170d_FE/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tphn28hpcpgv18_170a/
lappend search_path $tsmc28nlib
lappend search_path $iolib1p8
lappend search_path $memory
# Synthetic libraries
set synthetic_library [list dw_foundation.sldb]
# Set standard cell libraries
# Set OKSTATE standard cell libraries
set target_library [list]
#lappend target_library scc9gena_tt_1.2v_25C.db
if {$tech == "sky130"} {
lappend target_library $s8lib/sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db
} elseif {$tech == "sky90"} {
lappend target_library $s9lib/scc9gena_tt_1.2v_25C.db
} elseif {$tech == "tsmc28"} {
lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db
}
lappend target_library $iolib1p8/tphn28hpcpgv18tt0p9v1p8v25c.db
lappend target_library $tsmc28nlib/tcbn28hpcplusbwp7t30p140tt0p9v25c.db
lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db
lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db
lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db
lappend target_library $memory/tsdn28hpcpa1024x68m4mw_130a/NLDM/tsdn28hpcpa1024x68m4mw_tt0p9v25c.db
lappend target_library $memory/tsdn28hpcpa64x32m4mw_130a/NLDM/tsdn28hpcpa64x32m4mw_tt0p9v25c.db
lappend target_library $memory/dbs/tsdn28hpcpa128x64m4fw_tt0p9v25c.db
lappend target_library $memory/dbs/tsdn28hpcpa512x64m4fw_tt0p9v25c.db
lappend target_library $memory/dbs/tsdn28hpcpa2048x64m4mw_tt0p9v25c.db
# Set Link Library
set link_library "$target_library $synthetic_library"
@ -48,12 +39,6 @@ set cache_read $cache_write
lappend search_path ./scripts
lappend search_path ./hdl
lappend search_path ./mapped
if {$tech == "tsmc28"} {
set memory /home/jstine/WallyMem/rv64gc/
lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db
lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db
lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db
}
# Set up User Information
set company "Oklahoma State University"