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https://github.com/openhwgroup/cvw
synced 2025-02-03 02:05:21 +00:00
busybear: slightly neater error handling
This commit is contained in:
Noah Boorstin
parent
79fb83409f
commit
dd3a5b74a1
@ -50,7 +50,7 @@ module testbench_busybear();
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data_file_PC = $fopen("/courses/e190ax/busybear_boot/parsedPC.txt", "r");
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if (data_file_PC == 0) begin
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$display("file couldn't be opened");
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#10; $stop;
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$stop;
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end
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end
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@ -59,7 +59,7 @@ module testbench_busybear();
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data_file_PCW = $fopen("/courses/e190ax/busybear_boot/parsedPC.txt", "r");
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if (data_file_PCW == 0) begin
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$display("file couldn't be opened");
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#10; $stop;
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$stop;
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end
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end
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@ -69,7 +69,7 @@ module testbench_busybear();
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data_file_rf = $fopen("/courses/e190ax/busybear_boot/parsedRegs.txt", "r");
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if (data_file_rf == 0) begin
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$display("file couldn't be opened");
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#10; $stop;
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$stop;
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end
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end
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@ -79,7 +79,7 @@ module testbench_busybear();
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data_file_csr = $fopen("/courses/e190ax/busybear_boot/parsedCSRs.txt", "r");
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if (data_file_csr == 0) begin
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$display("file couldn't be opened");
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#10; $stop;
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$stop;
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end
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end
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@ -89,7 +89,7 @@ module testbench_busybear();
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data_file_memR = $fopen("/courses/e190ax/busybear_boot/parsedMemRead.txt", "r");
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if (data_file_memR == 0) begin
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$display("file couldn't be opened");
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#10; $stop;
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$stop;
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end
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end
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@ -99,9 +99,14 @@ module testbench_busybear();
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data_file_memW = $fopen("/courses/e190ax/busybear_boot/parsedMemWrite.txt", "r");
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if (data_file_memW == 0) begin
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$display("file couldn't be opened");
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#10; $stop;
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$stop;
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end
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end
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integer warningCount = 0;
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`define ERROR \
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#10; \
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$display("processed %0d instructions with %0d warnings", instrs, warningCount); \
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$stop;
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logic [63:0] pcExpected;
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logic [63:0] regExpected;
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@ -115,7 +120,7 @@ module testbench_busybear();
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scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
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if (dut.ieu.dp.regf.rf[i] != regExpected) begin
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$display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.ieu.dp.regf.rf[i], regExpected);
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#10; $stop;
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`ERROR
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end
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end else begin
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scan_file_rf = $fscanf(data_file_rf, "%d\n", regNumExpected);
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@ -125,7 +130,7 @@ module testbench_busybear();
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end
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if (dut.ieu.dp.regf.rf[i] != regExpected) begin
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$display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.ieu.dp.regf.rf[i], regExpected);
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#10; $stop;
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`ERROR
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end
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end
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end
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@ -138,14 +143,14 @@ module testbench_busybear();
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if (dut.MemRWM[1]) begin
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if($feof(data_file_memR)) begin
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$display("no more memR data to read");
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#10; $stop;
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`ERROR
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end
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scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
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scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA);
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#1;
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if (HADDR != readAdrExpected) begin
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$display("%t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected);
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#10; $stop;
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`ERROR
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end
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end
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end
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@ -157,17 +162,17 @@ module testbench_busybear();
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if (HWRITE) begin
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if($feof(data_file_memW)) begin
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$display("no more memW data to read");
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#10; $stop;
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`ERROR
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end
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected);
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if (writeDataExpected != HWDATA) begin
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$display("%t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected);
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#10; $stop;
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`ERROR
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end
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if (writeAdrExpected != HADDR) begin
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$display("%t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrExpected);
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#10; $stop;
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`ERROR
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end
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end
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end
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@ -199,14 +204,14 @@ module testbench_busybear();
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end \
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if(``PATH``.``CSR``_REGW != ``expected``CSR) begin \
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$display("%t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", CSR, ``PATH``.``CSR``_REGW, ``expected``CSR); \
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#10; $stop; \
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`ERROR \
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end \
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end else begin \
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for(integer j=0; j<totalCSR; j++) begin \
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if(!StartCSRname[j].icompare(`"CSR`")) begin \
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if(``PATH``.``CSR``_REGW != StartCSRexpected[j]) begin \
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$display("%t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", StartCSRname[j], ``PATH``.``CSR``_REGW, StartCSRexpected[j]); \
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#10; $stop; \
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`ERROR \
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end \
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end \
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end \
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@ -244,7 +249,7 @@ module testbench_busybear();
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if(dut.ieu.InstrValidW && dut.ifu.PCW != 0) begin
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if($feof(data_file_PCW)) begin
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$display("no more PC data to read");
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#10; $stop;
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`ERROR
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end
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scan_file_PCW = $fscanf(data_file_PCW, "%s\n", PCtextW);
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if (PCtextW != "ret" && PCtextW != "fence" && PCtextW != "nop" && PCtextW != "mret" && PCtextW != "sfence.vma" && PCtextW != "unimp") begin
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@ -256,7 +261,7 @@ module testbench_busybear();
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scan_file_PCW = $fscanf(data_file_PCW, "%x\n", PCWExpected);
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if(dut.ifu.PCW != PCWExpected) begin
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$display("%t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, dut.ifu.PCW, PCWExpected);
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#10; $stop;
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`ERROR
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end
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//if(it.InstrW != InstrWExpected) begin
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// $display("%t ps, instr %0d: InstrW does not equal InstrW expected: %x, %x", $time, instrs, it.InstrW, InstrWExpected);
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@ -277,12 +282,10 @@ module testbench_busybear();
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speculative = (PCF != pcExpected);
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end
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else begin
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//if (~speculative) begin
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if($feof(data_file_PC)) begin
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$display("no more PC data to read");
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#10; $stop;
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`ERROR
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end
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// first read instruction
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scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext);
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if (PCtext != "ret" && PCtext != "fence" && PCtext != "nop" && PCtext != "mret" && PCtext != "sfence.vma" && PCtext != "unimp") begin
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scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2);
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@ -292,10 +295,12 @@ module testbench_busybear();
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if(InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
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InstrF = 32'b0010011;
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$display("warning: NOPing out %s at PC=%0x", PCtext, PCF);
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warningCount += 1;
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end
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if(InstrF[28:27] != 2'b11 && InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
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InstrF = {12'b0, InstrF[19:7], 7'b0000011};
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$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, PCF);
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warningCount += 1;
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end
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// then expected PC value
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scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
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@ -329,7 +334,7 @@ module testbench_busybear();
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//check things!
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if ((~speculative) && (PCF !== pcExpected)) begin
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$display("%t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, PCF, pcExpected);
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#10; $stop;
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`ERROR
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end
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end
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end
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@ -349,17 +354,4 @@ module testbench_busybear();
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clk <= 1; # 5; clk <= 0; # 5;
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end
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//// check results
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//always @(negedge clk)
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// begin
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// if(MemWrite) begin
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// if(DataAdr === 84 & WriteData === 71) begin
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// $display("Simulation succeeded");
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// #10; $stop;
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// end else if (DataAdr !== 80) begin
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// $display("Simulation failed");
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// #10; $stop;
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// end
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// end
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// end
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endmodule
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