Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-03 02:05:21 +00:00
Code Issues Packages Projects Releases Wiki Activity

busybear: slightly neater error handling

Browse Source
This commit is contained in:
Noah Boorstin 2021-02-12 17:21:56 +00:00
parent 79fb83409f
commit dd3a5b74a1
1 changed files with 26 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

60
wally-pipelined/testbench/testbench-busybear.sv
View File

@ -50,7 +50,7 @@ module testbench_busybear();
data_file_PC = $fopen("/courses/e190ax/busybear_boot/parsedPC.txt", "r"); data_file_PC = $fopen("/courses/e190ax/busybear_boot/parsedPC.txt", "r");
if (data_file_PC == 0) begin if (data_file_PC == 0) begin
$display("file couldn't be opened"); $display("file couldn't be opened");
#10; $stop; $stop;
end end
end end
@ -59,7 +59,7 @@ module testbench_busybear();
data_file_PCW = $fopen("/courses/e190ax/busybear_boot/parsedPC.txt", "r"); data_file_PCW = $fopen("/courses/e190ax/busybear_boot/parsedPC.txt", "r");
if (data_file_PCW == 0) begin if (data_file_PCW == 0) begin
$display("file couldn't be opened"); $display("file couldn't be opened");
#10; $stop; $stop;
end end
end end
@ -69,7 +69,7 @@ module testbench_busybear();
data_file_rf = $fopen("/courses/e190ax/busybear_boot/parsedRegs.txt", "r"); data_file_rf = $fopen("/courses/e190ax/busybear_boot/parsedRegs.txt", "r");
if (data_file_rf == 0) begin if (data_file_rf == 0) begin
$display("file couldn't be opened"); $display("file couldn't be opened");
#10; $stop; $stop;
end end
end end
@ -79,7 +79,7 @@ module testbench_busybear();
data_file_csr = $fopen("/courses/e190ax/busybear_boot/parsedCSRs.txt", "r"); data_file_csr = $fopen("/courses/e190ax/busybear_boot/parsedCSRs.txt", "r");
if (data_file_csr == 0) begin if (data_file_csr == 0) begin
$display("file couldn't be opened"); $display("file couldn't be opened");
#10; $stop; $stop;
end end
end end
@ -89,7 +89,7 @@ module testbench_busybear();
data_file_memR = $fopen("/courses/e190ax/busybear_boot/parsedMemRead.txt", "r"); data_file_memR = $fopen("/courses/e190ax/busybear_boot/parsedMemRead.txt", "r");
if (data_file_memR == 0) begin if (data_file_memR == 0) begin
$display("file couldn't be opened"); $display("file couldn't be opened");
#10; $stop; $stop;
end end
end end
@ -99,9 +99,14 @@ module testbench_busybear();
data_file_memW = $fopen("/courses/e190ax/busybear_boot/parsedMemWrite.txt", "r"); data_file_memW = $fopen("/courses/e190ax/busybear_boot/parsedMemWrite.txt", "r");
if (data_file_memW == 0) begin if (data_file_memW == 0) begin
$display("file couldn't be opened"); $display("file couldn't be opened");
#10; $stop; $stop;
end end
end end
integer warningCount = 0;
`define ERROR \
#10; \
$display("processed %0d instructions with %0d warnings", instrs, warningCount); \
$stop;
logic [63:0] pcExpected; logic [63:0] pcExpected;
logic [63:0] regExpected; logic [63:0] regExpected;
@ -115,7 +120,7 @@ module testbench_busybear();
scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected); scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
if (dut.ieu.dp.regf.rf[i] != regExpected) begin if (dut.ieu.dp.regf.rf[i] != regExpected) begin
$display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.ieu.dp.regf.rf[i], regExpected); $display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.ieu.dp.regf.rf[i], regExpected);
#10; $stop; `ERROR
end end
end else begin end else begin
scan_file_rf = $fscanf(data_file_rf, "%d\n", regNumExpected); scan_file_rf = $fscanf(data_file_rf, "%d\n", regNumExpected);
@ -125,7 +130,7 @@ module testbench_busybear();
end end
if (dut.ieu.dp.regf.rf[i] != regExpected) begin if (dut.ieu.dp.regf.rf[i] != regExpected) begin
$display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.ieu.dp.regf.rf[i], regExpected); $display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.ieu.dp.regf.rf[i], regExpected);
#10; $stop; `ERROR
end end
end end
end end
@ -138,14 +143,14 @@ module testbench_busybear();
if (dut.MemRWM[1]) begin if (dut.MemRWM[1]) begin
if($feof(data_file_memR)) begin if($feof(data_file_memR)) begin
$display("no more memR data to read"); $display("no more memR data to read");
#10; $stop; `ERROR
end end
scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected); scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA); scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA);
#1; #1;
if (HADDR != readAdrExpected) begin if (HADDR != readAdrExpected) begin
$display("%t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected); $display("%t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected);
#10; $stop; `ERROR
end end
end end
end end
@ -157,17 +162,17 @@ module testbench_busybear();
if (HWRITE) begin if (HWRITE) begin
if($feof(data_file_memW)) begin if($feof(data_file_memW)) begin
$display("no more memW data to read"); $display("no more memW data to read");
#10; $stop; `ERROR
end end
scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected); scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected); scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected);
if (writeDataExpected != HWDATA) begin if (writeDataExpected != HWDATA) begin
$display("%t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected); $display("%t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected);
#10; $stop; `ERROR
end end
if (writeAdrExpected != HADDR) begin if (writeAdrExpected != HADDR) begin
$display("%t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrExpected); $display("%t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrExpected);
#10; $stop; `ERROR
end end
end end
end end
@ -199,14 +204,14 @@ module testbench_busybear();
end \ end \
if(``PATH``.``CSR``_REGW != ``expected``CSR) begin \ if(``PATH``.``CSR``_REGW != ``expected``CSR) begin \
$display("%t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", CSR, ``PATH``.``CSR``_REGW, ``expected``CSR); \ $display("%t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", CSR, ``PATH``.``CSR``_REGW, ``expected``CSR); \
#10; $stop; \ `ERROR \
end \ end \
end else begin \ end else begin \
for(integer j=0; j<totalCSR; j++) begin \ for(integer j=0; j<totalCSR; j++) begin \
if(!StartCSRname[j].icompare(`"CSR`")) begin \ if(!StartCSRname[j].icompare(`"CSR`")) begin \
if(``PATH``.``CSR``_REGW != StartCSRexpected[j]) begin \ if(``PATH``.``CSR``_REGW != StartCSRexpected[j]) begin \
$display("%t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", StartCSRname[j], ``PATH``.``CSR``_REGW, StartCSRexpected[j]); \ $display("%t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", StartCSRname[j], ``PATH``.``CSR``_REGW, StartCSRexpected[j]); \
#10; $stop; \ `ERROR \
end \ end \
end \ end \
end \ end \
@ -244,7 +249,7 @@ module testbench_busybear();
if(dut.ieu.InstrValidW && dut.ifu.PCW != 0) begin if(dut.ieu.InstrValidW && dut.ifu.PCW != 0) begin
if($feof(data_file_PCW)) begin if($feof(data_file_PCW)) begin
$display("no more PC data to read"); $display("no more PC data to read");
#10; $stop; `ERROR
end end
scan_file_PCW = $fscanf(data_file_PCW, "%s\n", PCtextW); scan_file_PCW = $fscanf(data_file_PCW, "%s\n", PCtextW);
if (PCtextW != "ret" && PCtextW != "fence" && PCtextW != "nop" && PCtextW != "mret" && PCtextW != "sfence.vma" && PCtextW != "unimp") begin if (PCtextW != "ret" && PCtextW != "fence" && PCtextW != "nop" && PCtextW != "mret" && PCtextW != "sfence.vma" && PCtextW != "unimp") begin
@ -256,7 +261,7 @@ module testbench_busybear();
scan_file_PCW = $fscanf(data_file_PCW, "%x\n", PCWExpected); scan_file_PCW = $fscanf(data_file_PCW, "%x\n", PCWExpected);
if(dut.ifu.PCW != PCWExpected) begin if(dut.ifu.PCW != PCWExpected) begin
$display("%t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, dut.ifu.PCW, PCWExpected); $display("%t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, dut.ifu.PCW, PCWExpected);
#10; $stop; `ERROR
end end
//if(it.InstrW != InstrWExpected) begin //if(it.InstrW != InstrWExpected) begin
// $display("%t ps, instr %0d: InstrW does not equal InstrW expected: %x, %x", $time, instrs, it.InstrW, InstrWExpected); // $display("%t ps, instr %0d: InstrW does not equal InstrW expected: %x, %x", $time, instrs, it.InstrW, InstrWExpected);
@ -277,12 +282,10 @@ module testbench_busybear();
speculative = (PCF != pcExpected); speculative = (PCF != pcExpected);
end end
else begin else begin
//if (~speculative) begin
if($feof(data_file_PC)) begin if($feof(data_file_PC)) begin
$display("no more PC data to read"); $display("no more PC data to read");
#10; $stop; `ERROR
end end
// first read instruction
scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext); scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext);
if (PCtext != "ret" && PCtext != "fence" && PCtext != "nop" && PCtext != "mret" && PCtext != "sfence.vma" && PCtext != "unimp") begin if (PCtext != "ret" && PCtext != "fence" && PCtext != "nop" && PCtext != "mret" && PCtext != "sfence.vma" && PCtext != "unimp") begin
scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2); scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2);
@ -292,10 +295,12 @@ module testbench_busybear();
if(InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs if(InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
InstrF = 32'b0010011; InstrF = 32'b0010011;
$display("warning: NOPing out %s at PC=%0x", PCtext, PCF); $display("warning: NOPing out %s at PC=%0x", PCtext, PCF);
warningCount += 1;
end end
if(InstrF[28:27] != 2'b11 && InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD if(InstrF[28:27] != 2'b11 && InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
InstrF = {12'b0, InstrF[19:7], 7'b0000011}; InstrF = {12'b0, InstrF[19:7], 7'b0000011};
$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, PCF); $display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, PCF);
warningCount += 1;
end end
// then expected PC value // then expected PC value
scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected); scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
@ -329,7 +334,7 @@ module testbench_busybear();
//check things! //check things!
if ((~speculative) && (PCF !== pcExpected)) begin if ((~speculative) && (PCF !== pcExpected)) begin
$display("%t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, PCF, pcExpected); $display("%t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, PCF, pcExpected);
#10; $stop; `ERROR
end end
end end
end end
@ -349,17 +354,4 @@ module testbench_busybear();
clk <= 1; # 5; clk <= 0; # 5; clk <= 1; # 5; clk <= 0; # 5;
end end
//// check results
//always @(negedge clk)
// begin
// if(MemWrite) begin
// if(DataAdr === 84 & WriteData === 71) begin
// $display("Simulation succeeded");
// #10; $stop;
// end else if (DataAdr !== 80) begin
// $display("Simulation failed");
// #10; $stop;
// end
// end
// end
endmodule endmodule