From dd33479056f154d4047ecd562836cfc4451beb2d Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 6 Mar 2024 04:59:58 -0800 Subject: [PATCH] Switched to ?: for gating per section 4.2.4.3 --- src/fpu/fma/fmaadd.sv | 4 ++-- src/privileged/trap.sv | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/fpu/fma/fmaadd.sv b/src/fpu/fma/fmaadd.sv index 56f4a80cb..d408381c0 100644 --- a/src/fpu/fma/fmaadd.sv +++ b/src/fpu/fma/fmaadd.sv @@ -51,9 +51,9 @@ module fmaadd import cvw::*; #(parameter cvw_t P) ( /////////////////////////////////////////////////////////////////////////////// // Choose an inverted or non-inverted addend. Put carry into adder/LZA for addition - assign AmInv = {3*P.NF+4{InvA}}^Am; + assign AmInv = InvA ? ~Am : Am; // Kill the product if the product is too small to effect the addition (determined in fma1.sv) - assign PmKilled = {2*P.NF+2{~KillProd}}&Pm; + assign PmKilled = KillProd ? '0 : Pm; // Do the addition // - calculate a positive and negative sum in parallel // if there was a small negative number killed in the alignment stage one needs to be subtracted from the sum diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv index f20604379..469ff4e06 100644 --- a/src/privileged/trap.sv +++ b/src/privileged/trap.sv @@ -65,8 +65,8 @@ module trap import cvw::*; #(parameter cvw_t P) ( assign PendingIntsM = MIP_REGW & MIE_REGW; assign IntPendingM = |PendingIntsM; assign Committed = CommittedM | CommittedF; - assign EnabledIntsM = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW); - assign ValidIntsM = {12{~Committed}} & EnabledIntsM; + assign EnabledIntsM = (MIntGlobalEnM ? PendingIntsM & ~MIDELEG_REGW : '0) | (SIntGlobalEnM ? PendingIntsM & MIDELEG_REGW : '0); + assign ValidIntsM = Committed ? '0 : EnabledIntsM; assign InterruptM = (|ValidIntsM) & InstrValidM & (~wfiM | wfiW); // suppress interrupt if the memory system has partially processed a request. Delay interrupt until wfi is in the W stage. // wfiW is to support possible but unlikely back to back wfi instructions. wfiM would be high in the M stage, while also in the W stage. assign DelegateM = P.S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) &