From dd0a02f0c8b4902232bb44745df067c08fbfbdb3 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 20 Dec 2022 16:24:04 -0800
Subject: [PATCH] Converted tvecmux to structural

---
 pipelined/regression/lint-wally |  2 +-
 pipelined/src/privileged/csr.sv | 17 ++++++++++-------
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/pipelined/regression/lint-wally b/pipelined/regression/lint-wally
index eaeb1f518..b51797e66 100755
--- a/pipelined/regression/lint-wally
+++ b/pipelined/regression/lint-wally
@@ -8,7 +8,7 @@ basepath=$(dirname $0)/..
 #for config in rv32e rv64gc rv32gc rv32ic rv32i rv64i rv64fpquad; do
 for config in  rv64gc; do
     echo "$config linting..."
-    if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes --Wall); then
+    if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
         echo "Exiting after $config lint due to errors or warnings"
         exit 1
     fi
diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv
index c14a7a000..75e635895 100644
--- a/pipelined/src/privileged/csr.sv
+++ b/pipelined/src/privileged/csr.sv
@@ -100,8 +100,9 @@ module csr #(parameter
   logic [`XLEN-1:0] TVec, TrapVector, NextFaultMtvalM;
   logic MTrapM, STrapM;
 
-  logic [`XLEN-1:0] XEPC_REG;
+  logic [`XLEN-1:0] EPC;
   logic 			RetM;
+  logic       SelMtvec;
   
   logic InstrValidNotFlushedM;
   assign InstrValidNotFlushedM = ~StallW & ~FlushW;
@@ -120,7 +121,7 @@ module csr #(parameter
     endcase
 
   ///////////////////////////////////////////
-  // Trap Vectoring
+  // Trap Vectoring & Returns
   ///////////////////////////////////////////
   //
   // POSSIBLE OPTIMIZATION: 
@@ -131,9 +132,8 @@ module csr #(parameter
   // [untested] TrapVector = {TVec[`XLEN-1:7], CauseM[3:0], 4'b0000}
   // However, this is program dependent, so not implemented at this time.
 
-  always_comb
-    if (NextPrivilegeModeM == `S_MODE) TVec = STVEC_REGW;
-    else                               TVec = MTVEC_REGW; 
+  assign SelMtvec = (NextPrivilegeModeM == `M_MODE);
+  mux2 #(`XLEN) tvecmux(STVEC_REGW, MTVEC_REGW, SelMtvec, TVec);
 
   if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec
       always_comb
@@ -146,9 +146,12 @@ module csr #(parameter
     assign TrapVector = {TVec[`XLEN-1:2], 2'b00};
   end
 
+  // Trap Returns
+  // A trap sets the PC to TrapVector
+  // A return sets the PC to MEPC or SEPC
   assign RetM = mretM | sretM;
-  mux2 #(`XLEN) xepcMux(SEPC_REGW, MEPC_REGW, mretM, XEPC_REG);
-  mux3 #(`XLEN) pcmux3(PCNext2F, XEPC_REG, TrapVector, {TrapM, RetM}, UnalignedPCNextF);
+  mux2 #(`XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPC);
+  mux3 #(`XLEN) pcmux3(PCNext2F, EPC, TrapVector, {TrapM, RetM}, UnalignedPCNextF);
   
 
   ///////////////////////////////////////////