From dcfb68daeeed2b76d9127c3b8b8c56cec4b71312 Mon Sep 17 00:00:00 2001
From: Jacob Pease <jacobpease@protonmail.com>
Date: Fri, 13 Jan 2023 14:36:23 -0600
Subject: [PATCH] Added IPs to wally.tcl.

---
 fpga/generator/wally.tcl |  3 ++
 fpga/src/fpgaTop.v       | 73 ----------------------------------------
 2 files changed, 3 insertions(+), 73 deletions(-)

diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index a032a866c..4399656b5 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -16,6 +16,9 @@ read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
 
 # Added crossbar - Jacob Pease <2023-01-12 Thu>
 read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossbar.xci
+read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci
+read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci
+
 
 
 read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv]
diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v
index 48c475b4f..300cfe801 100644
--- a/fpga/src/fpgaTop.v
+++ b/fpga/src/fpgaTop.v
@@ -486,79 +486,6 @@ module fpgaTop
      .m_axi_rvalid(m_axi_rvalid),
      .m_axi_rlast(m_axi_rlast),
      .m_axi_rready(m_axi_rready));
-   
-  wire [3:0] 	   s00_axi_awid;
-  wire [7:0] 	   s00_axi_awlen;
-  wire [2:0] 	   s00_axi_awsize;
-  wire [1:0] 	   s00_axi_awburst;
-  wire [3:0] 	   s00_axi_awcache;
-  wire [31:0] 	   s00_axi_awaddr;
-  wire [2:0] 	   s00_axi_awprot;
-  wire 		   s00_axi_awvalid;
-  wire 		   s00_axi_awready;
-  wire 		   s00_axi_awlock;
-  wire [63:0] 	   s00_axi_wdata;
-  wire [7:0] 	   s00_axi_wstrb;
-  wire 		   s00_axi_wlast;
-  wire 		   s00_axi_wvalid;
-  wire 		   s00_axi_wready;
-  wire [3:0] 	   s00_axi_bid;
-  wire [1:0] 	   s00_axi_bresp;
-  wire 		   s00_axi_bvalid;
-  wire 		   s00_axi_bready;
-  wire [3:0] 	   s00_axi_arid;
-  wire [7:0] 	   s00_axi_arlen;
-  wire [2:0] 	   s00_axi_arsize;
-  wire [1:0] 	   s00_axi_arburst;
-  wire [2:0] 	   s00_axi_arprot;
-  wire [3:0] 	   s00_axi_arcache;
-  wire 		   s00_axi_arvalid;
-  wire [31:0] 	   s00_axi_araddr;
-  wire 			   s00_axi_arlock;
-  wire 		   s00_axi_arready;
-  wire [3:0] 	   s00_axi_rid;
-  wire [63:0] 	   s00_axi_rdata;
-  wire [1:0] 	   s00_axi_rresp;
-  wire 		   s00_axi_rvalid;
-  wire 		   s00_axi_rlast;
-  wire 		   s00_axi_rready;
-
-  wire [3:0]  s01_axi_awid;
-  wire [7:0] 	   s01_axi_awlen;
-  wire [2:0] 	   s01_axi_awsize;
-  wire [1:0] 	   s01_axi_awburst;
-  wire [3:0] 	   s01_axi_awcache;
-  wire [31:0] 	   s01_axi_awaddr;
-  wire [2:0] 	   s01_axi_awprot;
-  wire 		   s01_axi_awvalid;
-  wire 		   s01_axi_awready;
-  wire 		   s01_axi_awlock;
-  wire [63:0] 	   s01_axi_wdata;
-  wire [7:0] 	   s01_axi_wstrb;
-  wire 		   s01_axi_wlast;
-  wire 		   s01_axi_wvalid;
-  wire 		   s01_axi_wready;
-  wire [3:0] 	   s01_axi_bid;
-  wire [1:0] 	   s01_axi_bresp;
-  wire 		   s01_axi_bvalid;
-  wire 		   s01_axi_bready;
-  wire [3:0] 	   s01_axi_arid;
-  wire [7:0] 	   s01_axi_arlen;
-  wire [2:0] 	   s01_axi_arsize;
-  wire [1:0] 	   s01_axi_arburst;
-  wire [2:0] 	   s01_axi_arprot;
-  wire [3:0] 	   s01_axi_arcache;
-  wire 		   s01_axi_arvalid;
-  wire [31:0] 	   s01_axi_araddr;
-  wire 			   s01_axi_arlock;
-  wire 		   s01_axi_arready;
-  wire [3:0] 	   s01_axi_rid;
-  wire [63:0] 	   s01_axi_rdata;
-  wire [1:0] 	   s01_axi_rresp;
-  wire 		   s01_axi_rvalid;
-  wire 		   s01_axi_rlast;
-  wire		   s01_axi_rready;
-
 
   // AXI Crossbar for arbitrating the SDC and CPU --------------
   xlnx_axi_crossbar xlnx_axi_crossbar_0