Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Renamed RW signals through the caches, bus interfaces, and IFU/LSU.

Browse Source 
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
This commit is contained in:
Ross Thompson 2022-09-23 11:46:53 -05:00
parent 6a6686a34b
commit dcc00ef4b3
9 changed files with 93 additions and 97 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
pipelined/src/cache/cache.sv vendored
View File

@ -54,8 +54,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
input logic Cacheable, input logic Cacheable,
input logic SelReplay, input logic SelReplay,
// Bus fsm interface // Bus fsm interface
output logic CacheFetchLine, output logic [1:0] CacheBusRW,
output logic CacheWriteLine,
input logic CacheBusAck, input logic CacheBusAck,
input logic SelBusWord, input logic SelBusWord,
input logic [LOGBWPL-1:0] WordCount, input logic [LOGBWPL-1:0] WordCount,
@ -212,7 +211,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
assign CacheRW = Cacheable ? RW : 2'b00; assign CacheRW = Cacheable ? RW : 2'b00;
assign CacheAtomic = Cacheable ? Atomic : 2'b00; assign CacheAtomic = Cacheable ? Atomic : 2'b00;
cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck, cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
.CacheRW, .CacheAtomic, .CPUBusy, .IgnoreRequestTLB, .TrapM, .CacheRW, .CacheAtomic, .CPUBusy, .IgnoreRequestTLB, .TrapM,
.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
.CacheMiss, .CacheAccess, .SelAdr, .CacheMiss, .CacheAccess, .SelAdr,

69
pipelined/src/cache/cachefsm.sv vendored
View File

@ -32,50 +32,49 @@
module cachefsm module cachefsm
(input logic clk, (input logic clk,
input logic reset, input logic reset,
// inputs from IEU // inputs from IEU
input logic [1:0] CacheRW, input logic [1:0] CacheRW,
input logic [1:0] CacheAtomic, input logic [1:0] CacheAtomic,
input logic FlushCache, input logic FlushCache,
input logic InvalidateCache, input logic InvalidateCache,
// hazard inputs // hazard inputs
input logic CPUBusy, input logic CPUBusy,
// interlock fsm // interlock fsm
input logic IgnoreRequestTLB, input logic IgnoreRequestTLB,
input logic TrapM, input logic TrapM,
// Bus inputs // Bus inputs
input logic CacheBusAck, input logic CacheBusAck,
// dcache internals // dcache internals
input logic CacheHit, input logic CacheHit,
input logic VictimDirty, input logic VictimDirty,
input logic FlushAdrFlag, input logic FlushAdrFlag,
input logic FlushWayFlag, input logic FlushWayFlag,
// hazard outputs // hazard outputs
output logic CacheStall, output logic CacheStall,
// counter outputs // counter outputs
output logic CacheMiss, output logic CacheMiss,
output logic CacheAccess, output logic CacheAccess,
// Bus outputs // Bus outputs
output logic CacheCommitted, output logic CacheCommitted,
output logic CacheWriteLine, output logic [1:0] CacheBusRW,
output logic CacheFetchLine,
// dcache internals // dcache internals
output logic SelAdr, output logic SelAdr,
output logic ClearValid, output logic ClearValid,
output logic ClearDirty, output logic ClearDirty,
output logic SetDirty, output logic SetDirty,
output logic SetValid, output logic SetValid,
output logic SelEvict, output logic SelEvict,
output logic LRUWriteEn, output logic LRUWriteEn,
output logic SelFlush, output logic SelFlush,
output logic FlushAdrCntEn, output logic FlushAdrCntEn,
output logic FlushWayCntEn, output logic FlushWayCntEn,
output logic FlushAdrCntRst, output logic FlushAdrCntRst,
output logic FlushWayCntRst, output logic FlushWayCntRst,
output logic SelBusBuffer, output logic SelBusBuffer,
output logic SRAMEnable); output logic SRAMEnable);
logic resetDelay; logic resetDelay;
logic AMO; logic AMO;
@ -194,8 +193,8 @@ module cachefsm
assign FlushAdrCntRst = (CurrState == STATE_READY); assign FlushAdrCntRst = (CurrState == STATE_READY);
assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR); assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR);
// Bus interface controls // Bus interface controls
assign CacheFetchLine = (CurrState == STATE_READY & DoAnyMiss) | (CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck); assign CacheBusRW[1] = (CurrState == STATE_READY & DoAnyMiss) | (CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck);
assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) | assign CacheBusRW[0] = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) |
(CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) | (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) |
(CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck) | (CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck) |
(CurrState == STATE_FLUSH_CHECK & VictimDirty); (CurrState == STATE_FLUSH_CHECK & VictimDirty);

2
pipelined/src/cache/cacheway.sv vendored
View File

@ -98,7 +98,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
// Data Array // Data Array
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
genvar words; genvar words;
localparam integer SRAMLEN = 128; localparam integer SRAMLEN = 128;
localparam integer NUMSRAM = LINELEN/SRAMLEN; localparam integer NUMSRAM = LINELEN/SRAMLEN;

8
pipelined/src/ebu/ahbcacheinterface.sv
View File

@ -50,14 +50,14 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
// cache interface // cache interface
input logic [`PA_BITS-1:0] CacheBusAdr, input logic [`PA_BITS-1:0] CacheBusAdr,
input logic [1:0] CacheRW, input logic [1:0] CacheBusRW,
output logic CacheBusAck, output logic CacheBusAck,
output logic [LINELEN-1:0] FetchBuffer, output logic [LINELEN-1:0] FetchBuffer,
output logic SelUncachedAdr, output logic SelUncachedAdr,
// lsu/ifu interface // lsu/ifu interface
input logic [`PA_BITS-1:0] PAdr, input logic [`PA_BITS-1:0] PAdr,
input logic [1:0] RW, input logic [1:0] BusRW,
input logic CPUBusy, input logic CPUBusy,
input logic [2:0] Funct3, input logic [2:0] Funct3,
output logic SelBusWord, output logic SelBusWord,
@ -83,7 +83,7 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE)); mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE));
buscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm( buscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
.HCLK, .HRESETn, .RW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord, .HCLK, .HRESETn, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord,
.CacheRW, .CacheBusAck, .SelUncachedAdr, .WordCount, .WordCountDelayed, .CacheBusRW, .CacheBusAck, .SelUncachedAdr, .WordCount, .WordCountDelayed,
.HREADY, .HTRANS, .HWRITE, .HBURST); .HREADY, .HTRANS, .HWRITE, .HBURST);
endmodule endmodule

4
pipelined/src/ebu/ahbinterface.sv
View File

@ -47,7 +47,7 @@ module ahbinterface #(parameter LSU = 0) // **** modify to use LSU/ifu parameter
output logic [`XLEN/8-1:0] HWSTRB, output logic [`XLEN/8-1:0] HWSTRB,
// lsu/ifu interface // lsu/ifu interface
input logic [1:0] RW, input logic [1:0] BusRW,
input logic [`XLEN/8-1:0] ByteMask, input logic [`XLEN/8-1:0] ByteMask,
input logic [`XLEN-1:0] WriteData, input logic [`XLEN-1:0] WriteData,
input logic CPUBusy, input logic CPUBusy,
@ -71,7 +71,7 @@ module ahbinterface #(parameter LSU = 0) // **** modify to use LSU/ifu parameter
assign HWSTRB = '0; assign HWSTRB = '0;
end end
busfsm busfsm(.HCLK, .HRESETn, .RW, busfsm busfsm(.HCLK, .HRESETn, .BusRW,
.BusCommitted, .CPUBusy, .BusStall, .CaptureEn, .HREADY, .BusCommitted, .CPUBusy, .BusStall, .CaptureEn, .HREADY,
.HTRANS, .HWRITE); .HTRANS, .HWRITE);
endmodule endmodule

44
pipelined/src/ebu/buscachefsm.sv
View File

@ -38,14 +38,14 @@ module buscachefsm #(parameter integer WordCountThreshold,
input logic HRESETn, input logic HRESETn,
// IEU interface // IEU interface
input logic [1:0] RW, input logic [1:0] BusRW,
input logic CPUBusy, input logic CPUBusy,
output logic BusCommitted, output logic BusCommitted,
output logic BusStall, output logic BusStall,
output logic CaptureEn, output logic CaptureEn,
// cache interface // cache interface
input logic [1:0] CacheRW, input logic [1:0] CacheBusRW,
output logic CacheBusAck, output logic CacheBusAck,
// lsu interface // lsu interface
@ -83,21 +83,21 @@ module buscachefsm #(parameter integer WordCountThreshold,
always_comb begin always_comb begin
case(CurrState) case(CurrState)
ADR_PHASE: if(HREADY & |RW) NextState = DATA_PHASE; ADR_PHASE: if(HREADY & |BusRW) NextState = DATA_PHASE;
else if (HREADY & CacheRW[0]) NextState = CACHE_EVICT; else if (HREADY & CacheBusRW[0]) NextState = CACHE_EVICT;
else if (HREADY & CacheRW[1]) NextState = CACHE_FETCH; else if (HREADY & CacheBusRW[1]) NextState = CACHE_FETCH;
else NextState = ADR_PHASE; else NextState = ADR_PHASE;
DATA_PHASE: if(HREADY) NextState = MEM3; DATA_PHASE: if(HREADY) NextState = MEM3;
else NextState = DATA_PHASE; else NextState = DATA_PHASE;
MEM3: if(CPUBusy) NextState = MEM3; MEM3: if(CPUBusy) NextState = MEM3;
else NextState = ADR_PHASE; else NextState = ADR_PHASE;
CACHE_FETCH: if(HREADY & FinalWordCount & CacheRW[0]) NextState = CACHE_EVICT; CACHE_FETCH: if(HREADY & FinalWordCount & CacheBusRW[0]) NextState = CACHE_EVICT;
else if(HREADY & FinalWordCount & CacheRW[1]) NextState = CACHE_FETCH; else if(HREADY & FinalWordCount & CacheBusRW[1]) NextState = CACHE_FETCH;
else if(HREADY & FinalWordCount & ~|CacheRW) NextState = ADR_PHASE; else if(HREADY & FinalWordCount & ~|CacheBusRW) NextState = ADR_PHASE;
else NextState = CACHE_FETCH; else NextState = CACHE_FETCH;
CACHE_EVICT: if(HREADY & FinalWordCount & CacheRW[0]) NextState = CACHE_EVICT; CACHE_EVICT: if(HREADY & FinalWordCount & CacheBusRW[0]) NextState = CACHE_EVICT;
else if(HREADY & FinalWordCount & CacheRW[1]) NextState = CACHE_FETCH; else if(HREADY & FinalWordCount & CacheBusRW[1]) NextState = CACHE_FETCH;
else if(HREADY & FinalWordCount & ~|CacheRW) NextState = ADR_PHASE; else if(HREADY & FinalWordCount & ~|CacheBusRW) NextState = ADR_PHASE;
else NextState = CACHE_EVICT; else NextState = CACHE_EVICT;
default: NextState = ADR_PHASE; default: NextState = ADR_PHASE;
endcase endcase
@ -122,30 +122,30 @@ module buscachefsm #(parameter integer WordCountThreshold,
assign FinalWordCount = WordCountDelayed == WordCountThreshold[LOGWPL-1:0]; assign FinalWordCount = WordCountDelayed == WordCountThreshold[LOGWPL-1:0];
assign WordCntEn = ((NextState == CACHE_EVICT | NextState == CACHE_FETCH) & HREADY) | assign WordCntEn = ((NextState == CACHE_EVICT | NextState == CACHE_FETCH) & HREADY) |
(NextState == ADR_PHASE & |CacheRW & HREADY); (NextState == ADR_PHASE & |CacheBusRW & HREADY);
assign WordCntReset = NextState == ADR_PHASE; assign WordCntReset = NextState == ADR_PHASE;
assign CaptureEn = (CurrState == DATA_PHASE & RW[1]) | (CurrState == CACHE_FETCH & HREADY); assign CaptureEn = (CurrState == DATA_PHASE & BusRW[1]) | (CurrState == CACHE_FETCH & HREADY);
assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_EVICT; assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_EVICT;
assign BusStall = (CurrState == ADR_PHASE & (|RW | |CacheRW)) | assign BusStall = (CurrState == ADR_PHASE & (|BusRW | |CacheBusRW)) |
//(CurrState == DATA_PHASE & ~RW[0]) | // replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem. //(CurrState == DATA_PHASE & ~BusRW[0]) | // replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem.
(CurrState == DATA_PHASE) | (CurrState == DATA_PHASE) |
(CurrState == CACHE_FETCH) | (CurrState == CACHE_FETCH) |
(CurrState == CACHE_EVICT); (CurrState == CACHE_EVICT);
assign BusCommitted = CurrState != ADR_PHASE; assign BusCommitted = CurrState != ADR_PHASE;
assign SelUncachedAdr = (CurrState == ADR_PHASE & |RW) | assign SelUncachedAdr = (CurrState == ADR_PHASE & |BusRW) |
(CurrState == DATA_PHASE) | (CurrState == DATA_PHASE) |
(CurrState == MEM3); (CurrState == MEM3);
// AHB bus interface // AHB bus interface
assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|RW | |CacheRW)) | assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW)) |
(CurrState == DATA_PHASE & ~HREADY) | (CurrState == DATA_PHASE & ~HREADY) |
(CacheAccess & ~|WordCount & |CacheRW) ? AHB_NONSEQ : (CacheAccess & ~|WordCount & |CacheBusRW) ? AHB_NONSEQ :
(CacheAccess & |WordCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; (CacheAccess & |WordCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
assign HWRITE = RW[0] | CacheRW[0]; assign HWRITE = BusRW[0] | CacheBusRW[0];
assign HBURST = `BURST_EN ? ((|CacheRW) ? LocalBurstType : 3'b0) : 3'b0; // this line is for burst. assign HBURST = `BURST_EN ? ((|CacheBusRW) ? LocalBurstType : 3'b0) : 3'b0; // this line is for burst.
always_comb begin always_comb begin
case(WordCountThreshold) case(WordCountThreshold)
@ -159,8 +159,8 @@ module buscachefsm #(parameter integer WordCountThreshold,
// communication to cache // communication to cache
assign CacheBusAck = (CacheAccess & HREADY & FinalWordCount); assign CacheBusAck = (CacheAccess & HREADY & FinalWordCount);
assign SelBusWord = (CurrState == ADR_PHASE & (RW[0] | CacheRW[0])) | assign SelBusWord = (CurrState == ADR_PHASE & (BusRW[0] | CacheBusRW[0])) |
(CurrState == DATA_PHASE & RW[0]) | (CurrState == DATA_PHASE & BusRW[0]) |
(CurrState == CACHE_EVICT) | (CurrState == CACHE_EVICT) |
(CurrState == CACHE_FETCH); (CurrState == CACHE_FETCH);

12
pipelined/src/ebu/busfsm.sv
View File

@ -36,7 +36,7 @@ module busfsm
input logic HRESETn, input logic HRESETn,
// IEU interface // IEU interface
input logic [1:0] RW, input logic [1:0] BusRW,
input logic CPUBusy, input logic CPUBusy,
output logic BusCommitted, output logic BusCommitted,
output logic BusStall, output logic BusStall,
@ -60,7 +60,7 @@ module busfsm
always_comb begin always_comb begin
case(CurrState) case(CurrState)
ADR_PHASE: if(HREADY & |RW) NextState = DATA_PHASE; ADR_PHASE: if(HREADY & |BusRW) NextState = DATA_PHASE;
else NextState = ADR_PHASE; else NextState = ADR_PHASE;
DATA_PHASE: if(HREADY) NextState = MEM3; DATA_PHASE: if(HREADY) NextState = MEM3;
else NextState = DATA_PHASE; else NextState = DATA_PHASE;
@ -70,15 +70,15 @@ module busfsm
endcase endcase
end end
assign BusStall = (CurrState == ADR_PHASE & |RW) | assign BusStall = (CurrState == ADR_PHASE & |BusRW) |
// (CurrState == DATA_PHASE & ~RW[0]); // possible optimization here. fails uart test, but i'm not sure the failure is valid. // (CurrState == DATA_PHASE & ~BusRW[0]); // possible optimization here. fails uart test, but i'm not sure the failure is valid.
(CurrState == DATA_PHASE); (CurrState == DATA_PHASE);
assign BusCommitted = CurrState != ADR_PHASE; assign BusCommitted = CurrState != ADR_PHASE;
assign HTRANS = (CurrState == ADR_PHASE & HREADY & |RW) | assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW) |
(CurrState == DATA_PHASE & ~HREADY) ? AHB_NONSEQ : AHB_IDLE; (CurrState == DATA_PHASE & ~HREADY) ? AHB_NONSEQ : AHB_IDLE;
assign HWRITE = RW[0]; assign HWRITE = BusRW[0];
assign CaptureEn = CurrState == DATA_PHASE; assign CaptureEn = CurrState == DATA_PHASE;
endmodule endmodule

27
pipelined/src/ifu/ifu.sv
View File

@ -92,7 +92,7 @@ module ifu (
logic CompressedF; logic CompressedF;
logic [31:0] InstrRawD, InstrRawF; logic [31:0] InstrRawD, InstrRawF;
logic [31:0] FinalInstrRawF; logic [31:0] FinalInstrRawF;
logic [1:0] RWF; logic [1:0] IFURWF;
logic [31:0] InstrE; logic [31:0] InstrE;
logic [`XLEN-1:0] PCD; logic [`XLEN-1:0] PCD;
@ -186,11 +186,11 @@ module ifu (
// The IROM uses untranslated addresses, so it is not compatible with virtual memory. // The IROM uses untranslated addresses, so it is not compatible with virtual memory.
if (`IROM_SUPPORTED) begin : irom if (`IROM_SUPPORTED) begin : irom
assign RWF = 2'b10; assign IFURWF = 2'b10;
irom irom(.clk, .reset, .ce(~CPUBusy), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(FinalInstrRawF)); irom irom(.clk, .reset, .ce(~CPUBusy), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(FinalInstrRawF));
end else begin end else begin
assign RWF = 2'b10; assign IFURWF = 2'b10;
end end
if (`BUS) begin : bus if (`BUS) begin : bus
localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1; localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
@ -201,24 +201,23 @@ module ifu (
logic [`PA_BITS-1:0] ICacheBusAdr; logic [`PA_BITS-1:0] ICacheBusAdr;
logic ICacheBusAck; logic ICacheBusAck;
logic SelUncachedAdr; logic SelUncachedAdr;
logic [1:0] CacheRW, RW; logic [1:0] CacheBusRW, BusRW;
assign CacheRW = {ICacheFetchLine, 1'b0} & ~{ITLBMissF, ITLBMissF}; assign BusRW = IFURWF & ~{ITLBMissF, ITLBMissF} & ~{CacheableF, CacheableF};
assign RW = RWF & ~{ITLBMissF, ITLBMissF} & ~{CacheableF, CacheableF};
cache #(.LINELEN(`ICACHE_LINELENINBITS), cache #(.LINELEN(`ICACHE_LINELENINBITS),
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
.NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .TrapM, icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .TrapM,
.FetchBuffer, .CacheBusAck(ICacheBusAck), .FetchBuffer, .CacheBusAck(ICacheBusAck),
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
.CacheFetchLine(ICacheFetchLine), .CacheBusRW,
.CacheWriteLine(), .ReadDataWord(FinalInstrRawF), .ReadDataWord(FinalInstrRawF),
.Cacheable(CacheableF), .Cacheable(CacheableF),
.SelReplay('0), .SelReplay('0),
.CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
.ByteMask('0), .WordCount('0), .SelBusWord('0), .ByteMask('0), .WordCount('0), .SelBusWord('0),
.FinalWriteData('0), .FinalWriteData('0),
.RW(RWF), .RW(IFURWF),
.Atomic('0), .FlushCache('0), .Atomic('0), .FlushCache('0),
.NextAdr(PCNextFSpill[11:0]), .NextAdr(PCNextFSpill[11:0]),
.PAdr(PCPF), .PAdr(PCPF),
@ -226,12 +225,12 @@ module ifu (
ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE) ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE)
ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
.HRDATA, .HRDATA,
.CacheRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS),
.Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr), .Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
.WordCount(), .SelUncachedAdr, .SelBusWord(), .WordCount(), .SelUncachedAdr, .SelBusWord(),
.CacheBusAck(ICacheBusAck), .CacheBusAck(ICacheBusAck),
.FetchBuffer, .PAdr(PCPF), .FetchBuffer, .PAdr(PCPF),
.RW, .CPUBusy, .BusRW, .CPUBusy,
.BusStall, .BusCommitted()); .BusStall, .BusCommitted());
mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(FetchBuffer[32-1:0]), mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(FetchBuffer[32-1:0]),
@ -239,13 +238,13 @@ module ifu (
end else begin : passthrough end else begin : passthrough
assign IFUHADDR = PCPF; assign IFUHADDR = PCPF;
logic CaptureEn; logic CaptureEn;
logic [1:0] RW; logic [1:0] BusRW;
assign RW = RWF & ~{ITLBMissF, ITLBMissF}; assign BusRW = IFURWF & ~{ITLBMissF, ITLBMissF};
assign IFUHSIZE = 3'b010; assign IFUHSIZE = 3'b010;
ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY), ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY),
.HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(), .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
.HWSTRB(), .RW, .ByteMask(), .WriteData('0), .HWSTRB(), .BusRW, .ByteMask(), .WriteData('0),
.CPUBusy, .BusStall, .BusCommitted(), .ReadDataWord(InstrRawF[31:0])); .CPUBusy, .BusStall, .BusCommitted(), .ReadDataWord(InstrRawF[31:0]));
assign IFUHBURST = 3'b0; assign IFUHBURST = 3'b0;

19
pipelined/src/lsu/lsu.sv
View File

@ -229,10 +229,9 @@ module lsu (
logic SelBusWord; logic SelBusWord;
logic [`XLEN-1:0] PreHWDATA; //*** change name logic [`XLEN-1:0] PreHWDATA; //*** change name
logic [`XLEN/8-1:0] ByteMaskMDelay; logic [`XLEN/8-1:0] ByteMaskMDelay;
logic [1:0] CacheRW, UnCacheRW; logic [1:0] CacheBusRW, BusRW;
assign CacheRW = {DCacheFetchLine, DCacheWriteLine} & ~{IgnoreRequest, IgnoreRequest}; assign BusRW = LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableM, CacheableM};
assign UnCacheRW = LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableM, CacheableM};
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache(
@ -243,16 +242,16 @@ module lsu (
.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
.IgnoreRequestTLB, .TrapM, .CacheCommitted(DCacheCommittedM), .IgnoreRequestTLB, .TrapM, .CacheCommitted(DCacheCommittedM),
.CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM), .CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM),
.FetchBuffer, .CacheFetchLine(DCacheFetchLine), .FetchBuffer, .CacheBusRW,
.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) ahbcacheinterface( ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) ahbcacheinterface(
.HCLK(clk), .HRESETn(~reset), .HCLK(clk), .HRESETn(~reset),
.HRDATA, .HRDATA,
.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
.WordCount, .SelBusWord, .WordCount, .SelBusWord,
.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheRW, .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW,
.CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM),
.SelUncachedAdr, .RW(UnCacheRW), .CPUBusy, .SelUncachedAdr, .BusRW, .CPUBusy,
.BusStall, .BusCommitted(BusCommittedM)); .BusStall, .BusCommitted(BusCommittedM));
mux2 #(`LLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0] }), mux2 #(`LLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0] }),
@ -271,15 +270,15 @@ module lsu (
end else begin : passthrough // just needs a register to hold the value from the bus end else begin : passthrough // just needs a register to hold the value from the bus
logic CaptureEn; logic CaptureEn;
logic [1:0] RW; logic [1:0] BusRW;
assign RW = LSURWM & ~{IgnoreRequest, IgnoreRequest}; assign BusRW = LSURWM & ~{IgnoreRequest, IgnoreRequest};
assign LSUHADDR = PAdrM; assign LSUHADDR = PAdrM;
assign LSUHSIZE = LSUFunct3M; assign LSUHSIZE = LSUFunct3M;
ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(LSUHREADY), ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(LSUHREADY),
.HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
.HWSTRB(LSUHWSTRB), .RW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM), .HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM),
.CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .ReadDataWord(ReadDataWordM)); .CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .ReadDataWord(ReadDataWordM));
assign ReadDataWordMuxM = ReadDataWordM; // from byte swapping assign ReadDataWordMuxM = ReadDataWordM; // from byte swapping