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Fixed syntax bugs. inline functions are now static and in the spi.h header.

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This commit is contained in:
Jacob Pease 2024-07-23 17:00:32 -05:00
parent 5f0addd69a
commit dcb2edf888
6 changed files with 70 additions and 42 deletions
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10
fpga/zsbl/boot.c
View File

@ -46,9 +46,9 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) {
crc = crc7(crc, sector & 0xff); crc = crc7(crc, sector & 0xff);
crc = crc | 1; crc = crc | 1;
if (sd_cmd(18, sector &, crc) != 0x00) { if (sd_cmd(18, sector & 0xffffffff, crc) != 0x00) {
print_uart("disk_read: CMD18 failed. r = "); print_uart("disk_read: CMD18 failed. r = ");
print_byte(r & 0xff); print_uart_byte(r & 0xff);
return -1; return -1;
} }
@ -60,7 +60,7 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) {
r = spi_readbyte(); r = spi_readbyte();
if (r != SD_DATA_TOKEN) { if (r != SD_DATA_TOKEN) {
print_uart("Didn't receive data token first thing. Shoot: "); print_uart("Didn't receive data token first thing. Shoot: ");
print_byte(r & 0xff); print_uart_byte(r & 0xff);
return -1; return -1;
} }
@ -76,7 +76,7 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) {
if (crc != crc_exp) { if (crc != crc_exp) {
print_uart("Stinking CRC16 didn't match on block "); print_uart("Stinking CRC16 didn't match on block ");
print_int(i); print_uart_int(i);
print_uart("\r\n"); print_uart("\r\n");
return -1; return -1;
} }
@ -104,5 +104,5 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) {
// Intialize the SD card // Intialize the SD card
init_sd(); init_sd();
ret = gpt_load_partitions(card_type); ret = gpt_load_partitions();
} }

2
fpga/zsbl/boot.h
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@ -30,7 +30,7 @@ typedef QWORD LBA_t;
" \\___/\\___/ /___/ \\___\\|_______||_______| |___|\n\n" " \\___/\\___/ /___/ \\___\\|_______||_______| |___|\n\n"
// Export disk_read // Export disk_read
int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type); int disk_read(BYTE * buf, LBA_t sector, UINT count);
#endif // WALLYBOOT #endif // WALLYBOOT

2
fpga/zsbl/sd.c
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@ -129,7 +129,7 @@ uint64_t sd_read64(uint16_t * crc) {
// This first initializes the SPI peripheral then initializes the SD // This first initializes the SPI peripheral then initializes the SD
// card itself. We use the uart to display anything that goes wrong. // card itself. We use the uart to display anything that goes wrong.
void init_sd(){ void init_sd(){
init_spi(); spi_init();
uint64_t r; uint64_t r;

46
fpga/zsbl/spi.c
View File

@ -30,33 +30,29 @@
#include "spi.h" #include "spi.h"
// Write to a register // Write to a register
inline void write_reg(uintptr_t addr, uint32_t value) { /* inline void write_reg(uintptr_t addr, uint32_t value) { */
volatile uint32_t * loc = (volatile uint32_t *) addr; /* volatile uint32_t * loc = (volatile uint32_t *) addr; */
*loc = value; /* *loc = value; */
} /* } */
// Read a register /* // Read a register */
inline void read_reg(uintptr_t addr) { /* inline uint32_t read_reg(uintptr_t addr) { */
return *(volatile uint32_t *) addr; /* return *(volatile uint32_t *) addr; */
} /* } */
// Queues a single byte in the transfer fifo /* // Queues a single byte in the transfer fifo */
inline void spi_sendbyte(uint8_t byte) { /* inline void spi_sendbyte(uint8_t byte) { */
// Write byte to transfer fifo /* // Write byte to transfer fifo */
write_reg(SPI_TXDATA, byte); /* write_reg(SPI_TXDATA, byte); */
} /* } */
inline uint8_t spi_readbyte() { /* inline void waittx() { */
return read_reg(SPI_RXDATA); /* while(!(read_reg(SPI_IP) & 1)) {} */
} /* } */
inline void waittx() { /* inline void waitrx() { */
while(!(read_reg(SPI_IP) & 1)) {} /* while(read_reg(SPI_IP) & 2) {} */
} /* } */
inline void waitrx() {
while(read_reg(SPI_IP) & 2)) {}
}
uint8_t spi_txrx(uint8_t byte) { uint8_t spi_txrx(uint8_t byte) {
spi_sendbyte(0xFF); spi_sendbyte(0xFF);
@ -64,6 +60,10 @@ uint8_t spi_txrx(uint8_t byte) {
return spi_readbyte(); return spi_readbyte();
} }
/* inline uint8_t spi_readbyte() { */
/* return read_reg(SPI_RXDATA); */
/* } */
uint64_t spi_read64() { uint64_t spi_read64() {
uint64_t r; uint64_t r;
uint8_t rbyte; uint8_t rbyte;

48
fpga/zsbl/spi.h
View File

@ -28,15 +28,15 @@
#define SPI_IP SPI_BASE + 0x74 /* Interrupt Pendings Register */ #define SPI_IP SPI_BASE + 0x74 /* Interrupt Pendings Register */
/* delay0 bits */ /* delay0 bits */
#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x)) #define SIFIVE_SPI_DELAY0_CSSCK(x) ((uint32_t)(x))
#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU #define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16) #define SIFIVE_SPI_DELAY0_SCKCS(x) ((uint32_t)(x) << 16)
#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16) #define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
/* delay1 bits */ /* delay1 bits */
#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) #define SIFIVE_SPI_DELAY1_INTERCS(x) ((uint32_t)(x))
#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU #define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16) #define SIFIVE_SPI_DELAY1_INTERXFR(x) ((uint32_t)(x) << 16)
#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16) #define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
/* csmode bits */ /* csmode bits */
@ -48,14 +48,42 @@
#define WAITTX while(!(read_reg(SPI_IP) & 1) {} #define WAITTX while(!(read_reg(SPI_IP) & 1) {}
#define WAITRX while(read_reg(SPI_IP) & 2) {} #define WAITRX while(read_reg(SPI_IP) & 2) {}
inline void write_reg(uintptr_t addr, uint32_t value); // inline void write_reg(uintptr_t addr, uint32_t value);
inline uint32_t read_reg(uintptr_t addr); //inline uint32_t read_reg(uintptr_t addr);
inline void spi_sendbyte(uint8_t byte); //inline void spi_sendbyte(uint8_t byte);
inline void waittx(); //inline void waittx();
inline void waitrx(); //inline void waitrx();
uint8_t spi_txrx(uint8_t byte); uint8_t spi_txrx(uint8_t byte);
inline uint8_t spi_readbyte(); //inline uint8_t spi_readbyte();
uint64_t spi_read64(); uint64_t spi_read64();
void spi_init(); void spi_init();
static inline void write_reg(uintptr_t addr, uint32_t value) {
volatile uint32_t * loc = (volatile uint32_t *) addr;
*loc = value;
}
// Read a register
static inline uint32_t read_reg(uintptr_t addr) {
return *(volatile uint32_t *) addr;
}
// Queues a single byte in the transfer fifo
static inline void spi_sendbyte(uint8_t byte) {
// Write byte to transfer fifo
write_reg(SPI_TXDATA, byte);
}
static inline void waittx() {
while(!(read_reg(SPI_IP) & 1)) {}
}
static inline void waitrx() {
while(read_reg(SPI_IP) & 2) {}
}
static inline uint8_t spi_readbyte() {
return read_reg(SPI_RXDATA);
}
#endif #endif

4
fpga/zsbl/uart.c
View File

@ -14,12 +14,12 @@ uint8_t read_reg_u8(uintptr_t addr)
int is_transmit_empty() int is_transmit_empty()
{ {
return read_reg_u8(UART_LINE_STATUS) & 0x20; return read_reg_u8(UART_LSR) & 0x20;
} }
int is_receive_empty() int is_receive_empty()
{ {
return !(read_reg_u8(UART_LINE_STATUS) & 0x1); return !(read_reg_u8(UART_LSR) & 0x1);
} }
void write_serial(char a) void write_serial(char a)