Hardware reductions in the lsu.

wally-pipelined/src/lsu/lsu.sv

@@ -101,6 +101,7 @@ module lsu
   logic 					   DTLBWriteM;
   logic 					   HPTWStall;  
   logic [`PA_BITS-1:0] 		   TranslationPAdr;
+  //logic [`PA_BITS-1:0] 		   TranslationPAdrM;
   logic 					   HPTWRead;
   logic [1:0] 				   MemRWMtoDCache;
   logic [1:0] 				   MemRWMtoLRSC;
@@ -116,6 +117,8 @@ module lsu
   logic 					   CacheableM;
   logic 					   CacheableMtoDCache;
   logic 					   SelPTW;
+  logic [2:0] 				   HPTWSize;
+
 
   logic 					   CommittedMfromDCache;
   logic 					   PendingInterruptMtoDCache;
@@ -254,50 +257,32 @@ module lsu
 
   // *** add generate to conditionally create hptw, lsuArb, and mmu
   // based on `MEM_VIRTMEM
-  hptw hptw(.clk(clk),
+  hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM,
-			.reset(reset),
-			.SATP_REGW(SATP_REGW),
-			.PCF(PCF),
-			.IEUAdrM(IEUAdrM),
 			.ITLBMissF(ITLBMissF & ~PendingInterruptM),
 			.DTLBMissM(DTLBMissM & ~PendingInterruptM),
-			.MemRWM(MemRWM),
+			.MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
-			.PTE(PTE),
-			.PageType,
-			.ITLBWriteF(ITLBWriteF),
-			.DTLBWriteM(DTLBWriteM),
 			.HPTWReadPTE(ReadDataM),
-			.DCacheStall(DCacheStall),
+			.DCacheStall, .TranslationPAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM,
-			.TranslationPAdr,			  
-			.HPTWRead(HPTWRead),
-			.AnyCPUReqM,
 			.WalkerInstrPageFaultF(WalkerInstrPageFaultRaw),
-			.WalkerLoadPageFaultM(WalkerLoadPageFaultM),  
+			.WalkerLoadPageFaultM, .WalkerStorePageFaultM);
-			.WalkerStorePageFaultM(WalkerStorePageFaultM));
 
   assign LSUStall = DCacheStall | InterlockStall;
   
   assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
 
   // arbiter between IEU and hptw
-  logic [2:0] PTWSize;
-  logic [`PA_BITS-1:0]  TranslationPAdrM;
-  logic [`XLEN+1:0]  IEUAdrMExt;
   
   // multiplex the outputs to LSU
   assign MemRWMtoLRSC = SelPTW ? {HPTWRead, 1'b0} : MemRWM;
   
-  generate
+  mux2 #(3) sizemux(Funct3M, HPTWSize, SelPTW, Funct3MtoDCache);
-    assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw
-  endgenerate
-  mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache);
 
   // this is for the d cache SRAM.
-  flop #(`PA_BITS) TranslationPAdrMReg(clk, TranslationPAdr, TranslationPAdrM);   // delay TranslationPAdrM by a cycle
+  // turns out because we cannot pipeline hptw requests we don't need this register
+  //flop #(`PA_BITS) TranslationPAdrMReg(clk, TranslationPAdr, TranslationPAdrM);   // delay TranslationPAdrM by a cycle
 
   assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
-  assign IEUAdrMExt = {2'b00, IEUAdrM};
+  assign MemPAdrNoTranslate = SelPTW ? TranslationPAdr : {2'b00, IEUAdrM}[`PA_BITS-1:0]; 
-  assign MemPAdrNoTranslate = SelPTW ? TranslationPAdrM : IEUAdrMExt[`PA_BITS-1:0]; 
   assign MemAdrE = SelPTW ? TranslationPAdr[11:0] : IEUAdrE[11:0];  
   assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
   // always block interrupts when using the hardware page table walker.

wally-pipelined/src/mmu/hptw.sv

@@ -32,20 +32,21 @@
 
 module hptw
   (
-   input logic 		       clk, reset,
+   input logic 				   clk, reset,
-   input logic [`XLEN-1:0]     SATP_REGW, // includes SATP.MODE to determine number of levels in page table
+   input logic [`XLEN-1:0] 	   SATP_REGW, // includes SATP.MODE to determine number of levels in page table
-   input logic [`XLEN-1:0]     PCF, IEUAdrM, // addresses to translate
+   input logic [`XLEN-1:0] 	   PCF, IEUAdrM, // addresses to translate
-   input logic 		       ITLBMissF, DTLBMissM, // TLB Miss
+   input logic 				   ITLBMissF, DTLBMissM, // TLB Miss
-   input logic [1:0] 	       MemRWM, // 10 = read, 01 = write
+   input logic [1:0] 		   MemRWM, // 10 = read, 01 = write
-   input logic [`XLEN-1:0]     HPTWReadPTE, // page table entry from LSU
+   input logic [`XLEN-1:0] 	   HPTWReadPTE, // page table entry from LSU
-   input logic 		       DCacheStall, // stall from LSU
+   input logic 				   DCacheStall, // stall from LSU
-   input logic 		       AnyCPUReqM,
+   input logic 				   AnyCPUReqM,
    output logic [`XLEN-1:0]    PTE, // page table entry to TLBs
-   output logic [1:0] 	       PageType, // page type to TLBs
+   output logic [1:0] 		   PageType, // page type to TLBs
-   output logic 	       ITLBWriteF, DTLBWriteM, // write TLB with new entry
+   output logic 			   ITLBWriteF, DTLBWriteM, // write TLB with new entry
    output logic [`PA_BITS-1:0] TranslationPAdr,
-   output logic 	       HPTWRead, // HPTW requesting to read memory
+   output logic 			   HPTWRead, // HPTW requesting to read memory
-   output logic 	       WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
+   output logic [2:0] 		   HPTWSize, // 32 or 64 bit access.
+   output logic 			   WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
 );
 
       typedef enum  {L0_ADR, L0_RD, 
@@ -123,7 +124,8 @@ module hptw
 		logic [`PPN_BITS-1:0] PPN;
 		assign VPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? TranslationVAdr[31:22] : TranslationVAdr[21:12]; // select VPN field based on HPTW state
 		assign PPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? BasePageTablePPN : CurrentPPN; 
-		assign TranslationPAdr = {PPN, VPN, 2'b00}; 
+		assign TranslationPAdr = {PPN, VPN, 2'b00};
+		assign HPTWSize = 3'b010;
 	  end else begin // RV64
 		logic [8:0] VPN;
 		logic [`PPN_BITS-1:0] PPN;
@@ -136,7 +138,8 @@ module hptw
 			endcase
 		assign PPN = ((WalkerState == L3_ADR) | (WalkerState == L3_RD) | 
 		              (SvMode != `SV48 & ((WalkerState == L2_ADR) | (WalkerState == L2_RD)))) ? BasePageTablePPN : CurrentPPN;
-		assign TranslationPAdr = {PPN, VPN, 3'b000}; 
+		assign TranslationPAdr = {PPN, VPN, 3'b000};
+		assign HPTWSize = 3'b011;
 	  end
 
 	  // Initial state and misalignment for RV32/64
@@ -208,7 +211,8 @@ module hptw
     end else begin // No Virtual memory supported; tie HPTW outputs to 0
       assign HPTWRead = 0;
       assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0;
-      assign TranslationPAdr = 0; 
+      assign TranslationPAdr = 0;
+	  assign HPTWSize = 3'b000;
     end
   endgenerate
 endmodule