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Program clean up

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This commit is contained in:
Harshini Srinath 2023-06-10 18:13:40 -07:00 committed by GitHub
parent aafa5d6ec3
commit dc0b95c4ac
1 changed files with 11 additions and 11 deletions
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src/ebu/ahbcacheinterface.sv
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@ -45,14 +45,14 @@ module ahbcacheinterface #(
output logic [2:0] HSIZE, // AHB transaction width output logic [2:0] HSIZE, // AHB transaction width
output logic [2:0] HBURST, // AHB burst length output logic [2:0] HBURST, // AHB burst length
// bus interface buses // bus interface buses
input logic [AHBW-1:0] HRDATA, // AHB read data input logic [AHBW-1:0] HRDATA, // AHB read data
output logic [PA_BITS-1:0] HADDR, // AHB address output logic [PA_BITS-1:0] HADDR, // AHB address
output logic [AHBW-1:0] HWDATA, // AHB write data output logic [AHBW-1:0] HWDATA, // AHB write data
output logic [AHBW/8-1:0] HWSTRB, // AHB byte mask output logic [AHBW/8-1:0] HWSTRB, // AHB byte mask
// cache interface // cache interface
input logic [PA_BITS-1:0] CacheBusAdr, // Address of cache line input logic [PA_BITS-1:0] CacheBusAdr, // Address of cache line
input logic [LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback input logic [LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback
input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$ input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$
input logic Cacheable, // Memory operation is cachable input logic Cacheable, // Memory operation is cachable
input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch
@ -62,8 +62,8 @@ module ahbcacheinterface #(
output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
// uncached interface // uncached interface
input logic [PA_BITS-1:0] PAdr, // Physical address of uncached memory operation input logic [PA_BITS-1:0] PAdr, // Physical address of uncached memory operation
input logic [LLEN-1:0] WriteDataM, // IEU write data for uncached store input logic [LLEN-1:0] WriteDataM, // IEU write data for uncached store
input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write
input logic [2:0] Funct3, // Size of uncached memory operation input logic [2:0] Funct3, // Size of uncached memory operation
@ -75,11 +75,11 @@ module ahbcacheinterface #(
localparam BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index localparam BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index
logic [PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation logic [PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation
logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage
logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA
logic [AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s logic [AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s
logic [AHBW-1:0] PreHWDATA; // AHB Address phase write data logic [AHBW-1:0] PreHWDATA; // AHB Address phase write data
genvar index; genvar index;