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Removed unused flushf.

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This commit is contained in:
Ross Thompson 2022-12-11 16:28:11 -06:00
parent ad7dd56180
commit dbc3dac03d
5 changed files with 10 additions and 11 deletions
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3
pipelined/src/hazard/hazard.sv
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@ -41,7 +41,7 @@ module hazard(
(* mark_debug = "true" *) input logic wfiM, IntPendingM, (* mark_debug = "true" *) input logic wfiM, IntPendingM,
// Stall & flush outputs // Stall & flush outputs
(* mark_debug = "true" *) output logic StallF, StallD, StallE, StallM, StallW, (* mark_debug = "true" *) output logic StallF, StallD, StallE, StallM, StallW,
(* mark_debug = "true" *) output logic FlushF, FlushD, FlushE, FlushM, FlushW (* mark_debug = "true" *) output logic FlushD, FlushE, FlushM, FlushW
); );
logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause; logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
@ -89,7 +89,6 @@ module hazard(
assign FirstUnstalledW = ~StallW & StallM; assign FirstUnstalledW = ~StallW & StallM;
// Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush // Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
assign #1 FlushF = BPPredWrongE;
assign #1 FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE; assign #1 FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE;
assign #1 FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE; // *** why is BPPredWrongE here, but not needed in simple processor assign #1 FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE; // *** why is BPPredWrongE here, but not needed in simple processor
assign #1 FlushM = FirstUnstalledM | TrapM | RetM; assign #1 FlushM = FirstUnstalledM | TrapM | RetM;

4
pipelined/src/ifu/bpred.sv
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@ -36,7 +36,7 @@
module bpred module bpred
(input logic clk, reset, (input logic clk, reset,
input logic StallF, StallD, StallE, StallM, input logic StallF, StallD, StallE, StallM,
input logic FlushF, FlushD, FlushE, FlushM, input logic FlushD, FlushE, FlushM,
// Fetch stage // Fetch stage
// the prediction // the prediction
input logic [31:0] InstrD, input logic [31:0] InstrD,
@ -103,7 +103,7 @@ module bpred
else if (`BPTYPE == "BPLOCALPAg") begin:Predictor else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
localHistoryPredictor DirPredictor(.clk, localHistoryPredictor DirPredictor(.clk,
.reset, .StallF, .StallE, .FlushF, .reset, .StallF, .StallE,
.LookUpPC(PCNextF), .LookUpPC(PCNextF),
.Prediction(BPPredF), .Prediction(BPPredF),
// update // update

4
pipelined/src/ifu/ifu.sv
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@ -34,7 +34,7 @@
module ifu ( module ifu (
input logic clk, reset, input logic clk, reset,
input logic StallF, StallD, StallE, StallM, input logic StallF, StallD, StallE, StallM,
input logic FlushF, FlushD, FlushE, FlushM, FlushW, input logic FlushD, FlushE, FlushM, FlushW,
// Bus interface // Bus interface
(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, (* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA,
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR, (* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR,
@ -309,7 +309,7 @@ module ifu (
logic [`XLEN-1:0] BPPredPCF; logic [`XLEN-1:0] BPPredPCF;
bpred bpred(.clk, .reset, bpred bpred(.clk, .reset,
.StallF, .StallD, .StallE, .StallM, .StallF, .StallD, .StallE, .StallM,
.FlushF, .FlushD, .FlushE, .FlushM, .FlushD, .FlushE, .FlushM,
.InstrD, .PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE, .InstrD, .PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE,
.PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM, .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM); .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM);

4
pipelined/src/ifu/localHistoryPredictor.sv
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@ -38,7 +38,7 @@ module localHistoryPredictor
) )
(input logic clk, (input logic clk,
input logic reset, input logic reset,
input logic StallF, StallE, FlushF, input logic StallF, StallE,
input logic [`XLEN-1:0] LookUpPC, input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] Prediction, output logic [1:0] Prediction,
// update // update
@ -116,7 +116,7 @@ module localHistoryPredictor
flopenrc #(k) LHRFReg(.clk(clk), flopenrc #(k) LHRFReg(.clk(clk),
.reset(reset), .reset(reset),
.en(~StallF), .en(~StallF),
.clear(FlushF), .clear(1'b0),
.d(ForwardLHRNext), .d(ForwardLHRNext),
.q(LHRF)); .q(LHRF));
/* /*

6
pipelined/src/wally/wallypipelinedcore.sv
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@ -53,7 +53,7 @@ module wallypipelinedcore (
// logic [1:0] ForwardAE, ForwardBE; // logic [1:0] ForwardAE, ForwardBE;
logic StallF, StallD, StallE, StallM, StallW; logic StallF, StallD, StallE, StallM, StallW;
logic FlushF, FlushD, FlushE, FlushM, FlushW; logic FlushD, FlushE, FlushM, FlushW;
logic RetM; logic RetM;
(* mark_debug = "true" *) logic TrapM; (* mark_debug = "true" *) logic TrapM;
@ -170,7 +170,7 @@ module wallypipelinedcore (
ifu ifu( ifu ifu(
.clk, .reset, .clk, .reset,
.StallF, .StallD, .StallE, .StallM, .StallF, .StallD, .StallE, .StallM,
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW, .FlushD, .FlushE, .FlushM, .FlushW,
// Fetch // Fetch
.HRDATA, .PCF, .IFUHADDR, .HRDATA, .PCF, .IFUHADDR,
.IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE,
@ -325,7 +325,7 @@ module wallypipelinedcore (
.wfiM, .IntPendingM, .wfiM, .IntPendingM,
// Stall & flush outputs // Stall & flush outputs
.StallF, .StallD, .StallE, .StallM, .StallW, .StallF, .StallD, .StallE, .StallM, .StallW,
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW .FlushD, .FlushE, .FlushM, .FlushW
); // global stall and flush control ); // global stall and flush control
if (`ZICSR_SUPPORTED) begin:priv if (`ZICSR_SUPPORTED) begin:priv