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Added instructions for rv64i_m/D

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davidharrishmc 2021-10-30 07:34:53 -07:00 committed by GitHub
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README.md
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@ -16,6 +16,8 @@ git clone https://github.com/riscv-software-src/riscv-isa-sim
cd riscv-isa-sim
cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv32i_m/F
<edit arch_test_target/spike/device/rv32i_m/F/Makefile.include line 35 and change --isa=rv32i to --isa=rv32if>
cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv64i_m/D
<edit arch_test_target/spike/device/rv64i_m/D/Makefile.include line 35 and change --isa=rv64i to --isa=rv64id>
mkdir build
cd build
set RISCV=/cad/riscv/gcc/bin (or whatever your path is)