Add mtvec and stvec tests to testbench

wally-pipelined/testbench/testbench-imperas.sv

@@ -354,6 +354,8 @@ module testbench();
     "rv64p/WALLY-SEPC", "4000",
     "rv64p/WALLY-MTVAL", "6000",
     "rv64p/WALLY-STVAL", "4000",
+    "rv64p/WALLY-MTVEC", "2000",
+    "rv64p/WALLY-STVEC", "2000",
     "rv64p/WALLY-MARCHID", "4000",
     "rv64p/WALLY-MIMPID", "4000",
     "rv64p/WALLY-MHARTID", "4000",
@@ -371,6 +373,8 @@ module testbench();
     // "rv32p/WALLY-MIMPID", "4000",
     // "rv32p/WALLY-MHARTID", "4000",
     // "rv32p/WALLY-MVENDORID", "4000"
+    // "rv32p/WALLY-MTVEC", "2000",
+    // "rv32p/WALLY-STVEC", "2000"
   };
 
   string tests64periph[] = '{

wally-pipelined/testgen/privileged/testgen-TVAL.py

@@ -190,7 +190,9 @@ for xlen in xlens:
       #     This is the address we write results to
       # x6: Starting address we should write expected results to
       # ...
-      # x1 - x5 can be freely written  
+      # x4 & x5 can be freely written
+      # x3 — DO NOT WRITE ANY NON-ZERO VALUE TO THIS — test exits on ecall if x3 = 1 (x3 is gp)
+      # x1 & x2 can be freely written 
 
 
 

wally-pipelined/testgen/privileged/testgen-TVEC.py

@@ -51,52 +51,39 @@ def writeVectors(storecmd, returningInstruction):
 
 
   # Illegal Instruction 
-  writeTest(storecmd, f, r, f"""
-    .fill 1, 4, 0
-  """, False, 0)
-
-  # Breakpoint
-  if returningInstruction != "ebreak":
-    writeTest(storecmd, f, r, f"""
-      ebreak
-    """, False, 0)
-
-  # Load Address Misaligned 
-  writeTest(storecmd, f, r, f"""
-    lw x0, 11(x0)
-  """, False, 0)
-
-  # Load Access fault: False, 5
-
-  # Store/AMO address misaligned
-  writeTest(storecmd, f, r, f"""
-    sw x0, 11(x0)
-  """, False, 0)
-
-  # Environment call from u-mode: only for when only M and U mode enabled?
   # writeTest(storecmd, f, r, f"""
-  #   ecall
+  #   .fill 1, 4, 0
-  # """, False, 8, "u")
+  # """, False, 0)
+
+  # # Breakpoint
+  # if returningInstruction != "ebreak":
+  #   writeTest(storecmd, f, r, f"""
+  #     ebreak
+  #   """, False, 0)
+
+  # # Load Address Misaligned 
+  # writeTest(storecmd, f, r, f"""
+  #   lw x0, 11(x0)
+  # """, False, 0)
+
+  # # Load Access fault: False, 5
+
+  # # Store/AMO address misaligned
+  # writeTest(storecmd, f, r, f"""
+  #   sw x0, 11(x0)
+  # """, False, 0)
+
+  # # Environment call from u-mode: only for when only M and U mode enabled?
+  # # writeTest(storecmd, f, r, f"""
+  # #   ecall
+  # # """, False, 8, "u")
   if returningInstruction != "ecall":
-    if fromMode == "u":
-      writeTest(storecmd, f, r, f"""
-        ecall
-      """, False, 0)
-
-    # Environment call from s-mode
-    if fromMode == "s":
-      writeTest(storecmd, f, r, f"""
-        ecall
-      """, False, 0)
-
-    # Environment call from m-mode
-    if fromMode == "m":
     writeTest(storecmd, f, r, f"""
       ecall
     """, False, 0)
 
 
-  if fromMode == "m":
+  if fromMode == "m" and testMode == "m":
     expectedCode = 7 if fromMode == "m" else 5
     clintAddr = "0x2004000"
 
@@ -105,9 +92,9 @@ def writeVectors(storecmd, returningInstruction):
       csrrs x0, {fromMode}status, x1
 
       la x18, {clintAddr}
-      lw x11, 0(x18)
+      # lw x11, 0(x18)
-      li x1, 0x3fffffffffffffff
+      # li x1, 0x3fffffffffffffff
-      {storecmd} x1, 0(x18)
+      # {storecmd} x1, 0(x18)
 
       li x1, 0x80
       csrrs x0, {fromMode}ie, x1
@@ -132,7 +119,7 @@ def writeVectors(storecmd, returningInstruction):
   
 
 def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
-  global testnum, storeAddressOffset
+  global testnum, storeAddressOffset, xlen
 
   expected = code
 
@@ -156,19 +143,27 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
     {test}
   """
 
-  lines += f"""
+
+  if not areVectoredTrapsSupported or not vectoredInterrupts:
+    expected = 0
+
+  writeGeneralTest(storecmd, f, r, lines, expected)
+
+def writeGeneralTest(storecmd, f, r, test, expected):
+  global testnum, storeAddressOffset, xlen
+
+  lines = f"""
+    {test}
     {storecmd} x25, {testnum * wordsize}(x6)
   """
 
-  if not areVectoredTrapsSupported:
-    expected = 0
-
   f.write(lines)
   if (xlen == 32):
     line = formatrefstr.format(expected)+"\n"
   else:
     line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
   r.write(line)
+
   testnum = testnum+1
 
 ##################################
@@ -177,7 +172,7 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
 
 author = "dottolia@hmc.edu"
 xlens = [32, 64]
-testCount = 16;
+testCount = 4;
 
 # setup
 # Change this seed to a different constant value for every test
@@ -219,6 +214,25 @@ for xlen in xlens:
     for line in h:  
       f.write(line)
 
+    # Ensure MODE of *tvec (last 2 bits) is either 00 or 01
+    f.write(f"""
+      csrr x19, {testMode}tvec
+    """)
+
+    for i in range(0, 16):
+      i = i;
+      trySet = i | 0b10;
+      expected = trySet & 0xFFFF_FFFFD;
+      writeGeneralTest(storecmd, f, r, f"""
+        li x1, {trySet}
+        csrw {testMode}tvec, x1
+        csrr x25, {testMode}tvec
+      """, expected)
+
+    f.write(f"""
+      csrw {testMode}tvec, x19
+    """)
+
     # We need to leave at least one bit in medeleg unset so that we have a way to get
     # back to machine mode when the tests are complete (otherwise we'll only ever be able
     # to get up to supervisor mode). 
@@ -233,7 +247,10 @@ for xlen in xlens:
     # For testgen-TVAL, we don't need to test ebreak, so we can use that as the sole
     # returning instruction. For others, like testgen-CAUSE, we'll need to put
     # both ebreak and ecall here.
+
+
     for returningInstruction in ["ebreak"]:
+      for vectoredInterrupts in [True, False]:
 
         # All registers used:
         # x30: set to 1 if we should return to & stay in machine mode after trap, 0 otherwise
@@ -262,7 +279,7 @@ for xlen in xlens:
 
         # Set up x7 and store old value of mtvec
         lines = f"""
-        add x7, x6, x0
+          # add x7, x6, x0
           csrr x19, mtvec
         """
 
@@ -281,82 +298,86 @@ for xlen in xlens:
           jr x28
         """
 
-      beforeCode = ""
+        beforeCode = {"m": "", "s": ""}
+        for pm in ["m", "s"]:
           for i in range(0, 16):
-        beforeCode+=f"""
+            beforeCode[pm] = beforeCode[pm] + f"""
               nop
               nop
               li x25, {i}
-          j _j_m_trap_end_{returningInstruction}
+              j _j_{pm}_trap_end_{returningInstruction}_{vectoredInterrupts}
             """
 
-        ########
-        ####### FIXME: wally is causing exception code 1 when you put non 4-bit aligned into mtvec. Bad wally.
-        ########
-
         # Code for handling traps in different modes
         # Some comments are inside of the below strings (prefixed with a #, as you might expected)
+        enableVectored = "addi x1, x1, 1" if vectoredInterrupts else ""
+
         lines += f"""
           # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode
           li x30, 0
 
           # Set up 
-        la x1, _j_m_trap_{returningInstruction}
+          la x1, _j_m_trap_{returningInstruction}_{vectoredInterrupts}
-        #addi x1, 1
+          {enableVectored} # enable/don't enable vectored interrupts
           csrw mtvec, x1
-        la x1, _j_s_trap_{returningInstruction}
+          la x1, _j_s_trap_{returningInstruction}_{vectoredInterrupts}
+          {enableVectored} # enable/don't enable vectored interrupts
           csrw stvec, x1
-        la x1, _j_u_trap_{returningInstruction}
+          la x1, _j_u_trap_{returningInstruction}_{vectoredInterrupts}
+          {enableVectored} # enable/don't enable vectored interrupts
           # csrw utvec, x1 # user mode traps are not supported
 
           # Start the tests!
-        j _j_t_begin_{returningInstruction}
+          j _j_t_begin_{returningInstruction}_{vectoredInterrupts}
 
           # Machine mode traps
-        _j_m_trap_{returningInstruction}:
+          _j_m_trap_{returningInstruction}_{vectoredInterrupts}:
-        {beforeCode}
+          {beforeCode['m']}
 
-        _j_m_trap_end_{returningInstruction}:
+          _j_m_trap_end_{returningInstruction}_{vectoredInterrupts}:
           {testJumpCode}
 
           csrrs x20, mepc, x0
           addi x20, x20, 4
           csrrw x0, mepc, x20
-        bnez x30, _j_all_end_{returningInstruction}
+          bnez x30, _j_all_end_{returningInstruction}_{vectoredInterrupts}
           mret
 
           # Supervisor mode traps
-        _j_s_trap_{returningInstruction}:
+          _j_s_trap_{returningInstruction}_{vectoredInterrupts}:
-        {testJumpCode if testMode == "s" else "li x25, 0xBAD00001"}
+          {beforeCode['s']}
+
+          _j_s_trap_end_{returningInstruction}_{vectoredInterrupts}:
+          {testJumpCode}
 
           csrrs x20, sepc, x0
           addi x20, x20, 4
           csrrw x0, sepc, x20
-        bnez x30, _j_goto_machine_mode_{returningInstruction}
+          bnez x30, _j_goto_machine_mode_{returningInstruction}_{vectoredInterrupts}
           sret
 
           # Unused: user mode traps are no longer supported
-        _j_u_trap_{returningInstruction}:
+          _j_u_trap_{returningInstruction}_{vectoredInterrupts}:
           {testJumpCode if testMode == "u" else "li x25, 0xBAD00000"}
 
           csrrs x20, uepc, x0
           addi x20, x20, 4
           csrrw x0, uepc, x20
-        bnez x30, _j_goto_supervisor_mode_{returningInstruction}
+          bnez x30, _j_goto_supervisor_mode_{returningInstruction}_{vectoredInterrupts}
           uret
 
           # Currently unused. Just jumps to _j_goto_machine_mode. If you actually
           # want to implement this, you'll likely need to reset sedeleg here
           # and then cause an exception with {returningInstruction} (based on my intuition. Try that first, but I could be missing something / just wrong)
-        _j_goto_supervisor_mode_{returningInstruction}:
+          _j_goto_supervisor_mode_{returningInstruction}_{vectoredInterrupts}:
-        j _j_goto_machine_mode_{returningInstruction}
+          j _j_goto_machine_mode_{returningInstruction}_{vectoredInterrupts}
 
-        _j_goto_machine_mode_{returningInstruction}:
+          _j_goto_machine_mode_{returningInstruction}_{vectoredInterrupts}:
-        li x30, 1 # This will cause us to branch to _j_all_end_{returningInstruction} in the machine trap handler, which we'll get into by invoking...
+          li x30, 1 # This will cause us to branch to _j_all_end_{returningInstruction}_{vectoredInterrupts} in the machine trap handler, which we'll get into by invoking...
           {returningInstruction} # ... this instruction!
 
           # Run the actual tests!
-        _j_t_begin_{returningInstruction}:
+          _j_t_begin_{returningInstruction}_{vectoredInterrupts}:
         """
 
         fromModeOptions = ["m", "s", "u"] if testMode == "m" else (["s", "u"] if testMode == "s" else ["u"])
@@ -431,7 +452,7 @@ for xlen in xlens:
           li x30, 1
           li gp, 0
           {returningInstruction}
-        _j_all_end_{returningInstruction}:
+          _j_all_end_{returningInstruction}_{vectoredInterrupts}:
 
           # Reset trap handling csrs to old values
           csrw mtvec, x19
@@ -450,8 +471,3 @@ for xlen in xlens:
     f.write(lines)
     f.close()
     r.close()
-
-
-
-
-