From db164462edf9240884656a856f289b9bc81549c4 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Wed, 17 Mar 2021 16:59:02 -0500 Subject: [PATCH] adapted coremark bare testbench to new dtim RAM HDL --- wally-pipelined/testbench/testbench-coremark_bare.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index d0ac7f286..1bc6f64d0 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -74,7 +74,7 @@ module testbench(); memfilename = tests[0]; $readmemh(memfilename, dut.imem.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM); - for(j=2371; j < 65535; j = j+1) + for(j=268437829; j < 268566528; j = j+1) dut.uncore.dtim.RAM[j] = 64'b0; // ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.addr"; // ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.lab";