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Updated fpga testbench.

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This commit is contained in:
Ross Thompson 2022-08-21 14:07:26 -05:00
parent 96d6218078
commit dad6770fc3
1 changed files with 64 additions and 53 deletions
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117
pipelined/testbench/testbench-fpga.sv
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@ -56,6 +56,7 @@ logic [3:0] dummy;
logic HREADYEXT, HRESPEXT; logic HREADYEXT, HRESPEXT;
logic [31:0] HADDR; logic [31:0] HADDR;
logic [`AHBW-1:0] HWDATA; logic [`AHBW-1:0] HWDATA;
logic [`XLEN/8-1:0] HWSTRB;
logic HWRITE; logic HWRITE;
logic [2:0] HSIZE; logic [2:0] HSIZE;
logic [2:0] HBURST; logic [2:0] HBURST;
@ -105,7 +106,7 @@ logic [3:0] dummy;
assign UARTSin = 1; assign UARTSin = 1;
wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
@ -162,7 +163,7 @@ logic [3:0] dummy;
always @(negedge clk) always @(negedge clk)
begin begin
if (TEST == "coremark") if (TEST == "coremark")
if (dut.core.priv.priv.ecallM) begin if (dut.core.priv.priv.EcallFaultM) begin
$display("Benchmark: coremark is done."); $display("Benchmark: coremark is done.");
$stop; $stop;
end end
@ -342,8 +343,13 @@ module DCacheFlushFSM
localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
localparam integer numwords = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN/`XLEN; localparam integer linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
localparam integer lognumlines = $clog2(numlines); localparam integer sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;
localparam integer cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
//testbench.dut.core.lsu.bus.dcache.dcache.CacheWays.NUMSRAM;
localparam integer numwords = sramlen/`XLEN;
localparam integer lognumlines = $clog2(numlines);
localparam integer loglinebytelen = $clog2(linebytelen); localparam integer loglinebytelen = $clog2(linebytelen);
localparam integer lognumways = $clog2(numways); localparam integer lognumways = $clog2(numways);
localparam integer tagstart = lognumlines + loglinebytelen; localparam integer tagstart = lognumlines + loglinebytelen;
@ -351,65 +357,71 @@ module DCacheFlushFSM
genvar index, way, cacheWord; genvar index, way, cacheWord;
logic [`XLEN-1:0] CacheData [numways-1:0] [numlines-1:0] [numwords-1:0]; logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0]; logic [sramlen-1:0] cacheline;
logic CacheValid [numways-1:0] [numlines-1:0] [numwords-1:0]; logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
logic CacheDirty [numways-1:0] [numlines-1:0] [numwords-1:0]; logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0]; logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
for(index = 0; index < numlines; index++) begin logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
for(way = 0; way < numways; way++) begin for(index = 0; index < numlines; index++) begin
for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin for(way = 0; way < numways; way++) begin
copyShadow #(.tagstart(tagstart), for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
.loglinebytelen(loglinebytelen)) copyShadow #(.tagstart(tagstart),
copyShadow(.clk, .loglinebytelen(loglinebytelen), .sramlen(sramlen))
.start, copyShadow(.clk,
.tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.StoredData[index]), .start,
.valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]), .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.StoredData[index]),
.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]), .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
.data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.StoredData[index]), .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
.index(index), .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.StoredData[index]),
.cacheWord(cacheWord), .index(index),
.CacheData(CacheData[way][index][cacheWord]), .cacheWord(cacheWord),
.CacheAdr(CacheAdr[way][index][cacheWord]), .CacheData(CacheData[way][index][cacheWord]),
.CacheTag(CacheTag[way][index][cacheWord]), .CacheAdr(CacheAdr[way][index][cacheWord]),
.CacheValid(CacheValid[way][index][cacheWord]), .CacheTag(CacheTag[way][index][cacheWord]),
.CacheDirty(CacheDirty[way][index][cacheWord])); .CacheValid(CacheValid[way][index][cacheWord]),
end .CacheDirty(CacheDirty[way][index][cacheWord]));
end end
end end
end
integer i, j, k; integer i, j, k, l;
always @(posedge clk) begin always @(posedge clk) begin
if (start) begin #1 if (start) begin #1
#1 #1
for(i = 0; i < numlines; i++) begin for(i = 0; i < numlines; i++) begin
for(j = 0; j < numways; j++) begin for(j = 0; j < numways; j++) begin
for(k = 0; k < numwords; k++) begin for(l = 0; l < cachesramwords; l++) begin
if (CacheValid[j][i][k] & CacheDirty[j][i][k]) begin if (CacheValid[j][i][l] & CacheDirty[j][i][l]) begin
ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k]; for(k = 0; k < numwords; k++) begin
end //cacheline = CacheData[j][i][0];
end // does not work with modelsim
end // # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions.
end // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions
end //ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = cacheline[`XLEN*(k+1)-1:`XLEN*k];
end ShadowRAM[(CacheAdr[j][i][l] >> $clog2(`XLEN/8)) + k] = CacheData[j][i][l][`XLEN*k +: `XLEN];
end
end
end end
end
end
end
end
end
flop #(1) doneReg(.clk, .d(start), .q(done)); flop #(1) doneReg(.clk, .d(start), .q(done));
endmodule endmodule
module copyShadow module copyShadow
#(parameter tagstart, loglinebytelen) #(parameter tagstart, loglinebytelen, sramlen)
(input logic clk, (input logic clk,
input logic start, input logic start,
input logic [`PA_BITS-1:tagstart] tag, input logic [`PA_BITS-1:tagstart] tag,
input logic valid, dirty, input logic valid, dirty,
input logic [`XLEN-1:0] data, input logic [sramlen-1:0] data,
input logic [32-1:0] index, input logic [32-1:0] index,
input logic [32-1:0] cacheWord, input logic [32-1:0] cacheWord,
output logic [`XLEN-1:0] CacheData, output logic [sramlen-1:0] CacheData,
output logic [`PA_BITS-1:0] CacheAdr, output logic [`PA_BITS-1:0] CacheAdr,
output logic [`XLEN-1:0] CacheTag, output logic [`XLEN-1:0] CacheTag,
output logic CacheValid, output logic CacheValid,
@ -422,9 +434,8 @@ module copyShadow
CacheValid = valid; CacheValid = valid;
CacheDirty = dirty; CacheDirty = dirty;
CacheData = data; CacheData = data;
CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(`XLEN/8)); CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(sramlen/8));
end end
end end
endmodule endmodule