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https://github.com/openhwgroup/cvw
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Rough draft of cache flush fsm enhancement.
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16
pipelined/src/cache/cache.sv
vendored
16
pipelined/src/cache/cache.sv
vendored
@ -85,6 +85,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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logic [TAGLEN-1:0] TagWay [NUMWAYS-1:0];
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logic [TAGLEN-1:0] TagWay [NUMWAYS-1:0];
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logic [TAGLEN-1:0] Tag;
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logic [TAGLEN-1:0] Tag;
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logic [SETLEN-1:0] FlushAdr;
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logic [SETLEN-1:0] FlushAdr;
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logic [SETLEN-1:0] OldFlushAdr, NextFlushAdr, RawFlushAdr;
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logic [SETLEN-1:0] FlushAdrP1;
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logic [SETLEN-1:0] FlushAdrP1;
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logic FlushAdrCntEn;
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logic FlushAdrCntEn;
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logic FlushAdrCntRst;
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logic FlushAdrCntRst;
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@ -102,6 +103,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr;
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logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr;
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logic SelFetchBuffer;
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logic SelFetchBuffer;
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logic CacheEn;
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logic CacheEn;
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logic SelOldFlushAdr;
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localparam LOGLLENBYTES = $clog2(WORDLEN/8);
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localparam LOGLLENBYTES = $clog2(WORDLEN/8);
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localparam CACHEWORDSPERLINE = `DCACHE_LINELENINBITS/WORDLEN;
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localparam CACHEWORDSPERLINE = `DCACHE_LINELENINBITS/WORDLEN;
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@ -181,10 +184,15 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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assign ResetOrFlushAdr = reset | FlushAdrCntRst;
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assign ResetOrFlushAdr = reset | FlushAdrCntRst;
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flopenr #(SETLEN) FlushAdrReg(.clk, .reset(ResetOrFlushAdr), .en(FlushAdrCntEn),
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flopenr #(SETLEN) FlushAdrReg(.clk, .reset(ResetOrFlushAdr), .en(FlushAdrCntEn),
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.d(FlushAdrP1), .q(FlushAdr));
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.d(FlushAdrP1), .q(RawFlushAdr));
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assign FlushAdrP1 = FlushAdr + 1'b1;
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assign NextFlushAdr = FlushAdrCntEn ? FlushAdrP1 : RawFlushAdr;
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assign FlushAdrFlag = (FlushAdr == FlushAdrThreshold[SETLEN-1:0]);
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assign FlushAdrP1 = RawFlushAdr + 1'b1;
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assign FlushAdrFlag = (RawFlushAdr == FlushAdrThreshold[SETLEN-1:0]);
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assign ResetOrFlushWay = reset | FlushWayCntRst;
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assign ResetOrFlushWay = reset | FlushWayCntRst;
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flopenr #(SETLEN) OldFlushAdrReg(.clk, .reset(ResetOrFlushAdr), .en(FlushAdrCntEn),
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.d(NextFlushAdr), .q(OldFlushAdr));
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mux2 #(SETLEN) FlushAdrMux(NextFlushAdr, OldFlushAdr, SelOldFlushAdr, FlushAdr);
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flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), .en(FlushWayCntEn),
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flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), .en(FlushWayCntEn),
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.val({{NUMWAYS-1{1'b0}}, 1'b1}), .d(NextFlushWay), .q(FlushWay));
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.val({{NUMWAYS-1{1'b0}}, 1'b1}), .d(NextFlushWay), .q(FlushWay));
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assign FlushWayFlag = FlushWay[NUMWAYS-1];
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assign FlushWayFlag = FlushWay[NUMWAYS-1];
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@ -200,7 +208,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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.CacheMiss, .CacheAccess, .SelAdr,
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.CacheMiss, .CacheAccess, .SelAdr,
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.ClearValid, .ClearDirty, .SetDirty,
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.ClearValid, .ClearDirty, .SetDirty,
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.SetValid, .SelWriteback, .SelFlush,
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.SetValid, .SelWriteback, .SelFlush,
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.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
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.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, .SelOldFlushAdr,
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.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer,
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.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer,
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.InvalidateCache,
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.InvalidateCache,
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.CacheEn,
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.CacheEn,
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35
pipelined/src/cache/cachefsm.sv
vendored
35
pipelined/src/cache/cachefsm.sv
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@ -72,6 +72,7 @@ module cachefsm
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output logic FlushAdrCntRst,
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output logic FlushAdrCntRst,
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output logic FlushWayCntRst,
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output logic FlushWayCntRst,
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output logic SelFetchBuffer,
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output logic SelFetchBuffer,
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output logic SelOldFlushAdr,
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output logic CacheEn);
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output logic CacheEn);
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logic resetDelay;
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logic resetDelay;
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@ -135,6 +136,14 @@ module cachefsm
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STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_FETCH_WDV;
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STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_FETCH_WDV;
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else NextState = STATE_MISS_EVICT_DIRTY;
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else NextState = STATE_MISS_EVICT_DIRTY;
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// eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
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// eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
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STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITE_BACK;
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else if (FlushFlag & FlushWayFlag) NextState = STATE_READY;
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else NextState = STATE_FLUSH;
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STATE_FLUSH_WRITE_BACK: if(CacheBusAck & ~(FlushFlag & FlushWayFlag)) NextState = STATE_FLUSH;
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else if(CacheBusAck) NextState = STATE_READY;
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else NextState = STATE_FLUSH_WRITE_BACK;
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/* -----\/----- EXCLUDED -----\/-----
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STATE_FLUSH: NextState = STATE_FLUSH_CHECK;
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STATE_FLUSH: NextState = STATE_FLUSH_CHECK;
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STATE_FLUSH_CHECK: if(LineDirty) NextState = STATE_FLUSH_WRITE_BACK;
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STATE_FLUSH_CHECK: if(LineDirty) NextState = STATE_FLUSH_WRITE_BACK;
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else if(FlushFlag) NextState = STATE_READY;
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else if(FlushFlag) NextState = STATE_READY;
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@ -146,6 +155,7 @@ module cachefsm
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else if(FlushWayFlag) NextState = STATE_FLUSH_INCR;
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else if(FlushWayFlag) NextState = STATE_FLUSH_INCR;
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else NextState = STATE_FLUSH_CHECK;
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else NextState = STATE_FLUSH_CHECK;
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end else NextState = STATE_FLUSH_WRITE_BACK;
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end else NextState = STATE_FLUSH_WRITE_BACK;
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-----/\----- EXCLUDED -----/\----- */
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default: NextState = STATE_READY;
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default: NextState = STATE_READY;
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endcase
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endcase
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end
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end
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@ -156,10 +166,10 @@ module cachefsm
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(CurrState == STATE_MISS_FETCH_WDV) |
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(CurrState == STATE_MISS_FETCH_WDV) |
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(CurrState == STATE_MISS_EVICT_DIRTY) |
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(CurrState == STATE_MISS_EVICT_DIRTY) |
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(CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(StoreAMO)) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
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(CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(StoreAMO)) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
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(CurrState == STATE_FLUSH) |
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(CurrState == STATE_FLUSH & ~(FlushFlag & ~LineDirty)) |
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(CurrState == STATE_FLUSH_CHECK & ~(FlushFlag)) |
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//(CurrState == STATE_FLUSH_CHECK & ~(FlushFlag)) |
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(CurrState == STATE_FLUSH_INCR) |
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//(CurrState == STATE_FLUSH_INCR) |
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(CurrState == STATE_FLUSH_WRITE_BACK & ~(FlushFlag) & CacheBusAck);
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(CurrState == STATE_FLUSH_WRITE_BACK & ~(FlushFlag & CacheBusAck));
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// write enables internal to cache
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// write enables internal to cache
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assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE;
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assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE;
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assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) |
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assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) |
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@ -175,12 +185,17 @@ module cachefsm
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assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) |
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assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) |
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(CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK);
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(CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK);
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assign FlushWayAndNotAdrFlag = FlushWayFlag & ~FlushAdrFlag;
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assign FlushWayAndNotAdrFlag = FlushWayFlag & ~FlushAdrFlag;
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assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~LineDirty & FlushWayAndNotAdrFlag) |
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//assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~LineDirty & FlushWayAndNotAdrFlag) |
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(CurrState == STATE_FLUSH_WRITE_BACK & FlushWayAndNotAdrFlag & CacheBusAck);
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// (CurrState == STATE_FLUSH_WRITE_BACK & FlushWayAndNotAdrFlag & CacheBusAck);
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assign FlushWayCntEn = (CurrState == STATE_FLUSH_CHECK & ~LineDirty & ~(FlushFlag)) |
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assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITE_BACK & FlushWayFlag & CacheBusAck) |
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(CurrState == STATE_FLUSH_WRITE_BACK & ~FlushFlag & CacheBusAck);
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(CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty);
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assign FlushAdrCntRst = (CurrState == STATE_READY);
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assign FlushWayCntEn = (CurrState == STATE_FLUSH & ~LineDirty) |
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assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR);
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(CurrState == STATE_FLUSH_WRITE_BACK & CacheBusAck);
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assign FlushAdrCntRst = (CurrState == STATE_FLUSH & FlushFlag & FlushWayFlag & ~LineDirty) |
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(CurrState == STATE_FLUSH_WRITE_BACK & FlushFlag & FlushWayFlag & CacheBusAck);
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assign FlushWayCntRst = FlushAdrCntRst;
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assign SelOldFlushAdr = (CurrState == STATE_FLUSH & LineDirty) |
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(CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck);
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// Bus interface controls
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// Bus interface controls
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assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) |
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assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) |
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(CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck) |
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(CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck) |
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@ -131,8 +131,8 @@ module buscachefsm #(parameter integer BeatCountThreshold,
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assign BusStall = (CurrState == ADR_PHASE & (|BusRW | |CacheBusRW)) |
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assign BusStall = (CurrState == ADR_PHASE & (|BusRW | |CacheBusRW)) |
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//(CurrState == DATA_PHASE & ~BusRW[0]) | // replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem.
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//(CurrState == DATA_PHASE & ~BusRW[0]) | // replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem.
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(CurrState == DATA_PHASE) |
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(CurrState == DATA_PHASE) |
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(CurrState == CACHE_FETCH) |
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(CurrState == CACHE_FETCH & ~HREADY) |
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(CurrState == CACHE_WRITEBACK);
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(CurrState == CACHE_WRITEBACK & ~HREADY);
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assign BusCommitted = CurrState != ADR_PHASE;
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assign BusCommitted = CurrState != ADR_PHASE;
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// AHB bus interface
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// AHB bus interface
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