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Rough draft of cache flush fsm enhancement.

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This commit is contained in:
Ross Thompson 2022-12-16 15:28:22 -06:00
parent bc907f3e2f
commit dacba855da
3 changed files with 39 additions and 16 deletions
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16
pipelined/src/cache/cache.sv vendored
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@ -85,6 +85,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
logic [TAGLEN-1:0] TagWay [NUMWAYS-1:0]; logic [TAGLEN-1:0] TagWay [NUMWAYS-1:0];
logic [TAGLEN-1:0] Tag; logic [TAGLEN-1:0] Tag;
logic [SETLEN-1:0] FlushAdr; logic [SETLEN-1:0] FlushAdr;
logic [SETLEN-1:0] OldFlushAdr, NextFlushAdr, RawFlushAdr;
logic [SETLEN-1:0] FlushAdrP1; logic [SETLEN-1:0] FlushAdrP1;
logic FlushAdrCntEn; logic FlushAdrCntEn;
logic FlushAdrCntRst; logic FlushAdrCntRst;
@ -102,6 +103,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr; logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr;
logic SelFetchBuffer; logic SelFetchBuffer;
logic CacheEn; logic CacheEn;
logic SelOldFlushAdr;
localparam LOGLLENBYTES = $clog2(WORDLEN/8); localparam LOGLLENBYTES = $clog2(WORDLEN/8);
localparam CACHEWORDSPERLINE = `DCACHE_LINELENINBITS/WORDLEN; localparam CACHEWORDSPERLINE = `DCACHE_LINELENINBITS/WORDLEN;
@ -181,10 +184,15 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
assign ResetOrFlushAdr = reset | FlushAdrCntRst; assign ResetOrFlushAdr = reset | FlushAdrCntRst;
flopenr #(SETLEN) FlushAdrReg(.clk, .reset(ResetOrFlushAdr), .en(FlushAdrCntEn), flopenr #(SETLEN) FlushAdrReg(.clk, .reset(ResetOrFlushAdr), .en(FlushAdrCntEn),
.d(FlushAdrP1), .q(FlushAdr)); .d(FlushAdrP1), .q(RawFlushAdr));
assign FlushAdrP1 = FlushAdr + 1'b1; assign NextFlushAdr = FlushAdrCntEn ? FlushAdrP1 : RawFlushAdr;
assign FlushAdrFlag = (FlushAdr == FlushAdrThreshold[SETLEN-1:0]); assign FlushAdrP1 = RawFlushAdr + 1'b1;
assign FlushAdrFlag = (RawFlushAdr == FlushAdrThreshold[SETLEN-1:0]);
assign ResetOrFlushWay = reset | FlushWayCntRst; assign ResetOrFlushWay = reset | FlushWayCntRst;
flopenr #(SETLEN) OldFlushAdrReg(.clk, .reset(ResetOrFlushAdr), .en(FlushAdrCntEn),
.d(NextFlushAdr), .q(OldFlushAdr));
mux2 #(SETLEN) FlushAdrMux(NextFlushAdr, OldFlushAdr, SelOldFlushAdr, FlushAdr);
flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), .en(FlushWayCntEn), flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), .en(FlushWayCntEn),
.val({{NUMWAYS-1{1'b0}}, 1'b1}), .d(NextFlushWay), .q(FlushWay)); .val({{NUMWAYS-1{1'b0}}, 1'b1}), .d(NextFlushWay), .q(FlushWay));
assign FlushWayFlag = FlushWay[NUMWAYS-1]; assign FlushWayFlag = FlushWay[NUMWAYS-1];
@ -200,7 +208,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
.CacheMiss, .CacheAccess, .SelAdr, .CacheMiss, .CacheAccess, .SelAdr,
.ClearValid, .ClearDirty, .SetDirty, .ClearValid, .ClearDirty, .SetDirty,
.SetValid, .SelWriteback, .SelFlush, .SetValid, .SelWriteback, .SelFlush,
.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, .FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, .SelOldFlushAdr,
.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer, .FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer,
.InvalidateCache, .InvalidateCache,
.CacheEn, .CacheEn,

35
pipelined/src/cache/cachefsm.sv vendored
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@ -72,6 +72,7 @@ module cachefsm
output logic FlushAdrCntRst, output logic FlushAdrCntRst,
output logic FlushWayCntRst, output logic FlushWayCntRst,
output logic SelFetchBuffer, output logic SelFetchBuffer,
output logic SelOldFlushAdr,
output logic CacheEn); output logic CacheEn);
logic resetDelay; logic resetDelay;
@ -135,6 +136,14 @@ module cachefsm
STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_FETCH_WDV; STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_FETCH_WDV;
else NextState = STATE_MISS_EVICT_DIRTY; else NextState = STATE_MISS_EVICT_DIRTY;
// eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITE_BACK;
else if (FlushFlag & FlushWayFlag) NextState = STATE_READY;
else NextState = STATE_FLUSH;
STATE_FLUSH_WRITE_BACK: if(CacheBusAck & ~(FlushFlag & FlushWayFlag)) NextState = STATE_FLUSH;
else if(CacheBusAck) NextState = STATE_READY;
else NextState = STATE_FLUSH_WRITE_BACK;
/* -----\/----- EXCLUDED -----\/-----
STATE_FLUSH: NextState = STATE_FLUSH_CHECK; STATE_FLUSH: NextState = STATE_FLUSH_CHECK;
STATE_FLUSH_CHECK: if(LineDirty) NextState = STATE_FLUSH_WRITE_BACK; STATE_FLUSH_CHECK: if(LineDirty) NextState = STATE_FLUSH_WRITE_BACK;
else if(FlushFlag) NextState = STATE_READY; else if(FlushFlag) NextState = STATE_READY;
@ -146,6 +155,7 @@ module cachefsm
else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; else if(FlushWayFlag) NextState = STATE_FLUSH_INCR;
else NextState = STATE_FLUSH_CHECK; else NextState = STATE_FLUSH_CHECK;
end else NextState = STATE_FLUSH_WRITE_BACK; end else NextState = STATE_FLUSH_WRITE_BACK;
-----/\----- EXCLUDED -----/\----- */
default: NextState = STATE_READY; default: NextState = STATE_READY;
endcase endcase
end end
@ -156,10 +166,10 @@ module cachefsm
(CurrState == STATE_MISS_FETCH_WDV) | (CurrState == STATE_MISS_FETCH_WDV) |
(CurrState == STATE_MISS_EVICT_DIRTY) | (CurrState == STATE_MISS_EVICT_DIRTY) |
(CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(StoreAMO)) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write. (CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(StoreAMO)) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
(CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH & ~(FlushFlag & ~LineDirty)) |
(CurrState == STATE_FLUSH_CHECK & ~(FlushFlag)) | //(CurrState == STATE_FLUSH_CHECK & ~(FlushFlag)) |
(CurrState == STATE_FLUSH_INCR) | //(CurrState == STATE_FLUSH_INCR) |
(CurrState == STATE_FLUSH_WRITE_BACK & ~(FlushFlag) & CacheBusAck); (CurrState == STATE_FLUSH_WRITE_BACK & ~(FlushFlag & CacheBusAck));
// write enables internal to cache // write enables internal to cache
assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE; assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE;
assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) | assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) |
@ -175,12 +185,17 @@ module cachefsm
assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) | assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) |
(CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK); (CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK);
assign FlushWayAndNotAdrFlag = FlushWayFlag & ~FlushAdrFlag; assign FlushWayAndNotAdrFlag = FlushWayFlag & ~FlushAdrFlag;
assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~LineDirty & FlushWayAndNotAdrFlag) | //assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~LineDirty & FlushWayAndNotAdrFlag) |
(CurrState == STATE_FLUSH_WRITE_BACK & FlushWayAndNotAdrFlag & CacheBusAck); // (CurrState == STATE_FLUSH_WRITE_BACK & FlushWayAndNotAdrFlag & CacheBusAck);
assign FlushWayCntEn = (CurrState == STATE_FLUSH_CHECK & ~LineDirty & ~(FlushFlag)) | assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITE_BACK & FlushWayFlag & CacheBusAck) |
(CurrState == STATE_FLUSH_WRITE_BACK & ~FlushFlag & CacheBusAck); (CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty);
assign FlushAdrCntRst = (CurrState == STATE_READY); assign FlushWayCntEn = (CurrState == STATE_FLUSH & ~LineDirty) |
assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR); (CurrState == STATE_FLUSH_WRITE_BACK & CacheBusAck);
assign FlushAdrCntRst = (CurrState == STATE_FLUSH & FlushFlag & FlushWayFlag & ~LineDirty) |
(CurrState == STATE_FLUSH_WRITE_BACK & FlushFlag & FlushWayFlag & CacheBusAck);
assign FlushWayCntRst = FlushAdrCntRst;
assign SelOldFlushAdr = (CurrState == STATE_FLUSH & LineDirty) |
(CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck);
// Bus interface controls // Bus interface controls
assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) |
(CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck) | (CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck) |

4
pipelined/src/ebu/buscachefsm.sv
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@ -131,8 +131,8 @@ module buscachefsm #(parameter integer BeatCountThreshold,
assign BusStall = (CurrState == ADR_PHASE & (|BusRW | |CacheBusRW)) | assign BusStall = (CurrState == ADR_PHASE & (|BusRW | |CacheBusRW)) |
//(CurrState == DATA_PHASE & ~BusRW[0]) | // replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem. //(CurrState == DATA_PHASE & ~BusRW[0]) | // replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem.
(CurrState == DATA_PHASE) | (CurrState == DATA_PHASE) |
(CurrState == CACHE_FETCH) | (CurrState == CACHE_FETCH & ~HREADY) |
(CurrState == CACHE_WRITEBACK); (CurrState == CACHE_WRITEBACK & ~HREADY);
assign BusCommitted = CurrState != ADR_PHASE; assign BusCommitted = CurrState != ADR_PHASE;
// AHB bus interface // AHB bus interface