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	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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						dac93bb366
					
				@ -99,8 +99,6 @@ module ifu (
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  logic 	    BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
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					  logic 	    BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
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  logic 	    PMPInstrAccessFaultF, PMAInstrAccessFaultF;
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  logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
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					  logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
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  logic [`XLEN+1:0]    PCFExt;
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					  logic [`XLEN+1:0]    PCFExt;
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@ -78,7 +78,7 @@ module tlbcontrol #(parameter ITLB = 0) (
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  endgenerate
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					  endgenerate
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  // Determine whether TLB is being used
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					  // Determine whether TLB is being used
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  assign TLBAccess = ReadAccess || WriteAccess;
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					  assign TLBAccess = ReadAccess | WriteAccess;
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  // Check whether upper bits of virtual addresss are all equal
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					  // Check whether upper bits of virtual addresss are all equal
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@ -120,5 +120,5 @@ module tlbcontrol #(parameter ITLB = 0) (
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  endgenerate
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					  endgenerate
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  assign TLBHit = CAMHit & TLBAccess;
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					  assign TLBHit = CAMHit & TLBAccess;
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  assign TLBMiss = ~CAMHit & ~TLBFlush & Translate & TLBAccess;
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					  assign TLBMiss = (~CAMHit | TLBFlush) & Translate & TLBAccess;
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endmodule
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					endmodule
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@ -102,6 +102,7 @@ module privileged (
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  logic       STATUS_MIE, STATUS_SIE;
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					  logic       STATUS_MIE, STATUS_SIE;
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  logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW;
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					  logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW;
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  logic md, sd;
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					  logic md, sd;
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					  logic       StallMQ;
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  ///////////////////////////////////////////
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					  ///////////////////////////////////////////
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@ -157,8 +158,16 @@ module privileged (
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  assign BreakpointFaultM = ebreakM; // could have other causes too
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					  assign BreakpointFaultM = ebreakM; // could have other causes too
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  assign EcallFaultM = ecallM;
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					  assign EcallFaultM = ecallM;
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  assign ITLBFlushF = sfencevmaM;
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					  flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ));
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					  assign ITLBFlushF = sfencevmaM & ~StallMQ;
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  assign DTLBFlushM = sfencevmaM;
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					  assign DTLBFlushM = sfencevmaM;
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					  // sets ITLBFlush to pulse for one cycle of the sfence.vma instruction
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					  // In this instr we want to flush the tlb and then do a pagetable walk to update the itlb and continue the program.
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					  // But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and 
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					  // the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush 
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					  // after a cycle AND pulse it for another cycle on any further back-to-back sfences. 
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  // A page fault might occur because of insufficient privilege during a TLB
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					  // A page fault might occur because of insufficient privilege during a TLB
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  // lookup or a improperly formatted page table during walking
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					  // lookup or a improperly formatted page table during walking
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