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Merge pull request #1231 from jordancarlin/compressed_decode

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Decode compressed instructions in instrNameDecTB
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David Harris 2025-01-13 11:01:25 -08:00 committed by GitHub
commit dac75fd17e
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4 changed files with 403 additions and 322 deletions
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87
testbench/common/instrNameDecTB.sv
View File

@ -22,29 +22,109 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
// decode the instruction name, to help the test bench // decode the instruction name, to help the test bench
module instrNameDecTB( module instrNameDecTB #(parameter XLEN) (
input logic [31:0] instr, input logic [31:0] instr,
output string name); output string name);
logic [6:0] op; logic [6:0] op;
logic funct1;
logic [1:0] funct2;
logic [2:0] funct3; logic [2:0] funct3;
logic [4:0] funct5;
logic [6:0] funct7; logic [6:0] funct7;
logic [11:0] imm; logic [11:0] imm;
logic [4:0] rs2, rd; logic [4:0] rs2, rd, CRrs2;
logic [1:0] compressedOp;
logic [5:0] compressed15_10;
assign op = instr[6:0]; assign op = instr[6:0];
assign funct1 = instr[6];
assign funct2 = instr[6:5];
assign funct3 = instr[14:12]; assign funct3 = instr[14:12];
assign funct5 = instr[6:2];
assign funct7 = instr[31:25]; assign funct7 = instr[31:25];
assign imm = instr[31:20]; assign imm = instr[31:20];
assign rs2 = instr[24:20]; assign rs2 = instr[24:20];
assign rd = instr[11:7]; assign rd = instr[11:7];
assign compressedOp = instr[1:0];
assign compressed15_10 = instr[15:10];
assign CRrs2 = instr[6:2];
// it would be nice to add the operands to the name // it would be nice to add the operands to the name
// create another variable called decoded // create another variable called decoded
always_comb always_comb
case (compressedOp)
2'b00:
casez (compressed15_10)
6'b000???: if (instr[12:7] != 8'b0) name = "C.ADDI4SPN";
6'b010???: name = "C.LW";
6'b110???: name = "C.SW";
6'b011???: if (XLEN == 32'd32) name = "C.FLW";
else name = "C.LD";
6'b111???: if (XLEN == 32'd32) name = "C.FSW";
else name = "C.SD";
6'b100000: name = "C.LBU";
6'b100001: if (funct1 == 1'b1) name = "C.LH";
else if (funct1 == 1'b0) name = "C.LHU";
6'b100010: name = "C.SB";
6'b100011: if (funct1 == 1'b0) name = "C.SH";
6'b001???: name = "C.FLD";
6'b101???: name = "C.FSD";
6'b000000: if(op == 7'b0000000 & funct3 == 3'b000) name = "BAD";
default: name = "ILLEGAL";
endcase
2'b01:
casez (compressed15_10)
6'b000000: if (rd == 5'b00000 & instr[6:2] == 5'b00000) name = "C.NOP";
6'b000???: if (rd != 5'b00000 & instr[6:2] != 5'b00000) name = "C.ADDI";
6'b010???: if (rd != 5'b00000) name = "C.LI";
6'b011???: if (rd != 5'b00000 & rd != 5'b00010 & instr[6:2] != 5'b00000) name = "C.LUI";
6'b011???: if (rd == 5'b00010 & instr[6:2] != 5'b00000) name = "C.ADDI16SP";
6'b100?00: name = "C.SRLI";
6'b100?01: name = "C.SRAI";
6'b100?10: name = "C.ANDI";
6'b100011: if (funct2 == 2'b00) name = "C.SUB";
else if (funct2 == 2'b01) name = "C.XOR";
else if (funct2 == 2'b10) name = "C.OR";
else if (funct2 == 2'b11) name = "C.AND";
6'b101???: name = "C.J";
6'b110???: name = "C.BEQZ";
6'b111???: name = "C.BNEZ";
6'b001???: if (XLEN == 32'd32) name = "C.JAL";
else if (XLEN == 32'd64 & rd != 5'b00000) name = "C.ADDIW";
6'b100111: if (XLEN == 32'd64 & funct2 == 2'b00) name = "C.SUBW";
else if (XLEN == 32'd64 & funct2 == 2'b01) name = "C.ADDW";
6'b100111: if (funct5 == 5'b11000) name = "C.ZEXT.B";
else if (funct5 == 5'b11001) name = "C.SEXT.B";
else if (funct5 == 5'b11010) name = "C.ZEXT.H";
else if (funct5 == 5'b11011) name = "C.SEXT.H";
else if (funct5 == 5'b11101) name = "C.NOT";
else if (funct2 == 2'b10) name = "C.MUL";
else if (funct5 == 5'b11100) name = "C.ZEXT.W";
default: name = "ILLEGAL";
endcase
2'b10:
casez (compressed15_10)
6'b000???: if (rd != 5'b00000) name = "C.SLLI";
6'b010???: if (rd != 5'b00000) name = "C.LWSP";
6'b1000??: if (rd != 5'b00000 & CRrs2 == 5'b00000 ) name = "C.JR";
6'b1000??: if (rd != 5'b00000 & CRrs2 != 5'b00000 ) name = "C.MV";
6'b1001??: if (rd == 5'b00000 & CRrs2 == 5'b00000 ) name = "C.EBREAK";
6'b1001??: if (rd != 5'b00000 & CRrs2 == 5'b00000 ) name = "C.JALR";
6'b1001??: if (rd != 5'b00000 & CRrs2 != 5'b00000 ) name = "C.ADD";
6'b110???: name = "C.SWSP";
6'b011???: if (XLEN == 32'd32) name = "C.FLWSP";
else if (rd != 5'b00000) name = "C.LDSP";
6'b111???: if (XLEN == 32'd32) name = "C.FSWSP";
else name = "C.SDSP";
6'b001???: name = "C.FLDSP";
6'b101???: name = "C.FSDSP";
default: name = "ILLEGAL";
endcase
2'b11:
casez({op, funct3}) casez({op, funct3})
10'b0000000_000: name = "BAD";
10'b0000011_000: name = "LB"; 10'b0000011_000: name = "LB";
10'b0000011_001: name = "LH"; 10'b0000011_001: name = "LH";
10'b0000011_010: name = "LW"; 10'b0000011_010: name = "LW";
@ -355,4 +435,5 @@ module instrNameDecTB(
10'b0100111_100: name = "FSQ"; 10'b0100111_100: name = "FSQ";
default: name = "ILLEGAL"; default: name = "ILLEGAL";
endcase endcase
endcase
endmodule endmodule

12
testbench/common/instrTrackerTB.sv
View File

@ -19,7 +19,7 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module instrTrackerTB( module instrTrackerTB #(parameter XLEN) (
input logic clk, reset, FlushE, input logic clk, reset, FlushE,
input logic [31:0] InstrF, InstrD, input logic [31:0] InstrF, InstrD,
input logic [31:0] InstrE, InstrM, input logic [31:0] InstrE, InstrM,
@ -30,9 +30,9 @@ module instrTrackerTB(
// stage Instr to Writeback for visualization // stage Instr to Writeback for visualization
// flopr #(32) InstrWReg(clk, reset, InstrM, InstrW); // flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
instrNameDecTB fdec(InstrF, InstrFName); instrNameDecTB #(XLEN) fdec(InstrF, InstrFName);
instrNameDecTB ddec(InstrD, InstrDName); instrNameDecTB #(XLEN) ddec(InstrD, InstrDName);
instrNameDecTB edec(InstrE, InstrEName); instrNameDecTB #(XLEN) edec(InstrE, InstrEName);
instrNameDecTB mdec(InstrM, InstrMName); instrNameDecTB #(XLEN) mdec(InstrM, InstrMName);
instrNameDecTB wdec(InstrW, InstrWName); instrNameDecTB #(XLEN) wdec(InstrW, InstrWName);
endmodule endmodule

2
testbench/common/wallyTracer.sv
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@ -733,7 +733,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
int file; int file;
string LogFile; string LogFile;
if(`STD_LOG) begin if(`STD_LOG) begin
instrNameDecTB NameDecoder(rvvi.insn[0][0], instrWName); instrNameDecTB #(P.XLEN) NameDecoder(rvvi.insn[0][0], instrWName);
initial begin initial begin
LogFile = "logs/boottrace.log"; LogFile = "logs/boottrace.log";
file = $fopen(LogFile, "w"); file = $fopen(LogFile, "w");

2
testbench/testbench.sv
View File

@ -669,7 +669,7 @@ module testbench;
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
logic [31:0] InstrW; logic [31:0] InstrW;
flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, InstrM, InstrW); flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, InstrM, InstrW);
instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE, instrTrackerTB #(P.XLEN) it(clk, reset, dut.core.ieu.dp.FlushE,
dut.core.ifu.InstrRawF[31:0], dut.core.ifu.InstrRawF[31:0],
dut.core.ifu.InstrD, dut.core.ifu.InstrE, dut.core.ifu.InstrD, dut.core.ifu.InstrE,
InstrM, InstrW, InstrM, InstrW,