From dab9d7ab3c9d64d012fc52ba1ee5af97525a3038 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Fri, 15 Dec 2023 13:07:08 -0600
Subject: [PATCH] Replaced fpga top level verilog with system verilog.

---
 fpga/generator/wally.tcl                       | 2 +-
 fpga/src/{fpgaTopArtyA7.v => fpgaTopArtyA7.sv} | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename fpga/src/{fpgaTopArtyA7.v => fpgaTopArtyA7.sv} (100%)

diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index bad9981df..119f50326 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -17,7 +17,7 @@ read_verilog -sv  ../src/CopiedFiles_do_not_add_to_repo/cvw.sv
 read_verilog -sv  ../src/wallypipelinedsocwrapper.sv
 # then read top level
 if {$board=="ArtyA7"} {
-    read_verilog  {../src/fpgaTopArtyA7.v}
+    read_verilog  {../src/fpgaTopArtyA7.sv}
 } else {
     read_verilog  {../src/fpgaTop.v}
 }
diff --git a/fpga/src/fpgaTopArtyA7.v b/fpga/src/fpgaTopArtyA7.sv
similarity index 100%
rename from fpga/src/fpgaTopArtyA7.v
rename to fpga/src/fpgaTopArtyA7.sv