From daac21b3bd96ab105bf2d72f4610ce6f3952bb78 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Dec 2021 14:17:18 -0600 Subject: [PATCH] Moved generate for lrsc to lsu. --- wally-pipelined/src/lsu/lrsc.sv | 41 ++++++++++++++------------------- wally-pipelined/src/lsu/lsu.sv | 13 ++++++++--- 2 files changed, 27 insertions(+), 27 deletions(-) diff --git a/wally-pipelined/src/lsu/lrsc.sv b/wally-pipelined/src/lsu/lrsc.sv index d7307702a..1bd2c3ca4 100644 --- a/wally-pipelined/src/lsu/lrsc.sv +++ b/wally-pipelined/src/lsu/lrsc.sv @@ -38,29 +38,22 @@ module lrsc output logic SquashSCW ); // Handle atomic load reserved / store conditional - generate - if (`A_SUPPORTED) begin // atomic instructions supported - logic [`PA_BITS-1:2] ReservationPAdrW; - logic ReservationValidM, ReservationValidW; - logic lrM, scM, WriteAdrMatchM; - logic SquashSCM; + logic [`PA_BITS-1:2] ReservationPAdrW; + logic ReservationValidM, ReservationValidW; + logic lrM, scM, WriteAdrMatchM; + logic SquashSCM; - assign lrM = MemReadM && LsuAtomicM[0]; - assign scM = LsuRWM[0] && LsuAtomicM[0]; - assign WriteAdrMatchM = LsuRWM[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; - assign SquashSCM = scM && ~WriteAdrMatchM; - assign DCRWM = SquashSCM ? 2'b00 : LsuRWM; - always_comb begin // ReservationValidM (next value of valid reservation) - if (lrM) ReservationValidM = 1; // set valid on load reserve - else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc - else ReservationValidM = ReservationValidW; // otherwise don't change valid - end - flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid - flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW); - flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW); - end else begin // Atomic operations not supported - assign SquashSCW = 0; - assign DCRWM = LsuRWM; - end - endgenerate + assign lrM = MemReadM && LsuAtomicM[0]; + assign scM = LsuRWM[0] && LsuAtomicM[0]; + assign WriteAdrMatchM = LsuRWM[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; + assign SquashSCM = scM && ~WriteAdrMatchM; + assign DCRWM = SquashSCM ? 2'b00 : LsuRWM; + always_comb begin // ReservationValidM (next value of valid reservation) + if (lrM) ReservationValidM = 1; // set valid on load reserve + else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc + else ReservationValidM = ReservationValidW; // otherwise don't change valid + end + flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid + flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW); + flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW); endmodule diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 1bdb37794..23ff5d17d 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -258,9 +258,16 @@ module lsu // Move generate from lrsc to outside this module. - assign MemReadM = LsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM; - lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .LsuRWM, .LsuAtomicM, .MemPAdrM, - .SquashSCW, .DCRWM); + generate + if (`A_SUPPORTED) begin + assign MemReadM = LsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM; + lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .LsuRWM, .LsuAtomicM, .MemPAdrM, + .SquashSCW, .DCRWM); + end else begin + assign SquashSCW = 0; + assign DCRWM = LsuRWM; + end + endgenerate // Specify which type of page fault is occurring // *** `MEM_VIRTMEM