From da4eec7e0efcba3101d86e84ca369c6767de3973 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 19 Jan 2023 17:41:57 -0600 Subject: [PATCH] Improved comment. --- pipelined/src/generic/mem/ram1p1rwbe.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/pipelined/src/generic/mem/ram1p1rwbe.sv index 6ad27d013..5abb85041 100644 --- a/pipelined/src/generic/mem/ram1p1rwbe.sv +++ b/pipelined/src/generic/mem/ram1p1rwbe.sv @@ -64,13 +64,13 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( end else begin: ram integer i; - // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff. - // Therefore these always blocks use the older always @(posedge clk) // Read - always @(posedge clk) + always_ff @(posedge clk) if(ce) dout <= #1 RAM[addr]; // Write divided into part for bytes and part for extra msbs + // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff. + // Therefore these always blocks use the older always @(posedge clk) if(WIDTH >= 8) always @(posedge clk) if (ce & we)