mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-03 02:05:21 +00:00
Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int.
This commit is contained in:
David Harris
parent
9e78a7e290
commit
da4eca4854
@ -41,6 +41,7 @@ localparam ZICNTR_SUPPORTED = 1;
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localparam ZIHPM_SUPPORTED = 1;
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localparam ZIHPM_SUPPORTED = 1;
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localparam COUNTERS = 12'd32;
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localparam COUNTERS = 12'd32;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFA_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 1;
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localparam SSTC_SUPPORTED = 1;
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localparam ZICBOM_SUPPORTED = 1;
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localparam ZICBOM_SUPPORTED = 1;
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localparam ZICBOZ_SUPPORTED = 1;
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localparam ZICBOZ_SUPPORTED = 1;
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@ -41,6 +41,7 @@ localparam COUNTERS = 12'd0;
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localparam ZICNTR_SUPPORTED = 0;
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localparam ZICNTR_SUPPORTED = 0;
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localparam ZIHPM_SUPPORTED = 0;
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localparam ZIHPM_SUPPORTED = 0;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFA_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 0;
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localparam ZICBOM_SUPPORTED = 0;
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localparam ZICBOM_SUPPORTED = 0;
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localparam ZICBOZ_SUPPORTED = 0;
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localparam ZICBOZ_SUPPORTED = 0;
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@ -42,6 +42,7 @@ localparam COUNTERS = 12'd32;
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localparam ZICNTR_SUPPORTED = 1;
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localparam ZICNTR_SUPPORTED = 1;
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localparam ZIHPM_SUPPORTED = 1;
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localparam ZIHPM_SUPPORTED = 1;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFA_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 1;
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localparam SSTC_SUPPORTED = 1;
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localparam ZICBOM_SUPPORTED = 1;
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localparam ZICBOM_SUPPORTED = 1;
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localparam ZICBOZ_SUPPORTED = 1;
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localparam ZICBOZ_SUPPORTED = 1;
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@ -41,6 +41,7 @@ localparam COUNTERS = 0;
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localparam ZICNTR_SUPPORTED = 0;
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localparam ZICNTR_SUPPORTED = 0;
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localparam ZIHPM_SUPPORTED = 0;
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localparam ZIHPM_SUPPORTED = 0;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFA_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 0;
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localparam ZICBOM_SUPPORTED = 0;
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localparam ZICBOM_SUPPORTED = 0;
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localparam ZICBOZ_SUPPORTED = 0;
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localparam ZICBOZ_SUPPORTED = 0;
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@ -40,6 +40,7 @@ localparam COUNTERS = 12'd32;
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localparam ZICNTR_SUPPORTED = 1;
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localparam ZICNTR_SUPPORTED = 1;
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localparam ZIHPM_SUPPORTED = 1;
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localparam ZIHPM_SUPPORTED = 1;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFA_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 0;
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localparam ZICBOM_SUPPORTED = 0;
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localparam ZICBOM_SUPPORTED = 0;
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localparam ZICBOZ_SUPPORTED = 0;
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localparam ZICBOZ_SUPPORTED = 0;
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@ -31,7 +31,7 @@
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localparam XLEN = 32'd64;
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localparam XLEN = 32'd64;
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// IEEE 754 compliance
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// IEEE 754 compliance
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localparam IEEE754 = 0;
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localparam IEEE754 = 1;
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// MISA RISC-V configuration per specification
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// MISA RISC-V configuration per specification
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localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 );
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localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 );
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@ -41,6 +41,7 @@ localparam COUNTERS = 12'd32;
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localparam ZICNTR_SUPPORTED = 1;
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localparam ZICNTR_SUPPORTED = 1;
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localparam ZIHPM_SUPPORTED = 1;
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localparam ZIHPM_SUPPORTED = 1;
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localparam ZFH_SUPPORTED = 1;
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localparam ZFH_SUPPORTED = 1;
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localparam ZFA_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 0;
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localparam ZICBOM_SUPPORTED = 0;
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localparam ZICBOM_SUPPORTED = 0;
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localparam ZICBOZ_SUPPORTED = 0;
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localparam ZICBOZ_SUPPORTED = 0;
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@ -41,6 +41,7 @@ localparam COUNTERS = 12'd32;
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localparam ZICNTR_SUPPORTED = 1;
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localparam ZICNTR_SUPPORTED = 1;
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localparam ZIHPM_SUPPORTED = 1;
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localparam ZIHPM_SUPPORTED = 1;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFA_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 1;
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localparam SSTC_SUPPORTED = 1;
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localparam ZICBOM_SUPPORTED = 1;
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localparam ZICBOM_SUPPORTED = 1;
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localparam ZICBOZ_SUPPORTED = 1;
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localparam ZICBOZ_SUPPORTED = 1;
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@ -41,6 +41,7 @@ localparam COUNTERS = 0;
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localparam ZICNTR_SUPPORTED = 0;
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localparam ZICNTR_SUPPORTED = 0;
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localparam ZIHPM_SUPPORTED = 0;
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localparam ZIHPM_SUPPORTED = 0;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFA_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 0;
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localparam ZICBOM_SUPPORTED = 0;
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localparam ZICBOM_SUPPORTED = 0;
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localparam ZICBOZ_SUPPORTED = 0;
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localparam ZICBOZ_SUPPORTED = 0;
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@ -14,6 +14,7 @@ localparam cvw_t P = '{
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ZICNTR_SUPPORTED : ZICNTR_SUPPORTED,
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ZICNTR_SUPPORTED : ZICNTR_SUPPORTED,
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ZIHPM_SUPPORTED : ZIHPM_SUPPORTED,
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ZIHPM_SUPPORTED : ZIHPM_SUPPORTED,
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ZFH_SUPPORTED : ZFH_SUPPORTED,
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ZFH_SUPPORTED : ZFH_SUPPORTED,
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ZFA_SUPPORTED : ZFA_SUPPORTED,
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SSTC_SUPPORTED : SSTC_SUPPORTED,
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SSTC_SUPPORTED : SSTC_SUPPORTED,
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VIRTMEM_SUPPORTED : VIRTMEM_SUPPORTED,
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VIRTMEM_SUPPORTED : VIRTMEM_SUPPORTED,
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VECTORED_INTERRUPTS_SUPPORTED : VECTORED_INTERRUPTS_SUPPORTED,
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VECTORED_INTERRUPTS_SUPPORTED : VECTORED_INTERRUPTS_SUPPORTED,
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@ -49,6 +49,7 @@ typedef struct packed {
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logic ZICNTR_SUPPORTED;
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logic ZICNTR_SUPPORTED;
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logic ZIHPM_SUPPORTED;
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logic ZIHPM_SUPPORTED;
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logic ZFH_SUPPORTED;
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logic ZFH_SUPPORTED;
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logic ZFA_SUPPORTED;
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logic SSTC_SUPPORTED;
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logic SSTC_SUPPORTED;
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logic VIRTMEM_SUPPORTED;
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logic VIRTMEM_SUPPORTED;
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logic VECTORED_INTERRUPTS_SUPPORTED;
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logic VECTORED_INTERRUPTS_SUPPORTED;
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@ -263,15 +263,17 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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.ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE),
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.ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE),
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.ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE));
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.ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE));
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// NaN Box SrcA to convert integer to requested FP size
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// NaN Box SrcA to convert integer to requested FP size for fmv int->fp
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if(P.FPSIZES == 1) assign AlignedSrcAE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE};
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if(P.FPSIZES == 1) assign AlignedSrcAE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE};
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else if(P.FPSIZES == 2)
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else if(P.FPSIZES == 2)
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mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE);
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mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE);
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else if(P.FPSIZES == 3 | P.FPSIZES == 4)
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else if(P.FPSIZES == 3 | P.FPSIZES == 4) begin
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localparam XD_LEN = P.D_LEN < P.XLEN ? P.D_LEN : P.XLEN; // shorter of D_LEN and XLEN
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mux4 #(P.FLEN) SrcAMux ({{P.FLEN-P.S_LEN{1'b1}}, ForwardedSrcAE[P.S_LEN-1:0]},
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mux4 #(P.FLEN) SrcAMux ({{P.FLEN-P.S_LEN{1'b1}}, ForwardedSrcAE[P.S_LEN-1:0]},
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{{P.FLEN-P.D_LEN{1'b1}}, ForwardedSrcAE[P.D_LEN-1:0]},
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{{P.FLEN-XD_LEN{1'b1}}, ForwardedSrcAE[XD_LEN-1:0]},
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{{P.FLEN-P.H_LEN{1'b1}}, ForwardedSrcAE[P.H_LEN-1:0]},
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{{P.FLEN-P.H_LEN{1'b1}}, ForwardedSrcAE[P.H_LEN-1:0]},
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{{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); // NaN boxing zeroes
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{{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); // NaN boxing zeroes
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end
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// select a result that may be written to the FP register
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// select a result that may be written to the FP register
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mux3 #(P.FLEN) FResMux(SgnResE, AlignedSrcAE, CmpFpResE, {OpCtrlE[2], &OpCtrlE[1:0]}, PreFpResE);
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mux3 #(P.FLEN) FResMux(SgnResE, AlignedSrcAE, CmpFpResE, {OpCtrlE[2], &OpCtrlE[1:0]}, PreFpResE);
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@ -282,20 +284,20 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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assign mvsgn = XE[P.FLEN-1];
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assign mvsgn = XE[P.FLEN-1];
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assign SgnExtXE = XE;
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assign SgnExtXE = XE;
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end else if(P.FPSIZES == 2) begin
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end else if(P.FPSIZES == 2) begin
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mux2 #(1) sgnmux (XE[P.LEN1-1], XE[P.FLEN-1],FmtE, mvsgn);
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mux2 #(1) sgnmux (XE[P.LEN1-1], XE[P.FLEN-1],FmtE, mvsgn);
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mux2 #(P.FLEN) sgnextmux ({{P.FLEN-P.LEN1{mvsgn}}, XE[P.LEN1-1:0]}, XE, FmtE, SgnExtXE);
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mux2 #(P.FLEN) sgnextmux ({{P.FLEN-P.LEN1{mvsgn}}, XE[P.LEN1-1:0]}, XE, FmtE, SgnExtXE);
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end else if(P.FPSIZES == 3 | P.FPSIZES == 4) begin
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end else if(P.FPSIZES == 3 | P.FPSIZES == 4) begin
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mux4 #(1) sgnmux (XE[P.H_LEN-1], XE[P.S_LEN-1], XE[P.D_LEN-1], XE[P.LLEN-1], FmtE, mvsgn);
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mux4 #(1) sgnmux (XE[P.S_LEN-1], XE[P.D_LEN-1], XE[P.H_LEN-1], XE[P.LLEN-1], FmtE, mvsgn);
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mux4 #(P.FLEN) fmulzeromux ({{P.FLEN-P.H_LEN{mvsgn}}, XE[P.H_LEN-1:0]},
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mux4 #(P.FLEN) sgnextmux ({{P.FLEN-P.S_LEN{mvsgn}}, XE[P.S_LEN-1:0]},
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{{P.FLEN-P.S_LEN{mvsgn}}, XE[P.S_LEN-1:0]},
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{{P.FLEN-P.D_LEN{mvsgn}}, XE[P.D_LEN-1:0]},
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{{P.FLEN-P.D_LEN{mvsgn}}, XE[P.D_LEN-1:0]},
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{{P.FLEN-P.H_LEN{mvsgn}}, XE[P.H_LEN-1:0]},
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XE, FmtE, SgnExtXE);
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XE, FmtE, SgnExtXE);
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end
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end
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if (P.FLEN>P.XLEN)
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if (P.FLEN>P.XLEN)
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assign IntSrcXE = SgnExtXE[P.XLEN-1:0];
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assign IntSrcXE = SgnExtXE[P.XLEN-1:0];
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else
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else
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assign IntSrcXE = {{P.XLEN-P.FLEN{mvsgn}}, SgnExtXE};
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assign IntSrcXE = {{P.XLEN-P.FLEN{mvsgn}}, SgnExtXE};
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mux3 #(P.XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE);
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mux3 #(P.XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE);
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// E/M pipe registers
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// E/M pipe registers
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@ -232,95 +232,7 @@ module instrNameDecTB(
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10'b1000111_???: name = "FMSUB";
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10'b1000111_???: name = "FMSUB";
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10'b1001011_???: name = "FNMSUB";
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10'b1001011_???: name = "FNMSUB";
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10'b1001111_???: name = "FNMADD";
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10'b1001111_???: name = "FNMADD";
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10'b1010011_000: if (funct7[6:2] == 5'b00000) name = "FADD";
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else if (funct7[6:2] == 5'b00001) name = "FSUB";
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else if (funct7[6:2] == 5'b00010) name = "FMUL";
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else if (funct7[6:2] == 5'b00011) name = "FDIV";
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else if (funct7[6:2] == 5'b01011) name = "FSQRT";
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else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
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else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
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else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
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else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
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else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
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else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
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else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
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else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
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else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
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else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
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else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
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else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
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else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
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else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
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else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
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else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
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else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
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else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
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else if (funct7 == 7'b1110000 & rs2 == 5'b00000) name = "FMV.X.W";
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else if (funct7 == 7'b1111000 & rs2 == 5'b00000) name = "FMV.W.X";
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else if (funct7 == 7'b1110001 & rs2 == 5'b00000) name = "FMV.X.D"; // DOUBLE
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else if (funct7 == 7'b1111001 & rs2 == 5'b00000) name = "FMV.D.X"; // DOUBLE
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else if (funct7[6:2] == 5'b00100) name = "FSGNJ";
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else if (funct7[6:2] == 5'b00101) name = "FMIN";
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else if (funct7[6:2] == 5'b10100) name = "FLE";
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else name = "ILLEGAL";
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10'b1010011_001: if (funct7[6:2] == 5'b00000) name = "FADD";
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else if (funct7[6:2] == 5'b00001) name = "FSUB";
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else if (funct7[6:2] == 5'b00010) name = "FMUL";
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else if (funct7[6:2] == 5'b00011) name = "FDIV";
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else if (funct7[6:2] == 5'b01011) name = "FSQRT";
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else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
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else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
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else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
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else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
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else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
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else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
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else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
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else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
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else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
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else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
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else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
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else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
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else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
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else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
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else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
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else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
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else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
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|
||||||
else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
|
|
||||||
else if (funct7[6:2] == 5'b00100) name = "FSGNJN";
|
|
||||||
else if (funct7[6:2] == 5'b00101) name = "FMAX";
|
|
||||||
else if (funct7[6:2] == 5'b10100) name = "FLT";
|
|
||||||
else if (funct7[6:2] == 5'b11100) name = "FCLASS";
|
|
||||||
else name = "ILLEGAL";
|
|
||||||
10'b1010011_010: if (funct7[6:2] == 5'b00000) name = "FADD";
|
|
||||||
else if (funct7[6:2] == 5'b00001) name = "FSUB";
|
|
||||||
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
|
||||||
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
|
||||||
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
|
|
||||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
|
|
||||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
|
|
||||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
|
|
||||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
|
|
||||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
|
|
||||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
|
|
||||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
|
|
||||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
|
|
||||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
|
|
||||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
|
|
||||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
|
|
||||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
|
|
||||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
|
|
||||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
|
|
||||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
|
|
||||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
|
|
||||||
else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
|
|
||||||
else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
|
|
||||||
else if (funct7[6:2] == 5'b00100) name = "FSGNJX";
|
|
||||||
else if (funct7[6:2] == 5'b10100) name = "FEQ";
|
|
||||||
else name = "ILLEGAL";
|
|
||||||
/* verilator lint_off CASEOVERLAP */
|
|
||||||
// *** RT: definitely take a look at this. This overlaps with 10'b1010011_000
|
|
||||||
10'b1010011_???: if (funct7[6:2] == 5'b00000) name = "FADD";
|
10'b1010011_???: if (funct7[6:2] == 5'b00000) name = "FADD";
|
||||||
/* verilator lint_on CASEOVERLAP */
|
|
||||||
else if (funct7[6:2] == 5'b00001) name = "FSUB";
|
else if (funct7[6:2] == 5'b00001) name = "FSUB";
|
||||||
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
||||||
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
||||||
@ -343,6 +255,49 @@ module instrNameDecTB(
|
|||||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
|
else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
|
||||||
else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
|
else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
|
||||||
else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
|
else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
|
||||||
|
else if (funct7 == 7'b1100010 & rs2 == 5'b00000) name = "FCVT.W.H";
|
||||||
|
else if (funct7 == 7'b1100010 & rs2 == 5'b00001) name = "FCVT.WU.H";
|
||||||
|
else if (funct7 == 7'b1100010 & rs2 == 5'b00010) name = "FCVT.L.H";
|
||||||
|
else if (funct7 == 7'b1100010 & rs2 == 5'b00011) name = "FCVT.LU.H";
|
||||||
|
else if (funct7 == 7'b1101010 & rs2 == 5'b00000) name = "FCVT.H.W";
|
||||||
|
else if (funct7 == 7'b1101010 & rs2 == 5'b00001) name = "FCVT.H.WU";
|
||||||
|
else if (funct7 == 7'b1101010 & rs2 == 5'b00010) name = "FCVT.H.L";
|
||||||
|
else if (funct7 == 7'b1101010 & rs2 == 5'b00011) name = "FCVT.H.LU";
|
||||||
|
else if (funct7 == 7'b1100011 & rs2 == 5'b00000) name = "FCVT.W.Q";
|
||||||
|
else if (funct7 == 7'b1100011 & rs2 == 5'b00001) name = "FCVT.WU.Q";
|
||||||
|
else if (funct7 == 7'b1100011 & rs2 == 5'b00010) name = "FCVT.L.Q";
|
||||||
|
else if (funct7 == 7'b1100011 & rs2 == 5'b00011) name = "FCVT.LU.Q";
|
||||||
|
else if (funct7 == 7'b1101011 & rs2 == 5'b00000) name = "FCVT.Q.W";
|
||||||
|
else if (funct7 == 7'b1101011 & rs2 == 5'b00001) name = "FCVT.Q.WU";
|
||||||
|
else if (funct7 == 7'b1101011 & rs2 == 5'b00010) name = "FCVT.Q.L";
|
||||||
|
else if (funct7 == 7'b1101011 & rs2 == 5'b00011) name = "FCVT.Q.LU";
|
||||||
|
else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
|
||||||
|
else if (funct7 == 7'b0100000 & rs2 == 5'b00010) name = "FCVT.S.H";
|
||||||
|
else if (funct7 == 7'b0100000 & rs2 == 5'b00011) name = "FCVT.S.Q";
|
||||||
|
else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
|
||||||
|
else if (funct7 == 7'b0100001 & rs2 == 5'b00010) name = "FCVT.D.H";
|
||||||
|
else if (funct7 == 7'b0100001 & rs2 == 5'b00011) name = "FCVT.D.Q";
|
||||||
|
else if (funct7 == 7'b0100010 & rs2 == 5'b00000) name = "FCVT.H.S";
|
||||||
|
else if (funct7 == 7'b0100010 & rs2 == 5'b00001) name = "FCVT.H.D";
|
||||||
|
else if (funct7 == 7'b0100010 & rs2 == 5'b00011) name = "FCVT.H.Q";
|
||||||
|
else if (funct7 == 7'b0100011 & rs2 == 5'b00000) name = "FCVT.Q.S";
|
||||||
|
else if (funct7 == 7'b0100011 & rs2 == 5'b00001) name = "FCVT.Q.D";
|
||||||
|
else if (funct7 == 7'b0100011 & rs2 == 5'b00010) name = "FCVT.Q.H";
|
||||||
|
else if (funct7 == 7'b1110000 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.X.W";
|
||||||
|
else if (funct7 == 7'b1111000 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.W.X";
|
||||||
|
else if (funct7 == 7'b1110001 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.X.D";
|
||||||
|
else if (funct7 == 7'b1111001 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.D.X";
|
||||||
|
else if (funct7 == 7'b1110010 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.X.H";
|
||||||
|
else if (funct7 == 7'b1111010 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.H.X";
|
||||||
|
else if (funct7[6:2] == 5'b00100 & funct3 == 3'b000) name = "FSGNJ";
|
||||||
|
else if (funct7[6:2] == 5'b00101 & funct3 == 3'b000) name = "FMIN";
|
||||||
|
else if (funct7[6:2] == 5'b10100 & funct3 == 3'b000) name = "FLE";
|
||||||
|
else if (funct7[6:2] == 5'b00100 & funct3 == 3'b001) name = "FSGNJN";
|
||||||
|
else if (funct7[6:2] == 5'b00101 & funct3 == 3'b001) name = "FMAX";
|
||||||
|
else if (funct7[6:2] == 5'b10100 & funct3 == 3'b001) name = "FLT";
|
||||||
|
else if (funct7[6:2] == 5'b11100 & funct3 == 3'b001) name = "FCLASS";
|
||||||
|
else if (funct7[6:2] == 5'b00100 & funct3 == 3'b010) name = "FSGNJX";
|
||||||
|
else if (funct7[6:2] == 5'b10100 & funct3 == 3'b010) name = "FEQ";
|
||||||
else name = "ILLEGAL";
|
else name = "ILLEGAL";
|
||||||
10'b0000111_010: name = "FLW";
|
10'b0000111_010: name = "FLW";
|
||||||
10'b0100111_010: name = "FSW";
|
10'b0100111_010: name = "FSW";
|
||||||
|
|||||||
@ -127,6 +127,8 @@ module testbench;
|
|||||||
"arch64zbs": if (P.ZBS_SUPPORTED) tests = arch64zbs;
|
"arch64zbs": if (P.ZBS_SUPPORTED) tests = arch64zbs;
|
||||||
"arch64zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch64zicboz;
|
"arch64zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch64zicboz;
|
||||||
"arch64zcb": if (P.ZCB_SUPPORTED) tests = arch64zcb;
|
"arch64zcb": if (P.ZCB_SUPPORTED) tests = arch64zcb;
|
||||||
|
"arch64zfh": if (P.ZFH_SUPPORTED) tests = arch64zfh;
|
||||||
|
// "arch64zfa": if (P.ZFA_SUPPORTED) tests = arch64zfa;
|
||||||
endcase
|
endcase
|
||||||
end else begin // RV32
|
end else begin // RV32
|
||||||
case (TEST)
|
case (TEST)
|
||||||
@ -161,6 +163,8 @@ module testbench;
|
|||||||
"arch32zbs": if (P.ZBS_SUPPORTED) tests = arch32zbs;
|
"arch32zbs": if (P.ZBS_SUPPORTED) tests = arch32zbs;
|
||||||
"arch32zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch32zicboz;
|
"arch32zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch32zicboz;
|
||||||
"arch32zcb": if (P.ZCB_SUPPORTED) tests = arch32zcb;
|
"arch32zcb": if (P.ZCB_SUPPORTED) tests = arch32zcb;
|
||||||
|
"arch32zfh": if (P.ZFH_SUPPORTED) tests = arch32zfh;
|
||||||
|
"arch32zfaf": if (P.ZFA_SUPPORTED) tests = arch32zfaf;
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
if (tests.size() == 0) begin
|
if (tests.size() == 0) begin
|
||||||
|
|||||||
@ -1291,6 +1291,172 @@ string imperas32f[] = '{
|
|||||||
"rv64i_m/F/src/fsw-align-01.S"
|
"rv64i_m/F/src/fsw-align-01.S"
|
||||||
};
|
};
|
||||||
|
|
||||||
|
string arch64zfh[] = '{
|
||||||
|
`RISCVARCHTEST,
|
||||||
|
"rv64i_m/Zfh/src/fmv.x.h_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fadd_b10-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fadd_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fadd_b11-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fadd_b12-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fadd_b13-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fadd_b2-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fadd_b3-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fadd_b4-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fadd_b5-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fadd_b7-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fadd_b8-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fclass_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.h.w_b25-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.h.w_b26-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.h.wu_b25-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.h.wu_b26-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.w.h_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.w.h_b22-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.w.h_b23-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.w.h_b24-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.w.h_b27-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.w.h_b28-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.w.h_b29-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.wu.h_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.wu.h_b22-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.wu.h_b23-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.wu.h_b24-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.wu.h_b27-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.wu.h_b28-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.wu.h_b29-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.h.l_b25-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.h.l_b26-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.h.lu_b26-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.l.h_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.l.h_b22-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.l.h_b23-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.l.h_b24-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.l.h_b27-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.l.h_b28-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.l.h_b29-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.lu.h_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.lu.h_b22-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.lu.h_b23-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.lu.h_b24-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.lu.h_b27-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.lu.h_b28-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fcvt.lu.h_b29-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fdiv_b20-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fdiv_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fdiv_b2-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fdiv_b21-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fdiv_b3-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fdiv_b4-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fdiv_b5-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fdiv_b6-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fdiv_b7-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fdiv_b8-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fdiv_b9-01.S",
|
||||||
|
"rv64i_m/Zfh/src/feq_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/feq_b19-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fle_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fle_b19-01.S",
|
||||||
|
"rv64i_m/Zfh/src/flt_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/flt_b19-01.S",
|
||||||
|
"rv64i_m/Zfh/src/flh-align-01.S",
|
||||||
|
/* "rv64i_m/Zfh/src/fmadd_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmadd_b14-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmadd_b16-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmadd_b17-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmadd_b18-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmadd_b2-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmadd_b3-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmadd_b4-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmadd_b5-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmadd_b6-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmadd_b7-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmadd_b8-01.S", */
|
||||||
|
"rv64i_m/Zfh/src/fmax_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmax_b19-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmin_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmin_b19-01.S",
|
||||||
|
/* "rv64i_m/Zfh/src/fmsub_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmsub_b14-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmsub_b16-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmsub_b17-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmsub_b18-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmsub_b2-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmsub_b3-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmsub_b4-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmsub_b5-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmsub_b6-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmsub_b7-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmsub_b8-01.S", */
|
||||||
|
"rv64i_m/Zfh/src/fmul_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmul_b2-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmul_b3-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmul_b4-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmul_b5-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmul_b6-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmul_b7-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmul_b8-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmul_b9-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmv.h.x_b25-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmv.h.x_b26-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmv.x.h_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmv.x.h_b22-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmv.x.h_b23-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmv.x.h_b24-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmv.x.h_b27-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmv.x.h_b28-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fmv.x.h_b29-01.S",
|
||||||
|
/* "rv64i_m/Zfh/src/fnmadd_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmadd_b14-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmadd_b16-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmadd_b17-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmadd_b18-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmadd_b2-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmadd_b3-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmadd_b4-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmadd_b5-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmadd_b6-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmadd_b7-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmadd_b8-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmsub_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmsub_b14-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmsub_b16-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmsub_b17-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmsub_b18-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmsub_b2-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmsub_b3-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmsub_b4-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmsub_b5-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmsub_b6-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmsub_b7-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fnmsub_b8-01.S", */
|
||||||
|
"rv64i_m/Zfh/src/fsgnj_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsgnjn_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsgnjx_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsqrt_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsqrt_b20-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsqrt_b2-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsqrt_b3-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsqrt_b4-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsqrt_b5-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsqrt_b7-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsqrt_b8-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsqrt_b9-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsub_b10-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsub_b1-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsub_b11-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsub_b12-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsub_b13-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsub_b2-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsub_b3-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsub_b4-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsub_b5-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsub_b7-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsub_b8-01.S",
|
||||||
|
"rv64i_m/Zfh/src/fsh-align-01.S"
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
string arch64d_fma[] = '{
|
string arch64d_fma[] = '{
|
||||||
`RISCVARCHTEST,
|
`RISCVARCHTEST,
|
||||||
//"rv64i_m/D/src/fmadd.d_b15-01.S",
|
//"rv64i_m/D/src/fmadd.d_b15-01.S",
|
||||||
@ -1638,7 +1804,6 @@ string arch64zbs[] = '{
|
|||||||
|
|
||||||
string arch32f[] = '{
|
string arch32f[] = '{
|
||||||
`RISCVARCHTEST,
|
`RISCVARCHTEST,
|
||||||
"rv32i_m/F/src/fdiv_b20-01.S",
|
|
||||||
"rv32i_m/F/src/fadd_b10-01.S",
|
"rv32i_m/F/src/fadd_b10-01.S",
|
||||||
"rv32i_m/F/src/fadd_b1-01.S",
|
"rv32i_m/F/src/fadd_b1-01.S",
|
||||||
"rv32i_m/F/src/fadd_b11-01.S",
|
"rv32i_m/F/src/fadd_b11-01.S",
|
||||||
@ -1783,6 +1948,166 @@ string arch64zbs[] = '{
|
|||||||
"rv32i_m/F/src/fsw-align-01.S"
|
"rv32i_m/F/src/fsw-align-01.S"
|
||||||
};
|
};
|
||||||
|
|
||||||
|
string arch32zfh[] = '{
|
||||||
|
`RISCVARCHTEST,
|
||||||
|
"rv32i_m/Zfh/src/fadd_b10-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fadd_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fadd_b11-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fadd_b12-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fadd_b13-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fadd_b2-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fadd_b3-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fadd_b4-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fadd_b5-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fadd_b7-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fadd_b8-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fclass_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fcvt.h.w_b25-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fcvt.h.w_b26-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fcvt.h.wu_b25-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fcvt.h.wu_b26-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fcvt.w.h_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fcvt.w.h_b22-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fcvt.w.h_b23-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fcvt.w.h_b24-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fcvt.w.h_b27-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fcvt.w.h_b28-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fcvt.w.h_b29-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fcvt.wu.h_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fcvt.wu.h_b22-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fcvt.wu.h_b23-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fcvt.wu.h_b24-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fcvt.wu.h_b27-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fcvt.wu.h_b28-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fcvt.wu.h_b29-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fdiv_b20-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fdiv_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fdiv_b2-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fdiv_b21-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fdiv_b3-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fdiv_b4-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fdiv_b5-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fdiv_b6-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fdiv_b7-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fdiv_b8-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fdiv_b9-01.S",
|
||||||
|
"rv32i_m/Zfh/src/feq_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/feq_b19-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fle_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fle_b19-01.S",
|
||||||
|
"rv32i_m/Zfh/src/flt_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/flt_b19-01.S",
|
||||||
|
"rv32i_m/Zfh/src/flh-align-01.S",
|
||||||
|
/* "rv32i_m/Zfh/src/fmadd_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmadd_b14-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmadd_b16-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmadd_b17-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmadd_b18-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmadd_b2-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmadd_b3-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmadd_b4-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmadd_b5-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmadd_b6-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmadd_b7-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmadd_b8-01.S", */
|
||||||
|
"rv32i_m/Zfh/src/fmax_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmax_b19-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmin_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmin_b19-01.S",
|
||||||
|
/* "rv32i_m/Zfh/src/fmsub_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmsub_b14-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmsub_b16-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmsub_b17-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmsub_b18-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmsub_b2-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmsub_b3-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmsub_b4-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmsub_b5-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmsub_b6-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmsub_b7-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmsub_b8-01.S", */
|
||||||
|
"rv32i_m/Zfh/src/fmul_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmul_b2-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmul_b3-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmul_b4-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmul_b5-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmul_b6-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmul_b7-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmul_b8-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmul_b9-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmv.h.x_b25-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmv.h.x_b26-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmv.x.h_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmv.x.h_b22-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmv.x.h_b23-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmv.x.h_b24-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmv.x.h_b27-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmv.x.h_b28-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fmv.x.h_b29-01.S",
|
||||||
|
/* "rv32i_m/Zfh/src/fnmadd_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmadd_b14-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmadd_b16-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmadd_b17-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmadd_b18-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmadd_b2-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmadd_b3-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmadd_b4-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmadd_b5-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmadd_b6-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmadd_b7-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmadd_b8-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmsub_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmsub_b14-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmsub_b16-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmsub_b17-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmsub_b18-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmsub_b2-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmsub_b3-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmsub_b4-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmsub_b5-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmsub_b6-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmsub_b7-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fnmsub_b8-01.S", */
|
||||||
|
"rv32i_m/Zfh/src/fsgnj_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsgnjn_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsgnjx_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsqrt_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsqrt_b20-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsqrt_b2-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsqrt_b3-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsqrt_b4-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsqrt_b5-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsqrt_b7-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsqrt_b8-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsqrt_b9-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsub_b10-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsub_b1-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsub_b11-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsub_b12-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsub_b13-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsub_b2-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsub_b3-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsub_b4-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsub_b5-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsub_b7-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsub_b8-01.S",
|
||||||
|
"rv32i_m/Zfh/src/fsh-align-01.S"
|
||||||
|
};
|
||||||
|
|
||||||
|
string arch32zfaf[] = '{
|
||||||
|
`RISCVARCHTEST,
|
||||||
|
"rv32i_m/F_Zfa/src/fle_b1-01.S",
|
||||||
|
"rv32i_m/F_Zfa/src/fle_b19-01.S",
|
||||||
|
"rv32i_m/F_Zfa/src/fli_b1-01.S",
|
||||||
|
"rv32i_m/F_Zfa/src/fltq_b1-01.S",
|
||||||
|
"rv32i_m/F_Zfa/src/fltq_b19-01.S",
|
||||||
|
"rv32i_m/F_Zfa/src/fmin_b1-01.S",
|
||||||
|
"rv32i_m/F_Zfa/src/fmin_b19-01.S",
|
||||||
|
"rv32i_m/F_Zfa/src/fmax_b1-01.S",
|
||||||
|
"rv32i_m/F_Zfa/src/fmax_b19-01.S",
|
||||||
|
"rv32i_m/F_Zfa/src/fround_b1-01.S"
|
||||||
|
};
|
||||||
|
|
||||||
string arch32d_fma[] = '{
|
string arch32d_fma[] = '{
|
||||||
`RISCVARCHTEST,
|
`RISCVARCHTEST,
|
||||||
//"rv32i_m/D/src/fmadd.d_b15-01.S",
|
//"rv32i_m/D/src/fmadd.d_b15-01.S",
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user