mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge conflict in coverage.svh
This commit is contained in:
David Harris
commit
da2310fb3e
18
.github/workflows/install.yml
vendored
18
.github/workflows/install.yml
vendored
@ -67,6 +67,12 @@ jobs:
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|||||||
os: ubuntu-latest
|
os: ubuntu-latest
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||||||
image: null
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image: null
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||||||
riscv_path: /home/riscv
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riscv_path: /home/riscv
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||||||
|
# Custom location user level installation
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||||||
|
- name: custom-user-install
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||||||
|
os: ubuntu-latest
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||||||
|
image: null
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||||||
|
user: true
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||||||
|
riscv_path: $HOME/riscv-toolchain
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||||||
|
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||||||
# run on selected version of ubuntu or on ubuntu-latest with docker image
|
# run on selected version of ubuntu or on ubuntu-latest with docker image
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||||||
runs-on: ${{ matrix.os }}
|
runs-on: ${{ matrix.os }}
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||||||
@ -108,6 +114,7 @@ jobs:
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fi
|
fi
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||||||
# Set environment variables for the rest of the job
|
# Set environment variables for the rest of the job
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||||||
- name: Set Environment Variables
|
- name: Set Environment Variables
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||||||
|
if: always()
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||||||
run: |
|
run: |
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||||||
if [ ! -z ${{ matrix.riscv_path }} ]; then
|
if [ ! -z ${{ matrix.riscv_path }} ]; then
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sed -i 's,exit 1,export RISCV=${{ matrix.riscv_path }},g' setup.sh
|
sed -i 's,exit 1,export RISCV=${{ matrix.riscv_path }},g' setup.sh
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@ -121,11 +128,11 @@ jobs:
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with:
|
with:
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||||||
name: installation-logs-${{ matrix.name }}
|
name: installation-logs-${{ matrix.name }}
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path: ${{ env.RISCV }}/logs/
|
path: ${{ env.RISCV }}/logs/
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||||||
# Make riscof only as that is the only testsuite used by standard regression
|
# Make riscof and zsbl only as that is the only testsuite used by standard regression
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||||||
- name: make tests
|
- name: make tests
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||||||
run: |
|
run: |
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||||||
source setup.sh
|
source setup.sh
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make riscof --jobs $(nproc --ignore 1)
|
make riscof zsbl --jobs $(nproc --ignore 1)
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||||||
# Only the linux-testvectors are needed, so remove the rest of the buildroot to save space
|
# Only the linux-testvectors are needed, so remove the rest of the buildroot to save space
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- name: Remove Buildroot to Save Space
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- name: Remove Buildroot to Save Space
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||||||
run: |
|
run: |
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||||||
@ -137,6 +144,13 @@ jobs:
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|||||||
run: |
|
run: |
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||||||
source setup.sh
|
source setup.sh
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||||||
regression-wally
|
regression-wally
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||||||
|
- name: Lint + wsim Test Only (for distros with broken Verilator sim)
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||||||
|
if: ${{ matrix.name == 'ubuntu-20.04' || matrix.name == 'rocky-8' || matrix.name == 'almalinux-8'}}
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||||||
|
run: |
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||||||
|
source setup.sh
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|
mkdir -p $WALLY/sim/verilator/logs/
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||||||
|
lint-wally
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||||||
|
wsim rv32i arch32i --sim verilator | tee $WALLY/sim/verilator/logs/rv32i_arch32i.log
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# Upload regression logs for debugging
|
# Upload regression logs for debugging
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||||||
- name: Upload regression logs
|
- name: Upload regression logs
|
||||||
uses: actions/upload-artifact@v4
|
uses: actions/upload-artifact@v4
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||||||
|
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206
README.md
206
README.md
@ -1,3 +1,5 @@
|
|||||||
|
|
||||||
|
|
||||||
# core-v-wally
|
# core-v-wally
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||||||
|
|
||||||
Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, including RV32/64, A, B, C, D, F, M, Q, and Zk* extensions, virtual memory, PMP, and the various privileged modes and CSRs. It provides optional caches, branch prediction, and standard RISC-V peripherals (CLINT, PLIC, UART, GPIO). Wally is written in SystemVerilog. It passes the [RISC-V Arch Tests](https://github.com/riscv-non-isa/riscv-arch-test) and boots Linux on an FPGA. Configurations range from a minimal RV32E core to a fully featured RV64GC application processor with all of the RVA22S64 profile extensions. Wally is part of the OpenHWGroup family of robust open RISC-V cores.
|
Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, including RV32/64, A, B, C, D, F, M, Q, and Zk* extensions, virtual memory, PMP, and the various privileged modes and CSRs. It provides optional caches, branch prediction, and standard RISC-V peripherals (CLINT, PLIC, UART, GPIO). Wally is written in SystemVerilog. It passes the [RISC-V Arch Tests](https://github.com/riscv-non-isa/riscv-arch-test) and boots Linux on an FPGA. Configurations range from a minimal RV32E core to a fully featured RV64GC application processor with all of the RVA22S64 profile extensions. Wally is part of the OpenHWGroup family of robust open RISC-V cores.
|
||||||
@ -14,58 +16,66 @@ Wally is presently at Technology Readiness Level 4, passing the RISC-V compatibi
|
|||||||
|
|
||||||
New users may wish to do the following setup to access the server via a GUI and use a text editor.
|
New users may wish to do the following setup to access the server via a GUI and use a text editor.
|
||||||
|
|
||||||
Git started with Git configuration and authentication: B.1 (replace with your name and email)
|
- Git started with Git configuration and authentication: C.1 (replace with your name and email)
|
||||||
$ git config --global user.name "Ben Bitdiddle"
|
```bash
|
||||||
$ git config --global user.email "ben_bitdiddle@wally.edu"
|
$ git config --global user.name "Ben Bitdiddle"
|
||||||
$ git config --global pull.rebase false
|
$ git config --global user.email "ben_bitdiddle@wally.edu"
|
||||||
Optional: Download and install x2go - A.1.1
|
$ git config --global pull.rebase false
|
||||||
Optional: Download and install VSCode - A.4.2
|
```
|
||||||
Optional: Make sure you can log into your server via x2go and via a terminal
|
- Optional: Download and install x2go - B.1.1
|
||||||
Terminal on Mac, cmd on Windows, xterm on Linux
|
- Optional: Download and install VSCode - B.4.2
|
||||||
See A.1 about ssh -Y login from a terminal
|
- Optional: Make sure you can log into your server via x2go and via a terminal
|
||||||
|
- Terminal on Mac, cmd on Windows, xterm on Linux
|
||||||
|
- See B.1 about ssh -Y login from a terminal
|
||||||
|
|
||||||
Then fork and clone the repo, source setup, make the tests and run regression
|
Then fork and clone the repo, source setup, make the tests and run regression
|
||||||
|
|
||||||
If you don't already have a Github account, create one
|
1. If you don't already have a Github account, create one
|
||||||
In a web browser, visit https://github.com/openhwgroup/cvw
|
2. In a web browser, visit https://github.com/openhwgroup/cvw
|
||||||
In the upper right part of the screen, click on Fork
|
3. In the upper right part of the screen, click on Fork
|
||||||
Create a fork, choosing the owner as your github account
|
4. Create a fork, choosing the owner as your github account and the repository as cvw.
|
||||||
and the repository as cvw.
|
5. On the Linux computer where you will be working, log in.
|
||||||
|
6. Clone your fork of the repo. Change `<yourgithubid>` to your github id.
|
||||||
On the Linux computer where you will be working, log in
|
```bash
|
||||||
|
|
||||||
Clone your fork of the repo. Change `<yourgithubid>` to your github id.
|
|
||||||
|
|
||||||
$ git clone --recurse-submodules https://github.com/<yourgithubid>/cvw
|
$ git clone --recurse-submodules https://github.com/<yourgithubid>/cvw
|
||||||
$ cd cvw
|
$ cd cvw
|
||||||
$ git remote add upstream https://github.com/openhwgroup/cvw
|
$ git remote add upstream https://github.com/openhwgroup/cvw
|
||||||
|
```
|
||||||
|
|
||||||
If you are installing on a new system without any tools installed, please jump to the next section, Toolchain Installation then come back here.
|
> [!NOTE]
|
||||||
|
> If you are installing on a new system without any tools installed, please jump to the next section, [Toolchain Installation](#toolchain-installation-and-configuration-sys-admin), then come back here.
|
||||||
|
|
||||||
Run the setup script to update your `PATH` and activate the python virtual environment.
|
7. Run the setup script to update your `PATH` and activate the python virtual environment.
|
||||||
|
|
||||||
|
```bash
|
||||||
$ source ./setup.sh
|
$ source ./setup.sh
|
||||||
|
```
|
||||||
|
|
||||||
Add the following lines to your `.bashrc` or `.bash_profile` to run the setup script each time you log in.
|
8. Add the following lines to your `.bashrc` or `.bash_profile` to run the setup script each time you log in.
|
||||||
|
|
||||||
|
```bash
|
||||||
if [ -f ~/cvw/setup.sh ]; then
|
if [ -f ~/cvw/setup.sh ]; then
|
||||||
source ~/cvw/setup.sh
|
source ~/cvw/setup.sh
|
||||||
fi
|
fi
|
||||||
|
```
|
||||||
|
|
||||||
|
9. Build the tests and run a regression simulation to prove everything is installed. Building tests may take a while.
|
||||||
|
|
||||||
Build the tests and run a regression simulation to prove everything is installed. Building tests will take a while.
|
```bash
|
||||||
|
|
||||||
$ make --jobs
|
$ make --jobs
|
||||||
$ regression-wally
|
$ regression-wally
|
||||||
|
```
|
||||||
|
|
||||||
# Toolchain Installation and Configuration (Sys Admin)
|
# Toolchain Installation and Configuration (Sys Admin)
|
||||||
|
|
||||||
This section describes the open source toolchain installation.
|
> This section describes the open source toolchain installation.
|
||||||
|
|
||||||
### Compatibility
|
### Compatibility
|
||||||
The current version of the toolchain has been tested on Ubuntu (versions 20.04 LTS, 22.04 LTS, and 24.04 LTS) and on Red Hat/Rocky/AlmaLinux (versions 8 and 9).
|
The current version of the toolchain has been tested on Ubuntu (versions 20.04 LTS, 22.04 LTS, and 24.04 LTS) and on Red Hat/Rocky/AlmaLinux (versions 8 and 9).
|
||||||
|
|
||||||
NOTE: Ubuntu 22.04LTS is incompatible with Synopsys Design Compiler.
|
> [!WARNING]
|
||||||
|
> - Ubuntu 22.04LTS is incompatible with Synopsys Design Compiler.
|
||||||
|
> - Verilator currently fails to simulate correctly on Ubuntu 20.04 LTS and Red Hat/Rocky/AlmaLinux 8.
|
||||||
|
|
||||||
### Overview
|
### Overview
|
||||||
The toolchain installation script installs the following tools:
|
The toolchain installation script installs the following tools:
|
||||||
@ -74,32 +84,37 @@ The toolchain installation script installs the following tools:
|
|||||||
- [QEMU](https://www.qemu.org/docs/master/system/target-riscv.html): emulator
|
- [QEMU](https://www.qemu.org/docs/master/system/target-riscv.html): emulator
|
||||||
- [Spike](https://github.com/riscv-software-src/riscv-isa-sim): functional RISC-V model
|
- [Spike](https://github.com/riscv-software-src/riscv-isa-sim): functional RISC-V model
|
||||||
- [Verilator](https://github.com/verilator/verilator): open-source Verilog simulator
|
- [Verilator](https://github.com/verilator/verilator): open-source Verilog simulator
|
||||||
- NOTE: Verilator does not currently work reliably for simulating Wally on Ubuntu 20.04 LTS and Red Hat 8
|
|
||||||
- [RISC-V Sail Model](https://github.com/riscv/sail-riscv): golden reference model for RISC-V
|
- [RISC-V Sail Model](https://github.com/riscv/sail-riscv): golden reference model for RISC-V
|
||||||
- [OSU Skywater 130 cell library](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12): standard cell library
|
- [OSU Skywater 130 cell library](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12): standard cell library
|
||||||
- [RISCOF](https://github.com/riscv-software-src/riscof.git): RISC-V compliance test framework
|
- [RISCOF](https://github.com/riscv-software-src/riscof.git): RISC-V compliance test framework
|
||||||
|
|
||||||
Additionally, Buildroot Linux is built for Wally and linux test-vectors are generated for simulation. See the [Linux README](linux/README.md) for more details.
|
Additionally, Buildroot Linux is built for Wally and linux test-vectors are generated for simulation. See the [Linux README](linux/README.md) for more details. This can be skipped using the `--no-buildroot` flag.
|
||||||
|
|
||||||
### Installation
|
### Installation
|
||||||
|
|
||||||
The tools can be installed by running
|
The tools can be installed by running
|
||||||
|
|
||||||
$ $WALLY/bin/wally-tool-chain-install.sh
|
```bash
|
||||||
|
$ $WALLY/bin/wally-tool-chain-install.sh
|
||||||
|
```
|
||||||
If this script is run as root or using `sudo`, it will also install all of the prerequisite packages using the system package manager. The default installation directory when run in this manner is `/opt/riscv`.
|
If this script is run as root or using `sudo`, it will also install all of the prerequisite packages using the system package manager. The default installation directory when run in this manner is `/opt/riscv`.
|
||||||
|
|
||||||
If a user-level installation is desired, the script can instead be run by any user without `sudo` and the installation directory will be `~/riscv`. In this case, the prerequisite packages must first be installed by running
|
If a user-level installation is desired, the script can instead be run by any user without `sudo` and the installation directory will be `~/riscv`. In this case, the prerequisite packages must first be installed by running
|
||||||
|
|
||||||
$ sudo $WALLY/bin/wally-package-install.sh
|
```bash
|
||||||
|
$ sudo $WALLY/bin/wally-package-install.sh
|
||||||
|
```
|
||||||
|
|
||||||
In either case, the installation directory can be overridden by passing the desired directory as the last argument to the installation script. For example,
|
In either case, the installation directory can be overridden by passing the desired directory as the last argument to the installation script. For example,
|
||||||
|
|
||||||
$ sudo $WALLY/bin/wally-tool-chain-install.sh /home/riscv
|
```bash
|
||||||
|
$ sudo $WALLY/bin/wally-tool-chain-install.sh /home/riscv
|
||||||
|
```
|
||||||
|
|
||||||
See `wally-tool-chain-install.sh` for a detailed description of each component, or to issue the commands one at a time to install on the command line.
|
See `wally-tool-chain-install.sh` for a detailed description of each component, or to issue the commands one at a time to install on the command line.
|
||||||
|
|
||||||
**NOTE:** The complete installation process requires ~55 GB of free space. If the `--clean` flag is passed as the first argument to the installation script then the final consumed space is only ~26 GB, but upgrading the tools requires reinstalling from scratch.
|
> [!NOTE]
|
||||||
|
> The complete installation process requires ~55 GB of free space. If the `--clean` flag is passed to the installation script then the final consumed space is only ~26 GB, but upgrading the tools will reinstall everything from scratch.
|
||||||
|
|
||||||
### Configuration
|
### Configuration
|
||||||
`$WALLY/setup.sh` sources `$RISCV/site-setup.sh`. If the toolchain was installed in either of the default locations (`/opt/riscv` or `~/riscv`), `$RISCV` will automatically be set to the correct path when `setup.sh` is run. If a custom installation directory was used, then `$WALLY/setup.sh` must be modified to set the correct path.
|
`$WALLY/setup.sh` sources `$RISCV/site-setup.sh`. If the toolchain was installed in either of the default locations (`/opt/riscv` or `~/riscv`), `$RISCV` will automatically be set to the correct path when `setup.sh` is run. If a custom installation directory was used, then `$WALLY/setup.sh` must be modified to set the correct path.
|
||||||
@ -108,12 +123,13 @@ See `wally-tool-chain-install.sh` for a detailed description of each component,
|
|||||||
|
|
||||||
Change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler and VCS installations and license servers. If you only have Questa or VCS, you can still simulate but cannot run logic synthesis. If Questa, VSC, or Design Compiler are already setup on this system then don't set these variables.
|
Change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler and VCS installations and license servers. If you only have Questa or VCS, you can still simulate but cannot run logic synthesis. If Questa, VSC, or Design Compiler are already setup on this system then don't set these variables.
|
||||||
|
|
||||||
export MGLS_LICENSE_FILE=.. # Change this to your Siemens license server
|
```bash
|
||||||
export SNPSLMD_LICENSE_FILE=.. # Change this to your Synopsys license server
|
export MGLS_LICENSE_FILE=.. # Change this to your Siemens license server
|
||||||
export QUESTA_HOME=.. # Change this for your path to Questa
|
export SNPSLMD_LICENSE_FILE=.. # Change this to your Synopsys license server
|
||||||
export DC_HOME=.. # Change this for your path to Synopsys Design Compiler
|
export QUESTA_HOME=.. # Change this for your path to Questa
|
||||||
export VCS_HOME=.. # Change this for your path to Synopsys VCS
|
export DC_HOME=.. # Change this for your path to Synopsys Design Compiler
|
||||||
|
export VCS_HOME=.. # Change this for your path to Synopsys VCS
|
||||||
|
```
|
||||||
|
|
||||||
# Installing EDA Tools
|
# Installing EDA Tools
|
||||||
|
|
||||||
@ -127,39 +143,48 @@ Although most EDA tools are Linux-friendly, they tend to have issues when not in
|
|||||||
|
|
||||||
### Siemens Questa
|
### Siemens Questa
|
||||||
|
|
||||||
Siemens Questa simulates behavioral, RTL and gate-level HDL. To install Siemens Questa first go to a web browser and navigate to
|
Siemens Questa simulates behavioral, RTL and gate-level HDL. To install Siemens Questa first go to a web browser and navigate to https://eda.sw.siemens.com/en-US/ic/questa/simulation/advanced-simulator/. Click Sign In and log in with your credentials and the product can easily be downloaded and installed. Some Windows-based installations also require gcc libraries that are typically provided as a compressed zip download through Siemens.
|
||||||
https://eda.sw.siemens.com/en-US/ic/questa/simulation/advanced-simulator/. Click Sign In and log in with your credentials and the product can easily be downloaded and installed. Some Windows-based installations also require gcc libraries that are typically provided as a compressed zip download through Siemens.
|
|
||||||
|
|
||||||
### Synopsys Design Compiler (DC)
|
### Synopsys Design Compiler (DC)
|
||||||
|
|
||||||
Many commercial synthesis and place and route tools require a common installer. These installers are provided by the EDA vendor and Synopsys has one called Synopsys Installer. To use Synopsys Installer, you will need to acquire a license through Synopsys that is typically Called Synopsys Common Licensing (SCL). Both the Synopsys Installer, license key file, and Design Compiler can all be downloaded through Synopsys Solvnet. First open a web browser, log into Synsopsy Solvnet, and download the installer and Design Compiler installation files. Then, install the Installer
|
Many commercial synthesis and place and route tools require a common installer. These installers are provided by the EDA vendor and Synopsys has one called Synopsys Installer. To use Synopsys Installer, you will need to acquire a license through Synopsys that is typically Called Synopsys Common Licensing (SCL). Both the Synopsys Installer, license key file, and Design Compiler can all be downloaded through Synopsys Solvnet. First open a web browser, log into Synsopsy Solvnet, and download the installer and Design Compiler installation files. Then, install the Installer.
|
||||||
|
|
||||||
$ firefox &
|
```bash
|
||||||
Navigate to https://solvnet.synopsys.com
|
$ firefox &
|
||||||
Log in with your institution’s username and password
|
```
|
||||||
Click on Downloads, then scroll down to Synopsys Installer
|
|
||||||
Select the latest version (currently 5.4). Click Download Here, agree,
|
|
||||||
Click on SynopsysInstaller_v5.4.run
|
|
||||||
Return to downloads and also get Design Compiler (synthesis) latest version, and any others you want.
|
|
||||||
Click on all parts and the .spf file, then click Download Files near the top
|
|
||||||
move the SynopsysInstaller into /cad/synopsys/Installer_5.4 with 755 permission for cad,
|
|
||||||
move other files into /cad/synopsys/downloads and work as user cad from here on
|
|
||||||
|
|
||||||
$ cd /cad/synopsys/installer_5.4
|
- Navigate to https://solvnet.synopsys.com
|
||||||
$ ./SynopsysInstaller_v5.4.run
|
- Log in with your institution’s username and password
|
||||||
Accept default installation directory
|
- Click on Downloads, then scroll down to Synopsys Installer
|
||||||
$ ./installer
|
- Select the latest version (currently 5.4). Click Download Here, agree,
|
||||||
Enter source path as /cad/synopsys/downloads, and installation path as /cad/synopsys
|
- Click on SynopsysInstaller_v5.4.run
|
||||||
When prompted, enter your site ID
|
- Return to downloads and also get Design Compiler (synthesis) latest version, and any others you want.
|
||||||
Follow prompts
|
- Click on all parts and the .spf file, then click Download Files near the top
|
||||||
|
- Move the SynopsysInstaller into `/cad/synopsys/Installer_5.4` with 755 permission for cad,
|
||||||
|
- move other files into `/cad/synopsys/downloads` and work as user cad from here on
|
||||||
|
|
||||||
|
```bash
|
||||||
|
$ cd /cad/synopsys/installer_5.4
|
||||||
|
$ ./SynopsysInstaller_v5.4.run
|
||||||
|
```
|
||||||
|
- Accept default installation directory
|
||||||
|
```bash
|
||||||
|
$ ./installer
|
||||||
|
```
|
||||||
|
- Enter source path as `/cad/synopsys/downloads`, and installation path as `/cad/synopsys`
|
||||||
|
- When prompted, enter your site ID
|
||||||
|
- Follow prompts
|
||||||
|
|
||||||
Installer can be utilized in graphical or text-based modes. It is far easier to use the text-based installation tool. To install DC, navigate to the location where your downloaded DC files are and type installer. You should be prompted with questions related to where you wish to have your files installed.
|
Installer can be utilized in graphical or text-based modes. It is far easier to use the text-based installation tool. To install DC, navigate to the location where your downloaded DC files are and type installer. You should be prompted with questions related to where you wish to have your files installed.
|
||||||
|
|
||||||
The Synopsys Installer automatically installs all downloaded product files into a single top-level target directory. You do not need to specify the installation directory for each product. For example, if you specify /import/programs/synopsys as the target directory, your installation directory structure might look like this after installation:
|
The Synopsys Installer automatically installs all downloaded product files into a single top-level target directory. You do not need to specify the installation directory for each product. For example, if you specify `/import/programs/synopsys` as the target directory, your installation directory structure might look like this after installation:
|
||||||
|
|
||||||
/import/programs/synopsys/syn/S-2021.06-SP1
|
```bash
|
||||||
|
/import/programs/synopsys/syn/S-2021.06-SP1
|
||||||
|
```
|
||||||
|
|
||||||
Note: Although most parts of Wally, including the Questa simulator, will work on most modern Linux platforms, as of 2022, the Synopsys CAD tools for SoC design are only supported on RedHat Enterprise Linux 7.4 or 8 or SUSE Linux Enterprise Server (SLES) 12 or 15. Moreover, the RISC-V formal specification (sail-riscv) does not build gracefully on RHEL7.
|
> [!Note]
|
||||||
|
> Although most parts of Wally, including the Questa simulator, will work on most modern Linux platforms, as of 2022, the Synopsys CAD tools for SoC design are only supported on RedHat Enterprise Linux 7.4 or 8 or SUSE Linux Enterprise Server (SLES) 12 or 15. Moreover, the RISC-V formal specification (sail-riscv) does not build gracefully on RHEL7.
|
||||||
|
|
||||||
The Verilog simulation has been tested with Siemens Questa/ModelSim. This package is available to universities worldwide as part of the Design Verification Bundle through the Siemens Academic Partner Program members for $990/year.
|
The Verilog simulation has been tested with Siemens Questa/ModelSim. This package is available to universities worldwide as part of the Design Verification Bundle through the Siemens Academic Partner Program members for $990/year.
|
||||||
|
|
||||||
@ -174,7 +199,7 @@ If you want to add a cronjob you can do the following:
|
|||||||
1) Set up the email client `mutt` for your distribution
|
1) Set up the email client `mutt` for your distribution
|
||||||
2) Enter `crontab -e` into a terminal
|
2) Enter `crontab -e` into a terminal
|
||||||
3) add this code to test building CVW and then running `regression-wally --nightly` at 9:30 PM each day
|
3) add this code to test building CVW and then running `regression-wally --nightly` at 9:30 PM each day
|
||||||
```
|
```bash
|
||||||
30 21 * * * bash -l -c "source ~/PATH/TO/CVW/setup.sh; PATH_TO_CVW/cvw/bin/wrapper_nightly_runs.sh --path {PATH_TO_TEST_LOCATION} --target all --tests nightly --send_email harris@hmc.edu,kaitlin.verilog@gmail.com"
|
30 21 * * * bash -l -c "source ~/PATH/TO/CVW/setup.sh; PATH_TO_CVW/cvw/bin/wrapper_nightly_runs.sh --path {PATH_TO_TEST_LOCATION} --target all --tests nightly --send_email harris@hmc.edu,kaitlin.verilog@gmail.com"
|
||||||
```
|
```
|
||||||
|
|
||||||
@ -182,44 +207,57 @@ If you want to add a cronjob you can do the following:
|
|||||||
|
|
||||||
wsim runs one of multiple simulators, Questa, VCS, or Verilator using a specific configuration and either a suite of tests or a specific elf file.
|
wsim runs one of multiple simulators, Questa, VCS, or Verilator using a specific configuration and either a suite of tests or a specific elf file.
|
||||||
The general syntax is
|
The general syntax is
|
||||||
wsim <config> <suite or elf file or directory> [--options]
|
`wsim <config> <suite or elf file or directory> [--options]`
|
||||||
|
|
||||||
Parameters and options:
|
Parameters and options:
|
||||||
|
|
||||||
-h, --help show this help message and exit
|
```
|
||||||
--sim {questa,verilator,vcs}, -s {questa,verilator,vcs} Simulator
|
-h, --help show this help message and exit
|
||||||
--tb {testbench,testbench_fp}, -t {testbench,testbench_fp} Testbench
|
--sim {questa,verilator,vcs}, -s {questa,verilator,vcs} Simulator
|
||||||
--gui, -g Simulate with GUI
|
--tb {testbench,testbench_fp}, -t {testbench,testbench_fp} Testbench
|
||||||
--coverage, -c Code & Functional Coverage
|
--gui, -g Simulate with GUI
|
||||||
--fcov, -f Code & Functional Coverage
|
--coverage, -c Code & Functional Coverage
|
||||||
--args ARGS, -a ARGS Optional arguments passed to simulator via $value$plusargs
|
--fcov, -f Code & Functional Coverage
|
||||||
--vcd, -v Generate testbench.vcd
|
--args ARGS, -a ARGS Optional arguments passed to simulator via $value$plusargs
|
||||||
--lockstep, -l Run ImperasDV lock, step, and compare.
|
--vcd, -v Generate testbench.vcd
|
||||||
--locksteplog LOCKSTEPLOG, -b LOCKSTEPLOG Retired instruction number to be begin logging.
|
--lockstep, -l Run ImperasDV lock, step, and compare.
|
||||||
--covlog COVLOG, -d COVLOG Log coverage after n instructions.
|
--locksteplog LOCKSTEPLOG, -b LOCKSTEPLOG Retired instruction number to be begin logging.
|
||||||
--elfext ELFEXT, -e ELFEXT When searching for elf files only includes ones which end in this extension
|
--covlog COVLOG, -d COVLOG Log coverage after n instructions.
|
||||||
|
--elfext ELFEXT, -e ELFEXT When searching for elf files only includes ones which end in this extension
|
||||||
|
```
|
||||||
|
|
||||||
Run basic test with questa
|
Run basic test with questa
|
||||||
|
|
||||||
wsim rv64gc arch64i
|
```bash
|
||||||
|
wsim rv64gc arch64i
|
||||||
|
```
|
||||||
|
|
||||||
Run Questa with gui
|
Run Questa with gui
|
||||||
|
|
||||||
wsim rv64gc wally64priv --gui
|
```bash
|
||||||
|
wsim rv64gc wally64priv --gui
|
||||||
|
```
|
||||||
|
|
||||||
Run lockstep against ImperasDV with a single elf file in the --gui. Lockstep requires single elf.
|
Run lockstep against ImperasDV with a single elf file in the gui. Lockstep requires single elf.
|
||||||
|
|
||||||
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --gui
|
```bash
|
||||||
|
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --gui
|
||||||
|
```
|
||||||
|
|
||||||
Run lockstep against ImperasDV with a single elf file. Compute coverage.
|
Run lockstep against ImperasDV with a single elf file. Compute coverage.
|
||||||
|
|
||||||
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --coverage
|
```bash
|
||||||
|
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --coverage
|
||||||
|
```
|
||||||
|
|
||||||
Run lockstep against ImperasDV with directory file.
|
Run lockstep against ImperasDV with directory file.
|
||||||
|
|
||||||
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep
|
```bash
|
||||||
|
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep
|
||||||
|
```
|
||||||
|
|
||||||
Run lockstep against ImperasDV with directory file and specify specific extension.
|
Run lockstep against ImperasDV with directory file and specify specific extension.
|
||||||
|
|
||||||
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep --elfext ref.elf
|
```bash
|
||||||
|
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep --elfext ref.elf
|
||||||
|
```
|
||||||
|
|||||||
@ -339,14 +339,15 @@ def run_test_case(config):
|
|||||||
grepfile = config.grepfile
|
grepfile = config.grepfile
|
||||||
cmd = config.cmd
|
cmd = config.cmd
|
||||||
os.chdir(regressionDir)
|
os.chdir(regressionDir)
|
||||||
# print(" run_test_case invoking %s" % cmd)
|
# print(" run_test_case invoking %s" % cmd, flush=True)
|
||||||
os.system(cmd)
|
os.system(cmd)
|
||||||
if search_log_for_text(config.grepstr, grepfile):
|
if search_log_for_text(config.grepstr, grepfile):
|
||||||
# print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name))
|
# Flush is needed to flush output to stdout when running in multiprocessing Pool
|
||||||
print(f"{bcolors.OKGREEN}%s: Success{bcolors.ENDC}" % (config.cmd))
|
# print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name), flush=True)
|
||||||
|
print(f"{bcolors.OKGREEN}%s: Success{bcolors.ENDC}" % (config.cmd), flush=True)
|
||||||
return 0
|
return 0
|
||||||
else:
|
else:
|
||||||
print(f"{bcolors.FAIL}%s: Failures detected in output{bcolors.ENDC}" % (config.cmd))
|
print(f"{bcolors.FAIL}%s: Failures detected in output{bcolors.ENDC}" % (config.cmd), flush=True)
|
||||||
print(" Check %s" % grepfile)
|
print(" Check %s" % grepfile)
|
||||||
return 1
|
return 1
|
||||||
|
|
||||||
@ -366,7 +367,6 @@ defaultsim = "verilator" # Default simulator for all other tests
|
|||||||
parser = argparse.ArgumentParser()
|
parser = argparse.ArgumentParser()
|
||||||
parser.add_argument("--ccov", help="Code Coverage", action="store_true")
|
parser.add_argument("--ccov", help="Code Coverage", action="store_true")
|
||||||
parser.add_argument("--fcov", help="Functional Coverage", action="store_true")
|
parser.add_argument("--fcov", help="Functional Coverage", action="store_true")
|
||||||
parser.add_argument("--fcovrvvi", help="Functional Coverage RVVI", action="store_true")
|
|
||||||
parser.add_argument("--nightly", help="Run large nightly regression", action="store_true")
|
parser.add_argument("--nightly", help="Run large nightly regression", action="store_true")
|
||||||
parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true")
|
parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true")
|
||||||
parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true")
|
parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true")
|
||||||
@ -385,8 +385,6 @@ if (args.ccov): # only run RV64GC tests in coverage mode
|
|||||||
coverStr = '--ccov'
|
coverStr = '--ccov'
|
||||||
elif (args.fcov): # only run RV64GC tests in lockstep in coverage mode
|
elif (args.fcov): # only run RV64GC tests in lockstep in coverage mode
|
||||||
coverStr = '--fcov'
|
coverStr = '--fcov'
|
||||||
elif (args.fcovrvvi): # only run RV64GC tests in rvvi coverage mode
|
|
||||||
coverStr = '--fcovrvvi'
|
|
||||||
else:
|
else:
|
||||||
coverStr = ''
|
coverStr = ''
|
||||||
|
|
||||||
@ -415,11 +413,8 @@ if (args.ccov): # only run RV64GC tests on Questa in code coverage mode
|
|||||||
elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode
|
elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode
|
||||||
addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1)
|
addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1)
|
||||||
addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1)
|
addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1)
|
||||||
# addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0)
|
#addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0)
|
||||||
elif (args.fcovrvvi): # only run RV64GC tests on Questa in rvvi coverage mode
|
|
||||||
addTests(tests64gc_nofp, coveragesim)
|
|
||||||
if (args.fp):
|
|
||||||
addTests(tests64gc_fp, coveragesim)
|
|
||||||
else:
|
else:
|
||||||
for sim in sims:
|
for sim in sims:
|
||||||
if (not (args.buildroot and sim == defaultsim)): # skip short buildroot sim if running long one
|
if (not (args.buildroot and sim == defaultsim)): # skip short buildroot sim if running long one
|
||||||
@ -511,9 +506,6 @@ def main():
|
|||||||
if args.ccov:
|
if args.ccov:
|
||||||
TIMEOUT_DUR = 20*60 # seconds
|
TIMEOUT_DUR = 20*60 # seconds
|
||||||
os.system('rm -f questa/cov/*.ucdb')
|
os.system('rm -f questa/cov/*.ucdb')
|
||||||
elif args.fcovrvvi:
|
|
||||||
TIMEOUT_DUR = 20*60
|
|
||||||
os.system('rm -f questa/fcovrvvi_ucdb/* questa/fcovrvvi_logs/* questa/fcovrvvi/*')
|
|
||||||
elif args.fcov:
|
elif args.fcov:
|
||||||
TIMEOUT_DUR = 8*60
|
TIMEOUT_DUR = 8*60
|
||||||
os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*')
|
os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*')
|
||||||
@ -550,8 +542,6 @@ def main():
|
|||||||
os.system('make QuestaCodeCoverage')
|
os.system('make QuestaCodeCoverage')
|
||||||
if args.fcov:
|
if args.fcov:
|
||||||
os.system('make -f '+WALLY+'/addins/cvw-arch-verif/Makefile merge')
|
os.system('make -f '+WALLY+'/addins/cvw-arch-verif/Makefile merge')
|
||||||
if args.fcovrvvi:
|
|
||||||
os.system('make QuestaFunctCoverageRvvi')
|
|
||||||
# Count the number of failures
|
# Count the number of failures
|
||||||
if num_fail:
|
if num_fail:
|
||||||
print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)
|
print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)
|
||||||
|
|||||||
@ -48,28 +48,64 @@ ENDC='\033[0m' # Reset to default color
|
|||||||
error() {
|
error() {
|
||||||
echo -e "${FAIL_COLOR}Error: $STATUS installation failed"
|
echo -e "${FAIL_COLOR}Error: $STATUS installation failed"
|
||||||
echo -e "Error on line ${BASH_LINENO[0]} with command $BASH_COMMAND${ENDC}"
|
echo -e "Error on line ${BASH_LINENO[0]} with command $BASH_COMMAND${ENDC}"
|
||||||
echo -e "Please check the log in $RISCV/logs/$STATUS.log for more information."
|
if [ -e "$RISCV/logs/$STATUS.log" ]; then
|
||||||
|
echo -e "Please check the log in $RISCV/logs/$STATUS.log for more information."
|
||||||
|
fi
|
||||||
exit 1
|
exit 1
|
||||||
}
|
}
|
||||||
|
|
||||||
# Check if a git repository exists, is up to date, and has been installed
|
# Check if a git repository exists, is up to date, and has been installed
|
||||||
# Clones the repository if it doesn't exist
|
# clones the repository if it doesn't exist
|
||||||
|
# $1: repo name
|
||||||
|
# $2: repo url to clone from
|
||||||
|
# $3: file to check if already installed
|
||||||
|
# $4: upstream branch, optional, default is master
|
||||||
git_check() {
|
git_check() {
|
||||||
local repo=$1
|
local repo=$1
|
||||||
local url=$2
|
local url=$2
|
||||||
local check=$3
|
local check=$3
|
||||||
local branch="${4:-master}"
|
local branch="${4:-master}"
|
||||||
if [[ ((! -e $repo) && ($(git clone "$url") || true)) || ($(cd "$repo"; git fetch; git rev-parse HEAD) != $(cd "$repo"; git rev-parse origin/"$branch")) || (! -e $check) ]]; then
|
|
||||||
return 0
|
# Clone repo if it doesn't exist
|
||||||
|
if [[ ! -e $repo ]]; then
|
||||||
|
for ((i=1; i<=5; i++)); do
|
||||||
|
git clone "$url" && break
|
||||||
|
echo -e "${WARNING_COLOR}Failed to clone $repo. Retrying.${ENDC}"
|
||||||
|
rm -rf "$repo"
|
||||||
|
sleep $i
|
||||||
|
done
|
||||||
|
if [[ ! -e $repo ]]; then
|
||||||
|
echo -e "${ERROR_COLOR}Failed to clone $repo after 5 attempts. Exiting.${ENDC}"
|
||||||
|
exit 1
|
||||||
|
fi
|
||||||
|
fi
|
||||||
|
|
||||||
|
# Get the current HEAD commit hash and the remote branch commit hash
|
||||||
|
cd "$repo"
|
||||||
|
git fetch
|
||||||
|
local local_head=$(git rev-parse HEAD)
|
||||||
|
local remote_head=$(git rev-parse origin/"$branch")
|
||||||
|
|
||||||
|
# Check if the git repository is not up to date or the specified file does not exist
|
||||||
|
if [[ "$local_head" != "$remote_head" ]]; then
|
||||||
|
echo "$repo is not up to date. Updating now."
|
||||||
|
true
|
||||||
|
elif [[ ! -e $check ]]; then
|
||||||
|
true
|
||||||
else
|
else
|
||||||
return 1
|
false
|
||||||
fi
|
fi
|
||||||
}
|
}
|
||||||
|
|
||||||
# Log output to a file and only print lines with keywords
|
# Log output to a file and only print lines with keywords
|
||||||
logger() {
|
logger() {
|
||||||
local log="$RISCV/logs/$1.log"
|
local log_file="$RISCV/logs/$1.log"
|
||||||
cat < /dev/stdin | tee -a "$log" | (grep -iE --color=never "(\bwarning|\berror|\bfail|\bsuccess|\bstamp|\bdoesn't work)" || true) | (grep -viE --color=never "(_warning|warning_|_error|error_|-warning|warning-|-error|error-|Werror|error\.o|warning flags)" || true)
|
local keyword_pattern="(\bwarning|\berror|\bfail|\bsuccess|\bstamp|\bdoesn't work)"
|
||||||
|
local exclude_pattern="(_warning|warning_|_error|error_|-warning|warning-|-error|error-|Werror|error\.o|warning flags)"
|
||||||
|
|
||||||
|
cat < /dev/stdin | tee -a "$log_file" | \
|
||||||
|
(grep -iE --color=never "$keyword_pattern" || true) | \
|
||||||
|
(grep -viE --color=never "$exclude_pattern" || true)
|
||||||
}
|
}
|
||||||
|
|
||||||
set -e # break on error
|
set -e # break on error
|
||||||
@ -111,6 +147,10 @@ fi
|
|||||||
export PATH=$PATH:$RISCV/bin:/usr/bin
|
export PATH=$PATH:$RISCV/bin:/usr/bin
|
||||||
export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$RISCV/lib/x86_64-linux-gnu/pkgconfig:$PKG_CONFIG_PATH
|
export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$RISCV/lib/x86_64-linux-gnu/pkgconfig:$PKG_CONFIG_PATH
|
||||||
|
|
||||||
|
if (( RHEL_VERSION != 8 )); then
|
||||||
|
retry_on_host_error="--retry-on-host-error"
|
||||||
|
fi
|
||||||
|
|
||||||
# Check for incompatible PATH environment variable before proceeding with installation
|
# Check for incompatible PATH environment variable before proceeding with installation
|
||||||
if [[ ":$PATH:" == *::* || ":$PATH:" == *:.:* ]]; then
|
if [[ ":$PATH:" == *::* || ":$PATH:" == *:.:* ]]; then
|
||||||
echo -e "${FAIL_COLOR}Error: You seem to have the current working directory in your \$PATH environment variable."
|
echo -e "${FAIL_COLOR}Error: You seem to have the current working directory in your \$PATH environment variable."
|
||||||
@ -191,11 +231,13 @@ if (( RHEL_VERSION == 8 )) || (( UBUNTU_VERSION == 20 )); then
|
|||||||
section_header "Installing glib"
|
section_header "Installing glib"
|
||||||
pip install -U meson # Meson is needed to build glib
|
pip install -U meson # Meson is needed to build glib
|
||||||
cd "$RISCV"
|
cd "$RISCV"
|
||||||
curl --location https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz | tar xJ
|
wget -nv --retry-connrefused $retry_on_host_error https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz
|
||||||
|
tar -xJf glib-2.70.5.tar.xz
|
||||||
|
rm -f glib-2.70.5.tar.xz
|
||||||
cd glib-2.70.5
|
cd glib-2.70.5
|
||||||
meson setup _build --prefix="$RISCV"
|
meson setup _build --prefix="$RISCV"
|
||||||
meson compile -C _build
|
meson compile -C _build -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
|
||||||
meson install -C _build
|
meson install -C _build 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
|
||||||
cd "$RISCV"
|
cd "$RISCV"
|
||||||
rm -rf glib-2.70.5
|
rm -rf glib-2.70.5
|
||||||
echo -e "${SUCCESS_COLOR}glib successfully installed!${ENDC}"
|
echo -e "${SUCCESS_COLOR}glib successfully installed!${ENDC}"
|
||||||
@ -208,11 +250,13 @@ if (( RHEL_VERSION == 8 )); then
|
|||||||
if [ ! -e "$RISCV"/include/gmp.h ]; then
|
if [ ! -e "$RISCV"/include/gmp.h ]; then
|
||||||
section_header "Installing gmp"
|
section_header "Installing gmp"
|
||||||
cd "$RISCV"
|
cd "$RISCV"
|
||||||
curl --location https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz | tar xJ
|
wget -nv --retry-connrefused $retry_on_host_error https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz
|
||||||
|
tar -xJf gmp-6.3.0.tar.xz
|
||||||
|
rm -f gmp-6.3.0.tar.xz
|
||||||
cd gmp-6.3.0
|
cd gmp-6.3.0
|
||||||
./configure --prefix="$RISCV"
|
./configure --prefix="$RISCV"
|
||||||
make -j "${NUM_THREADS}"
|
make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
|
||||||
make install
|
make install 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
|
||||||
cd "$RISCV"
|
cd "$RISCV"
|
||||||
rm -rf gmp-6.3.0
|
rm -rf gmp-6.3.0
|
||||||
echo -e "${SUCCESS_COLOR}gmp successfully installed!${ENDC}"
|
echo -e "${SUCCESS_COLOR}gmp successfully installed!${ENDC}"
|
||||||
@ -230,9 +274,9 @@ section_header "Installing/Updating RISC-V GNU Toolchain"
|
|||||||
STATUS="riscv-gnu-toolchain"
|
STATUS="riscv-gnu-toolchain"
|
||||||
cd "$RISCV"
|
cd "$RISCV"
|
||||||
# Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension.
|
# Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension.
|
||||||
if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then
|
if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2"; then
|
||||||
cd riscv-gnu-toolchain
|
cd "$RISCV"/riscv-gnu-toolchain
|
||||||
git reset --hard && git clean -f && git checkout b488ddb #&& git pull
|
git reset --hard && git clean -f && git checkout master && git pull
|
||||||
./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
|
./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
|
||||||
make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
|
make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
|
||||||
if [ "$clean" ]; then
|
if [ "$clean" ]; then
|
||||||
@ -257,7 +301,7 @@ STATUS="elf2hex"
|
|||||||
cd "$RISCV"
|
cd "$RISCV"
|
||||||
export PATH=$RISCV/bin:$PATH
|
export PATH=$RISCV/bin:$PATH
|
||||||
if git_check "elf2hex" "https://github.com/sifive/elf2hex.git" "$RISCV/bin/riscv64-unknown-elf-elf2bin"; then
|
if git_check "elf2hex" "https://github.com/sifive/elf2hex.git" "$RISCV/bin/riscv64-unknown-elf-elf2bin"; then
|
||||||
cd elf2hex
|
cd "$RISCV"/elf2hex
|
||||||
git reset --hard && git clean -f && git checkout master && git pull
|
git reset --hard && git clean -f && git checkout master && git pull
|
||||||
autoreconf -i
|
autoreconf -i
|
||||||
./configure --target=riscv64-unknown-elf --prefix="$RISCV"
|
./configure --target=riscv64-unknown-elf --prefix="$RISCV"
|
||||||
@ -279,7 +323,7 @@ section_header "Installing/Updating QEMU"
|
|||||||
STATUS="qemu"
|
STATUS="qemu"
|
||||||
cd "$RISCV"
|
cd "$RISCV"
|
||||||
if git_check "qemu" "https://github.com/qemu/qemu" "$RISCV/include/qemu-plugin.h"; then
|
if git_check "qemu" "https://github.com/qemu/qemu" "$RISCV/include/qemu-plugin.h"; then
|
||||||
cd qemu
|
cd "$RISCV"/qemu
|
||||||
git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules -j "${NUM_THREADS}"
|
git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules -j "${NUM_THREADS}"
|
||||||
git submodule update --init --recursive
|
git submodule update --init --recursive
|
||||||
./configure --target-list=riscv64-softmmu --prefix="$RISCV"
|
./configure --target-list=riscv64-softmmu --prefix="$RISCV"
|
||||||
@ -301,7 +345,7 @@ section_header "Installing/Updating SPIKE"
|
|||||||
STATUS="spike"
|
STATUS="spike"
|
||||||
cd "$RISCV"
|
cd "$RISCV"
|
||||||
if git_check "riscv-isa-sim" "https://github.com/riscv-software-src/riscv-isa-sim" "$RISCV/lib/pkgconfig/riscv-riscv.pc"; then
|
if git_check "riscv-isa-sim" "https://github.com/riscv-software-src/riscv-isa-sim" "$RISCV/lib/pkgconfig/riscv-riscv.pc"; then
|
||||||
cd riscv-isa-sim
|
cd "$RISCV"/riscv-isa-sim
|
||||||
git reset --hard && git clean -f && git checkout master && git pull
|
git reset --hard && git clean -f && git checkout master && git pull
|
||||||
mkdir -p build
|
mkdir -p build
|
||||||
cd build
|
cd build
|
||||||
@ -327,7 +371,7 @@ STATUS="verilator"
|
|||||||
cd "$RISCV"
|
cd "$RISCV"
|
||||||
if git_check "verilator" "https://github.com/verilator/verilator" "$RISCV/share/pkgconfig/verilator.pc"; then
|
if git_check "verilator" "https://github.com/verilator/verilator" "$RISCV/share/pkgconfig/verilator.pc"; then
|
||||||
unset VERILATOR_ROOT
|
unset VERILATOR_ROOT
|
||||||
cd verilator
|
cd "$RISCV"/verilator
|
||||||
git reset --hard && git clean -f && git checkout master && git pull
|
git reset --hard && git clean -f && git checkout master && git pull
|
||||||
autoconf
|
autoconf
|
||||||
./configure --prefix="$RISCV"
|
./configure --prefix="$RISCV"
|
||||||
@ -352,7 +396,9 @@ section_header "Installing/Updating Sail Compiler"
|
|||||||
STATUS="Sail Compiler"
|
STATUS="Sail Compiler"
|
||||||
if [ ! -e "$RISCV"/bin/sail ]; then
|
if [ ! -e "$RISCV"/bin/sail ]; then
|
||||||
cd "$RISCV"
|
cd "$RISCV"
|
||||||
curl --location https://github.com/rems-project/sail/releases/latest/download/sail.tar.gz | tar xvz --directory="$RISCV" --strip-components=1
|
wget -nv --retry-connrefused $retry_on_host_error --output-document=sail.tar.gz https://github.com/rems-project/sail/releases/latest/download/sail.tar.gz
|
||||||
|
tar xz --directory="$RISCV" --strip-components=1 -f sail.tar.gz
|
||||||
|
rm -f sail.tar.gz
|
||||||
echo -e "${SUCCESS_COLOR}Sail Compiler successfully installed/updated!${ENDC}"
|
echo -e "${SUCCESS_COLOR}Sail Compiler successfully installed/updated!${ENDC}"
|
||||||
else
|
else
|
||||||
echo -e "${SUCCESS_COLOR}Sail Compiler already installed.${ENDC}"
|
echo -e "${SUCCESS_COLOR}Sail Compiler already installed.${ENDC}"
|
||||||
@ -363,7 +409,7 @@ fi
|
|||||||
section_header "Installing/Updating RISC-V Sail Model"
|
section_header "Installing/Updating RISC-V Sail Model"
|
||||||
STATUS="riscv-sail-model"
|
STATUS="riscv-sail-model"
|
||||||
if git_check "sail-riscv" "https://github.com/riscv/sail-riscv.git" "$RISCV/bin/riscv_sim_RV32"; then
|
if git_check "sail-riscv" "https://github.com/riscv/sail-riscv.git" "$RISCV/bin/riscv_sim_RV32"; then
|
||||||
cd sail-riscv
|
cd "$RISCV"/sail-riscv
|
||||||
git reset --hard && git clean -f && git checkout master && git pull
|
git reset --hard && git clean -f && git checkout master && git pull
|
||||||
ARCH=RV64 make -j "${NUM_THREADS}" c_emulator/riscv_sim_RV64 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
|
ARCH=RV64 make -j "${NUM_THREADS}" c_emulator/riscv_sim_RV64 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
|
||||||
ARCH=RV32 make -j "${NUM_THREADS}" c_emulator/riscv_sim_RV32 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
|
ARCH=RV32 make -j "${NUM_THREADS}" c_emulator/riscv_sim_RV32 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
|
||||||
@ -386,7 +432,7 @@ STATUS="OSU Skywater 130 cell library"
|
|||||||
mkdir -p "$RISCV"/cad/lib
|
mkdir -p "$RISCV"/cad/lib
|
||||||
cd "$RISCV"/cad/lib
|
cd "$RISCV"/cad/lib
|
||||||
if git_check "sky130_osu_sc_t12" "https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12" "$RISCV/cad/lib/sky130_osu_sc_t12" "main"; then
|
if git_check "sky130_osu_sc_t12" "https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12" "$RISCV/cad/lib/sky130_osu_sc_t12" "main"; then
|
||||||
cd sky130_osu_sc_t12
|
cd "$RISCV"/sky130_osu_sc_t12
|
||||||
git reset --hard && git clean -f && git checkout main && git pull
|
git reset --hard && git clean -f && git checkout main && git pull
|
||||||
echo -e "${SUCCESS_COLOR}OSU Skywater library successfully installed!${ENDC}"
|
echo -e "${SUCCESS_COLOR}OSU Skywater library successfully installed!${ENDC}"
|
||||||
else
|
else
|
||||||
@ -428,8 +474,8 @@ section_header "Downloading Site Setup Script"
|
|||||||
STATUS="site-setup scripts"
|
STATUS="site-setup scripts"
|
||||||
cd "$RISCV"
|
cd "$RISCV"
|
||||||
if [ ! -e "${RISCV}"/site-setup.sh ]; then
|
if [ ! -e "${RISCV}"/site-setup.sh ]; then
|
||||||
wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.sh
|
wget -nv --retry-connrefused $retry_on_host_error https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.sh
|
||||||
wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh
|
wget -nv --retry-connrefused $retry_on_host_error https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh
|
||||||
echo -e "${SUCCESS_COLOR}Site setup script successfully downloaded!${ENDC}"
|
echo -e "${SUCCESS_COLOR}Site setup script successfully downloaded!${ENDC}"
|
||||||
echo -e "${WARNING_COLOR}Make sure to edit the environment variables in $RISCV/site-setup.sh (or .csh) to point to your installation of EDA tools and licensce files.${ENDC}"
|
echo -e "${WARNING_COLOR}Make sure to edit the environment variables in $RISCV/site-setup.sh (or .csh) to point to your installation of EDA tools and licensce files.${ENDC}"
|
||||||
else
|
else
|
||||||
|
|||||||
7
bin/wsim
7
bin/wsim
@ -29,7 +29,6 @@ parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true"
|
|||||||
parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true")
|
parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true")
|
||||||
parser.add_argument("--fcovimp", "-f2", help="Functional Coverage with Imperas licensed riscvISACOV, implies lockstep", action="store_true")
|
parser.add_argument("--fcovimp", "-f2", help="Functional Coverage with Imperas licensed riscvISACOV, implies lockstep", action="store_true")
|
||||||
parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true")
|
parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true")
|
||||||
parser.add_argument("--fcovrvvi", "-fr", help="Functional Coverage RVVI", action="store_true")
|
|
||||||
parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
|
parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
|
||||||
parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
|
parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
|
||||||
parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true")
|
parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true")
|
||||||
@ -71,7 +70,7 @@ if(args.lockstep and not args.testsuite.endswith('.elf')):
|
|||||||
exit(1)
|
exit(1)
|
||||||
|
|
||||||
# Validate arguments
|
# Validate arguments
|
||||||
if (args.gui or args.ccov or args.fcov or args.fcovimp or args.fcovrvvi or args.lockstep or args.lockstepverbose):
|
if (args.gui or args.ccov or args.fcov or args.fcovimp or args.lockstep or args.lockstepverbose):
|
||||||
if args.sim not in ["questa", "vcs"]:
|
if args.sim not in ["questa", "vcs"]:
|
||||||
print("Option only supported for Questa and VCS")
|
print("Option only supported for Questa and VCS")
|
||||||
exit(1)
|
exit(1)
|
||||||
@ -129,12 +128,10 @@ if (args.fcov):
|
|||||||
flags += " --fcov"
|
flags += " --fcov"
|
||||||
if (args.fcovimp):
|
if (args.fcovimp):
|
||||||
flags += " --fcovimp"
|
flags += " --fcovimp"
|
||||||
if (args.fcovrvvi):
|
|
||||||
flags += "--fcovrvvi"
|
|
||||||
|
|
||||||
# create the output sub-directories.
|
# create the output sub-directories.
|
||||||
regressionDir = WALLY + '/sim/'
|
regressionDir = WALLY + '/sim/'
|
||||||
for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb", "fcovrvvi", "fcovrvvi_ucdb"]:
|
for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb"]:
|
||||||
try:
|
try:
|
||||||
os.mkdir(regressionDir+args.sim+"/"+d)
|
os.mkdir(regressionDir+args.sim+"/"+d)
|
||||||
except:
|
except:
|
||||||
|
|||||||
@ -5,18 +5,22 @@
|
|||||||
// This file is needed in the config subdirectory for each config supporting coverage.
|
// This file is needed in the config subdirectory for each config supporting coverage.
|
||||||
// It defines which extensions are enabled for that config.
|
// It defines which extensions are enabled for that config.
|
||||||
|
|
||||||
|
// Unprivileged extensions
|
||||||
`include "RV64I_coverage.svh"
|
`include "RV64I_coverage.svh"
|
||||||
`include "RV64M_coverage.svh"
|
`include "RV64M_coverage.svh"
|
||||||
`include "RV64F_coverage.svh"
|
`include "RV64F_coverage.svh"
|
||||||
`include "RV64Zfh_coverage.svh"
|
`include "RV64Zfh_coverage.svh"
|
||||||
`include "RV64VM_coverage.svh"
|
`include "RV64VM_coverage.svh"
|
||||||
|
`include "RV64Zicond_coverage.svh"
|
||||||
|
`include "RV64Zca_coverage.svh"
|
||||||
|
`include "RV64Zcb_coverage.svh"
|
||||||
|
`include "RV64ZcbM_coverage.svh"
|
||||||
|
`include "RV64ZcbZbb_coverage.svh"
|
||||||
|
`include "RV64ZcbZba_coverage.svh"
|
||||||
|
|
||||||
|
// Privileged extensions
|
||||||
`include "ZicsrM_coverage.svh"
|
`include "ZicsrM_coverage.svh"
|
||||||
// `include "RV64VM_PMP_coverage.svh"
|
// `include "RV64VM_PMP_coverage.svh"
|
||||||
// `include "RV64CBO_VM_coverage.svh"
|
// `include "RV64CBO_VM_coverage.svh"
|
||||||
// `include "RV64CBO_PMP_coverage.svh"
|
// `include "RV64CBO_PMP_coverage.svh"
|
||||||
// `include "RV64Zicbom_coverage.svh"
|
// `include "RV64Zicbom_coverage.svh"
|
||||||
`include "RV64Zicond_coverage.svh"
|
|
||||||
`include "RV64Zca_coverage.svh"
|
|
||||||
`include "RV64Zcb_coverage.svh"
|
|
||||||
`include "RV64ZcbM_coverage.svh"
|
|
||||||
`include "RV64ZcbZbb_coverage.svh"
|
|
||||||
@ -1,41 +0,0 @@
|
|||||||
### Cross-Compile Buildroot Linux
|
|
||||||
|
|
||||||
Building Linux is only necessary for exploring the boot process in Chapter 17. Building and generating a trace is a time-consuming operation that could be skipped for now; you can return to this section later if you are interested in the Linux details.
|
|
||||||
|
|
||||||
Buildroot depends on configuration files in riscv-wally, so the cad user must install Wally first according to the instructions in Section 2.2.2. However, don’t source ~/wally-riscv/setup.sh because it will set LD_LIBRARY_PATH in a way to cause make to fail on buildroot.
|
|
||||||
|
|
||||||
To configure and build Buildroot:
|
|
||||||
|
|
||||||
$ cd $RISCV
|
|
||||||
$ export WALLY=~/riscv-wally # make sure you haven’t sourced ~/riscv-wally/setup.sh by now
|
|
||||||
$ git clone https://github.com/buildroot/buildroot.git
|
|
||||||
$ cd buildroot
|
|
||||||
$ git checkout 2021.05 # last tested working version
|
|
||||||
$ cp -r $WALLY/linux/buildroot-config-src/wally ./board
|
|
||||||
$ cp ./board/wally/main.config .config
|
|
||||||
$ make --jobs
|
|
||||||
|
|
||||||
To generate disassembly files and the device tree, run another make script. Note that you can expect some warnings about phandle references while running dtc on wally-virt.dtb.
|
|
||||||
Depending on your system configuration this makefile may need a bit of tweaking. It places the output buildroot images in $RISCV/linux-testvectors and the buildroot object dumps in $RISCV/buildroot/output/images/disassembly. If these directories are owned by root then the makefile will likely fail. You can either change the makefile's target directories or change temporarily change the owner of the two directories.
|
|
||||||
|
|
||||||
$ source ~/riscv-wally/setup.sh
|
|
||||||
$ cd $WALLY/linux/buildroot-scripts
|
|
||||||
$ make all
|
|
||||||
|
|
||||||
Note: When the make tasks complete, you’ll find source code in $RISCV/buildroot/output/build and the executables in $RISCV/buildroot/output/images.
|
|
||||||
|
|
||||||
### Generate load images for linux boot
|
|
||||||
|
|
||||||
The Questa linux boot uses preloaded bootram and ram memory. We use QEMU to generate these preloaded memory files. Files output in $RISCV/linux-testvectors
|
|
||||||
|
|
||||||
cd cvw/linux/testvector-generation
|
|
||||||
./genInitMem.sh
|
|
||||||
|
|
||||||
This may require changing file permissions to the linux-testvectors directory.
|
|
||||||
|
|
||||||
### Generate QEMU linux trace
|
|
||||||
|
|
||||||
The linux testbench can instruction by instruction compare Wally's committed instructions against QEMU. To do this QEMU outputs a log file consisting of all instructions executed. Interrupts are handled by forcing the testbench to generate an interrupt at the same cycle as in QEMU. Generating this trace will take more than 24 hours.
|
|
||||||
|
|
||||||
cd cvw/linux/testvector-generation
|
|
||||||
./genTrace.sh
|
|
||||||
@ -6,29 +6,39 @@ Wally supports the following boards
|
|||||||
|
|
||||||
# Quick Start
|
# Quick Start
|
||||||
|
|
||||||
## build FPGA
|
## Build FPGA
|
||||||
|
|
||||||
`cd generator
|
```bash
|
||||||
make <board name>`
|
cd generator
|
||||||
|
make <board name>
|
||||||
|
```
|
||||||
|
|
||||||
example
|
Example:
|
||||||
`make vcu108`
|
```bash
|
||||||
|
make vcu108
|
||||||
|
```
|
||||||
|
|
||||||
## Make flash card image
|
## Make flash card image
|
||||||
ls /dev/sd* or ls /dev/mmc* to see which flash card devices you have.
|
`ls /dev/sd*` or `ls /dev/mmc*` to see which flash card devices you have.
|
||||||
Insert the flash card into the reader and ls /dev/sd* or /dev/mmc* again. The new device is the one you want to use. Make sure you select the root device (i.e. /dev/sdb) not the partition (i.e. /dev/sdb1).
|
Insert the flash card into the reader and `ls /dev/sd*` or `/dev/mmc*` again. The new device is the one you want to use. Make sure you select the root device (i.e. `/dev/sdb`) not the partition (i.e. `/dev/sdb1`).
|
||||||
|
|
||||||
`cd $WALLY/linux/sd-card`
|
```bash
|
||||||
|
cd $WALLY/linux/sd-card
|
||||||
|
```
|
||||||
|
|
||||||
This following script requires root.
|
This following script requires root.
|
||||||
|
|
||||||
`./flash-sd.sh -b <path to buildroot> -d <path to compiled device tree file> <flash card device>`
|
```bash
|
||||||
|
./flash-sd.sh -b <path to buildroot> -d <path to compiled device tree file> <flash card device>
|
||||||
|
```
|
||||||
|
|
||||||
example with vcu108, buildroot installed to /opt/riscv/buildroot, and the flash card is device /dev/sdc
|
Example with vcu108, buildroot installed to `/opt/riscv/buildroot`, and the flash card is device `/dev/sdc`
|
||||||
|
|
||||||
`./flash-sd.sh -b /opt/riscv/buildroot -d /opt/riscv/buildroot/output/images/wally-vcu108.dtb /dev/sdc`
|
```bash
|
||||||
|
./flash-sd.sh -b /opt/riscv/buildroot -d /opt/riscv/buildroot/output/images/wally-vcu108.dtb /dev/sdc
|
||||||
|
```
|
||||||
|
|
||||||
Wait until the the script completes then remove the car.
|
Wait until the the script completes then remove the card.
|
||||||
|
|
||||||
## FPGA setup
|
## FPGA setup
|
||||||
|
|
||||||
@ -36,22 +46,26 @@ For the Arty A7 insert the PMOD daughter board into the right most slot and inse
|
|||||||
|
|
||||||
For the VCU108 and VCU118 boards insert the PMOD daughter board into the only PMOD slot on the right side of the boards.
|
For the VCU108 and VCU118 boards insert the PMOD daughter board into the only PMOD slot on the right side of the boards.
|
||||||
|
|
||||||
Power on the boards. Arty A7 just plug in the USB connector. For the VCU boards make sure the power supply is connected and the two usb cables are connected. Flip on the switch.
|
Power on the boards. For Arty A7 just plug in the USB connector. For the VCU boards make sure the power supply is connected and the two usb cables are connected. Flip on the switch.
|
||||||
The VCU118's on board UART converter does not work. Use a spark fun FTDI usb to UART adapter and plug into the mail PMOD on the right side of the board. Also the level sifters on the
|
The VCU118's on board UART converter does not work. Use a spark fun FTDI usb to UART adapter and plug into the mail PMOD on the right side of the board. Also the level sifters on the
|
||||||
VCU118 do not work correctly with the digilent sd PMOD board. We have a custom board which works instead.
|
VCU118 do not work correctly with the digilent sd PMOD board. We have a custom board which works instead.
|
||||||
|
|
||||||
`cd $WALLY/fpga/generator
|
```bash
|
||||||
vivado &`
|
cd $WALLY/fpga/generator
|
||||||
|
vivado &
|
||||||
|
```
|
||||||
|
|
||||||
open the design in the current directory WallyFPGA.xpr.
|
Open the design in the current directory `WallyFPGA.xpr`.
|
||||||
|
|
||||||
Then click "Open Target" under "PROGRAM AND DEBUG". Then Program the device.
|
Then click "Open Target" under "PROGRAM AND DEBUG". Then Program the device.
|
||||||
|
|
||||||
## Connect to UART
|
## Connect to UART
|
||||||
|
|
||||||
In another terminal ls /dev/ttyUSB*. One of these devices will be the UART connected to Wally. You may have to experiment by the running the following command multiple times.
|
In another terminal `ls /dev/ttyUSB*`. One of these devices will be the UART connected to Wally. You may have to experiment by the running the following command multiple times.
|
||||||
|
|
||||||
`screen /dev/ttyUSB1 115200`
|
```bash
|
||||||
|
screen /dev/ttyUSB1 115200
|
||||||
|
```
|
||||||
|
|
||||||
Swap out the USB1 for USB0 or USB1 as needed.
|
Swap out the `USB1` for `USB0` or `USB1` as needed.
|
||||||
|
|
||||||
|
|||||||
@ -27,9 +27,16 @@ BINARIES := fw_jump.elf vmlinux busybox
|
|||||||
OBJDUMPS := $(foreach name, $(BINARIES), $(basename $(name) .elf))
|
OBJDUMPS := $(foreach name, $(BINARIES), $(basename $(name) .elf))
|
||||||
OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump)
|
OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump)
|
||||||
|
|
||||||
.PHONY: all generate disassemble install clean cleanDTB cleanDriver check_write_permissions
|
.PHONY: all generate disassemble install clean cleanDTB check_write_permissions check_environment
|
||||||
|
|
||||||
all: check_write_permissions clean download Image disassemble install dumptvs
|
all: check_environment check_write_permissions clean download Image disassemble install dumptvs
|
||||||
|
|
||||||
|
check_environment: $(RISCV)
|
||||||
|
ifeq ($(findstring :$(RISCV)/lib:,:$(LD_LIBRARY_PATH):),)
|
||||||
|
@(echo "ERROR: Your environment variables are not set correctly." >&2 \
|
||||||
|
&& echo "Make sure to source setup.sh or install buildroot using the wally-tool-chain-install.sh script." >&2 \
|
||||||
|
&& exit 1)
|
||||||
|
endif
|
||||||
|
|
||||||
check_write_permissions:
|
check_write_permissions:
|
||||||
ifeq ($(SUDO), sudo)
|
ifeq ($(SUDO), sudo)
|
||||||
@ -41,17 +48,17 @@ endif
|
|||||||
&& exit 1)
|
&& exit 1)
|
||||||
@$(SUDO) rm -r $(RISCV)/.test
|
@$(SUDO) rm -r $(RISCV)/.test
|
||||||
|
|
||||||
Image:
|
Image: check_environment
|
||||||
bash -c "unset LD_LIBRARY_PATH; $(MAKE) -C $(BUILDROOT)"
|
bash -c "unset LD_LIBRARY_PATH; $(MAKE) -C $(BUILDROOT)"
|
||||||
$(MAKE) generate
|
$(MAKE) generate
|
||||||
@echo "Buildroot Image successfully generated."
|
@echo "Buildroot Image successfully generated."
|
||||||
|
|
||||||
install: check_write_permissions
|
install: check_write_permissions check_environment
|
||||||
$(SUDO) rm -rf $(RISCV)/$(BUILDROOT)
|
$(SUDO) rm -rf $(RISCV)/$(BUILDROOT)
|
||||||
$(SUDO) mv $(BUILDROOT) $(RISCV)/$(BUILDROOT)
|
$(SUDO) mv $(BUILDROOT) $(RISCV)/$(BUILDROOT)
|
||||||
@echo "Buildroot successfully installed."
|
@echo "Buildroot successfully installed."
|
||||||
|
|
||||||
dumptvs: check_write_permissions
|
dumptvs: check_write_permissions check_environment
|
||||||
$(SUDO) mkdir -p $(RISCV)/linux-testvectors
|
$(SUDO) mkdir -p $(RISCV)/linux-testvectors
|
||||||
cd testvector-generation; ./genInitMem.sh
|
cd testvector-generation; ./genInitMem.sh
|
||||||
@echo "Testvectors successfully generated."
|
@echo "Testvectors successfully generated."
|
||||||
@ -70,7 +77,7 @@ $(RISCV):
|
|||||||
@ echo "and sourced setup.sh"
|
@ echo "and sourced setup.sh"
|
||||||
|
|
||||||
# Disassembly rules ---------------------------------------------------
|
# Disassembly rules ---------------------------------------------------
|
||||||
disassemble:
|
disassemble: check_environment
|
||||||
rm -rf $(BUILDROOT)/output/images/disassembly
|
rm -rf $(BUILDROOT)/output/images/disassembly
|
||||||
find $(BUILDROOT)/output/build/linux-* -maxdepth 1 -name "vmlinux" | xargs cp -t $(BUILDROOT)/output/images/
|
find $(BUILDROOT)/output/build/linux-* -maxdepth 1 -name "vmlinux" | xargs cp -t $(BUILDROOT)/output/images/
|
||||||
mkdir -p $(DIS)
|
mkdir -p $(DIS)
|
||||||
@ -114,9 +121,6 @@ $(BUILDROOT):
|
|||||||
|
|
||||||
# ---------------------------------------------------------------------
|
# ---------------------------------------------------------------------
|
||||||
|
|
||||||
cleanDriver:
|
|
||||||
rm -f $(DRIVER)
|
|
||||||
|
|
||||||
cleanDTB:
|
cleanDTB:
|
||||||
rm -f $(IMAGES)/*.dtb
|
rm -f $(IMAGES)/*.dtb
|
||||||
|
|
||||||
|
|||||||
@ -12,23 +12,31 @@
|
|||||||
|
|
||||||
In order to generate the Linux and boot stage binaries compatible with Wally, Buildroot is used for cross-compilation.
|
In order to generate the Linux and boot stage binaries compatible with Wally, Buildroot is used for cross-compilation.
|
||||||
|
|
||||||
To set up a Buildroot directory, configuration files for Buildroot, Linux, and Busybox must be copied into the correct locations inside the main Buildroot directory. Buildroot and device tree binaries must be generated as well. This can all be done automatically using the Makefile inside Wally's Linux subdirectory (this one). To install a new buildroot directory, build the Buildroot binaries, generate the device tree binaries, generate test-vectors for simulation, and install the buildroot package needed to build the SD card driver for Linux, run:
|
To set up a Buildroot directory, configuration files for Buildroot, Linux, and Busybox must be copied into the correct locations inside the main Buildroot directory. Buildroot and device tree binaries must be generated as well.
|
||||||
|
|
||||||
$ make
|
This can all be done automatically using the Makefile inside Wally's Linux subdirectory (this one). The main Wally installation script (`bin/wally-tool-chain-install.sh`) runs this by default, so buildroot is likely already setup. Otherwise, to install a new buildroot directory, build the Buildroot binaries, generate the device tree binaries, and generate testvectors for simulation run:
|
||||||
|
|
||||||
|
```bash
|
||||||
|
$ make
|
||||||
|
```
|
||||||
|
|
||||||
This installs to the `$RISCV` directory. Buildroot itself is installed to `$RISCV/buildroot` and the test-vectors are installed to `$RISCV/linux-testvectors`.
|
This installs to the `$RISCV` directory. Buildroot itself is installed to `$RISCV/buildroot` and the test-vectors are installed to `$RISCV/linux-testvectors`.
|
||||||
|
|
||||||
Optionally, you can override the `BUILDROOT` variable to install a different buildroot source directory.
|
Optionally, you can override the `BUILDROOT` variable to install a different buildroot source directory.
|
||||||
|
|
||||||
$ make install BUILDROOT=path/to/buildroot
|
```bash
|
||||||
|
$ make install BUILDROOT=<path/to/buildroot>
|
||||||
|
```
|
||||||
|
|
||||||
## Generating Device Tree Binaries <a name="devicetree"></a>
|
## Generating Device Tree Binaries <a name="devicetree"></a>
|
||||||
|
|
||||||
The device tree files for the various FPGA's Wally supports, as well as QEMU's device tree for the virt machine, are located in the `./devicetree` subdirectory. These device tree files are necessary for the boot process.
|
The device tree files for the various FPGAs Wally supports, as well as QEMU's device tree for the virt machine, are located in the `./devicetree` subdirectory. These device tree files are necessary for the boot process.
|
||||||
|
|
||||||
They are built automatically using the main `make` command. To build the device tree binaries (.dtb) from the device tree sources (.dts) separately, we can build all of them at once using:
|
They are built automatically using the main `make` command. To build the device tree binaries (.dtb) from the device tree sources (.dts) separately, we can build all of them at once using:
|
||||||
|
|
||||||
$ make generate #optionally override BUILDROOT
|
```bash
|
||||||
|
$ make generate # optionally override BUILDROOT
|
||||||
|
```
|
||||||
|
|
||||||
The .dts files will end up in the `<BUILDROOT>/output/images` folder of your chosen buildroot directory.
|
The .dts files will end up in the `<BUILDROOT>/output/images` folder of your chosen buildroot directory.
|
||||||
|
|
||||||
@ -38,23 +46,30 @@ By using the `riscv64-unknown-elf-objdump` utility, we can disassemble the binar
|
|||||||
|
|
||||||
The disassembled binaries are built automatically using the main `make` command. To create the disassembled binaries separately, run:
|
The disassembled binaries are built automatically using the main `make` command. To create the disassembled binaries separately, run:
|
||||||
|
|
||||||
$ make disassemble #optionally override BUILDROOT
|
```bash
|
||||||
|
$ make disassemble # optionally override BUILDROOT
|
||||||
|
```
|
||||||
|
|
||||||
You'll find the resulting disassembled files in `<BUILDROOT>/output/images/disassembly`.
|
You'll find the resulting disassembled files in `<BUILDROOT>/output/images/disassembly`.
|
||||||
|
|
||||||
## Generate Memory Files for Linux Boot <a name="testvectors"></a>
|
## Generate Memory Files for Linux Boot <a name="testvectors"></a>
|
||||||
|
|
||||||
Running a linux boot simulation uses a preloaded bootrom and ram memory. We use QEMU to generate these preloaded memory files. The files are output to $RISCV/linux-testvectors. The memory files are generated automatically when using the main `make` command. Alternatively, they can be generated by running
|
Running a linux boot simulation uses a preloaded bootrom and ram memory. We use QEMU to generate these preloaded memory files. The files are output to `$RISCV/linux-testvectors`. The memory files are generated automatically when using the main `make` command. Alternatively, they can be generated by running
|
||||||
|
|
||||||
make dumptvs
|
```bash
|
||||||
|
$ make dumptvs
|
||||||
|
```
|
||||||
|
|
||||||
## Creating a Bootable SD Card <a name="sdcard"></a>
|
## Creating a Bootable SD Card <a name="sdcard"></a>
|
||||||
|
|
||||||
To flash a bootable sd card for Wally's bootloader, use the `flash-sd.sh` script located in `<WALLY>/linux/sdcard`. The script allows you to specify which buildroot directory you would like to use and to specify the device tree. By default it is set up for the default location of buildroot in `$RISCV` and uses the vcu108 device tree. To use the script with your own buildroot directory and device tree, type:
|
To flash a bootable sd card for Wally's bootloader, use the `flash-sd.sh` script located in `<WALLY>/linux/sdcard`. The script allows you to specify which buildroot directory you would like to use and to specify the device tree. By default it is set up for the default location of buildroot in `$RISCV` and uses the vcu108 device tree. To use the script with your own buildroot directory and device tree, type:
|
||||||
|
|
||||||
$ cd sdcard
|
```bash
|
||||||
$ ./flash-sd.sh -b <path/to/buildroot> -d <device tree name> <DEVICE>
|
$ cd sdcard
|
||||||
|
$ ./flash-sd.sh -b <path/to/buildroot> -d <device tree name> <DEVICE>
|
||||||
|
```
|
||||||
|
|
||||||
for example
|
for example
|
||||||
|
```bash
|
||||||
$ ./flash-sd.sh -b ~/repos/buildroot -d wally-vcu118.dtb /dev/sdb
|
$ ./flash-sd.sh -b ~/repos/buildroot -d wally-vcu118.dtb /dev/sdb
|
||||||
|
```
|
||||||
|
|||||||
10
sim/Makefile
10
sim/Makefile
@ -27,7 +27,7 @@ deriv:
|
|||||||
|
|
||||||
|
|
||||||
|
|
||||||
.PHONY: QuestaCodeCoverage QuestaFunctCoverageRvvi collect_functcov combine_functcov remove_functcov_artifacts riscvdv riscvdv_functcov
|
.PHONY: QuestaCodeCoverage collect_functcov combine_functcov remove_functcov_artifacts riscvdv riscvdv_functcov
|
||||||
|
|
||||||
QuestaCodeCoverage: questa/ucdb/rv64gc_arch64i.ucdb
|
QuestaCodeCoverage: questa/ucdb/rv64gc_arch64i.ucdb
|
||||||
vcover merge -out questa/ucdb/cov.ucdb questa/ucdb/rv64gc_arch64i.ucdb questa/ucdb/rv64gc*.ucdb -logfile questa/cov/log
|
vcover merge -out questa/ucdb/cov.ucdb questa/ucdb/rv64gc_arch64i.ucdb questa/ucdb/rv64gc*.ucdb -logfile questa/cov/log
|
||||||
@ -51,14 +51,6 @@ QuestaCodeCoverage: questa/ucdb/rv64gc_arch64i.ucdb
|
|||||||
# vcover report -recursive questa/ucdb/cov.ucdb > questa/cov/rv64gc_recursive.rpt
|
# vcover report -recursive questa/ucdb/cov.ucdb > questa/cov/rv64gc_recursive.rpt
|
||||||
vcover report -details -threshH 100 -html questa/ucdb/cov.ucdb
|
vcover report -details -threshH 100 -html questa/ucdb/cov.ucdb
|
||||||
|
|
||||||
QuestaFunctCoverageRvvi: ${WALLY}/addins/cvw-arch-verif/work/rv64gc_arch64i.ucdb
|
|
||||||
vcover merge -out ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb ${WALLY}/addins/cvw-arch-verif/work/rv64gc_arch64i.ucdb ${WALLY}/addins/cvw-arch-verif/work/rv64gc_*.ucdb -logfile ${SIM}/questa/fcovrvvi/log
|
|
||||||
vcover report -details -html ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb
|
|
||||||
vcover report ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb -details -cvg > ${SIM}/questa/fcovrvvi/fcovrvvi.log
|
|
||||||
vcover report ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb -testdetails -cvg > ${SIM}/questa/fcovrvvi/fcovrvvi.testdetails.log
|
|
||||||
vcover report ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb -details -cvg | egrep "Coverpoint|Covergroup|Cross|TYPE" > ${SIM}/questa/fcovrvvi/fcovrvvi.summary.log
|
|
||||||
grep "TOTAL COVERGROUP COVERAGE" ${SIM}/questa/fcovrvvi/fcovrvvi.log
|
|
||||||
|
|
||||||
collect_functcov: remove_functcov_artifacts riscvdv_functcov combine_functcov
|
collect_functcov: remove_functcov_artifacts riscvdv_functcov combine_functcov
|
||||||
|
|
||||||
riscvdv_functcov:
|
riscvdv_functcov:
|
||||||
|
|||||||
@ -51,8 +51,6 @@ if [file exists ${WKDIR}] {
|
|||||||
vdel -lib ${WKDIR} -all
|
vdel -lib ${WKDIR} -all
|
||||||
}
|
}
|
||||||
vlib ${WKDIR}
|
vlib ${WKDIR}
|
||||||
# Create directory for functional coverage data
|
|
||||||
mkdir -p ${FCRVVI}
|
|
||||||
|
|
||||||
set PlusArgs ""
|
set PlusArgs ""
|
||||||
set ParamArgs ""
|
set ParamArgs ""
|
||||||
@ -62,9 +60,6 @@ set ccov 0
|
|||||||
set CoverageVoptArg ""
|
set CoverageVoptArg ""
|
||||||
set CoverageVsimArg ""
|
set CoverageVsimArg ""
|
||||||
|
|
||||||
set FuncCovRVVI 0
|
|
||||||
set FCdefineRVVI_COVERAGE ""
|
|
||||||
|
|
||||||
set FunctCoverage 0
|
set FunctCoverage 0
|
||||||
set FCvlog ""
|
set FCvlog ""
|
||||||
set FCvopt ""
|
set FCvopt ""
|
||||||
@ -108,12 +103,6 @@ if {[lcheck lst "--ccov"]} {
|
|||||||
set CoverageVsimArg "-coverage"
|
set CoverageVsimArg "-coverage"
|
||||||
}
|
}
|
||||||
|
|
||||||
# if --fcovrvvi found set flag and remove from list
|
|
||||||
if {[lcheck lst "--fcovrvvi"]} {
|
|
||||||
set FuncCovRVVI 1
|
|
||||||
set FCdefineRVVI_COVERAGE "+define+RVVI_COVERAGE"
|
|
||||||
}
|
|
||||||
|
|
||||||
# if --fcovimp found set flag and remove from list
|
# if --fcovimp found set flag and remove from list
|
||||||
if {[lcheck lst "--fcovimp"]} {
|
if {[lcheck lst "--fcovimp"]} {
|
||||||
set FunctCoverage 1
|
set FunctCoverage 1
|
||||||
@ -138,11 +127,12 @@ if {[lcheck lst "--fcovimp"]} {
|
|||||||
if {[lcheck lst "--fcov"]} {
|
if {[lcheck lst "--fcov"]} {
|
||||||
set FunctCoverage 1
|
set FunctCoverage 1
|
||||||
# COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but no longer affects tests
|
# COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but no longer affects tests
|
||||||
set FCvlog "+define+INCLUDE_TRACE2COV \
|
set FCvlog "+define+INCLUDE_TRACE2COV \
|
||||||
+define+IDV_INCLUDE_TRACE2COV \
|
+define+IDV_INCLUDE_TRACE2COV \
|
||||||
+define+COVER_BASE_RV32I \
|
+define+COVER_BASE_RV32I \
|
||||||
+incdir+$env(WALLY)/addins/riscvISACOV/source \
|
+incdir+$env(WALLY)/addins/riscvISACOV/source \
|
||||||
"
|
"
|
||||||
|
|
||||||
set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1"
|
set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1"
|
||||||
|
|
||||||
}
|
}
|
||||||
@ -181,7 +171,6 @@ if {$DEBUG > 0} {
|
|||||||
echo "GUI = $GUI"
|
echo "GUI = $GUI"
|
||||||
echo "ccov = $ccov"
|
echo "ccov = $ccov"
|
||||||
echo "lockstep = $lockstep"
|
echo "lockstep = $lockstep"
|
||||||
echo "FuncCovRVVI = $FuncCovRVVI"
|
|
||||||
echo "FunctCoverage = $FunctCoverage"
|
echo "FunctCoverage = $FunctCoverage"
|
||||||
echo "remaining list = $lst"
|
echo "remaining list = $lst"
|
||||||
echo "Extra +args = $PlusArgs"
|
echo "Extra +args = $PlusArgs"
|
||||||
@ -194,7 +183,7 @@ if {$DEBUG > 0} {
|
|||||||
# because vsim will run vopt
|
# because vsim will run vopt
|
||||||
set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}"
|
set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}"
|
||||||
set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv"
|
set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv"
|
||||||
vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286
|
vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286
|
||||||
|
|
||||||
# start and run simulation
|
# start and run simulation
|
||||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||||
@ -220,11 +209,6 @@ if {$FunctCoverage} {
|
|||||||
coverage save -onexit ${UCDB}
|
coverage save -onexit ${UCDB}
|
||||||
}
|
}
|
||||||
|
|
||||||
if {$FuncCovRVVI} {
|
|
||||||
set UCDB ${WALLY}/addins/cvw-arch-verif/work/${CFG}_${TESTSUITE}.ucdb
|
|
||||||
coverage save -onexit ${UCDB}
|
|
||||||
}
|
|
||||||
|
|
||||||
run -all
|
run -all
|
||||||
|
|
||||||
if {$ccov} {
|
if {$ccov} {
|
||||||
|
|||||||
@ -221,8 +221,8 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
|
|||||||
SPI_DELAY0: Dout <= {8'b0, Delay0[15:8], 8'b0, Delay0[7:0]};
|
SPI_DELAY0: Dout <= {8'b0, Delay0[15:8], 8'b0, Delay0[7:0]};
|
||||||
SPI_DELAY1: Dout <= {8'b0, Delay1[15:8], 8'b0, Delay1[7:0]};
|
SPI_DELAY1: Dout <= {8'b0, Delay1[15:8], 8'b0, Delay1[7:0]};
|
||||||
SPI_FMT: Dout <= {12'b0, Format[4:1], 13'b0, Format[0], 2'b0};
|
SPI_FMT: Dout <= {12'b0, Format[4:1], 13'b0, Format[0], 2'b0};
|
||||||
SPI_TXDATA: Dout <= {23'b0, TransmitFIFOWriteFull, 8'b0};
|
SPI_TXDATA: Dout <= {TransmitFIFOWriteFull, 23'b0, 8'b0};
|
||||||
SPI_RXDATA: Dout <= {23'b0, ReceiveFIFOReadEmpty, ReceiveData[7:0]};
|
SPI_RXDATA: Dout <= {ReceiveFIFOReadEmpty, 23'b0, ReceiveData[7:0]};
|
||||||
SPI_TXMARK: Dout <= {29'b0, TransmitWatermark};
|
SPI_TXMARK: Dout <= {29'b0, TransmitWatermark};
|
||||||
SPI_RXMARK: Dout <= {29'b0, ReceiveWatermark};
|
SPI_RXMARK: Dout <= {29'b0, ReceiveWatermark};
|
||||||
SPI_IE: Dout <= {30'b0, InterruptEnable};
|
SPI_IE: Dout <= {30'b0, InterruptEnable};
|
||||||
|
|||||||
@ -1,42 +1,39 @@
|
|||||||
Synthesis for RISC-V Microprocessor System-on-Chip Design
|
# Synthesis for RISC-V Microprocessor System-on-Chip Design
|
||||||
|
|
||||||
This subdirectory contains synthesis scripts for use with Synopsys
|
This subdirectory contains synthesis scripts for use with Synopsys
|
||||||
(snps) Design Compiler (DC). Synthesis commands are found in
|
(snps) Design Compiler (DC). Synthesis commands are found in
|
||||||
scripts/synth.tcl.
|
`scripts/synth.tcl`.
|
||||||
|
|
||||||
Example Usage
|
## Example Usage
|
||||||
|
```bash
|
||||||
make synth DESIGN=wallypipelinedcore FREQ=500 CONFIG=rv32e
|
make synth DESIGN=wallypipelinedcore FREQ=500 CONFIG=rv32e
|
||||||
|
```
|
||||||
|
|
||||||
environment variables
|
## Environment Variables
|
||||||
|
|
||||||
DESIGN
|
- `DESIGN`
|
||||||
Design provides the name of the output log. Default is synth.
|
- Design provides the name of the output log. Default is synth.
|
||||||
|
- `FREQ`
|
||||||
|
- Frequency in MHz. Default is 500
|
||||||
|
- `CONFIG`
|
||||||
|
- The Wally configuration file. The default is rv32e.
|
||||||
|
- Examples: rv32e, rv64gc, rv32gc
|
||||||
|
- `TECH`
|
||||||
|
- The target standard cell library. The default is sky130.
|
||||||
|
- Options:
|
||||||
|
- sky90: skywater 90nm TT 25C
|
||||||
|
- sky130: skywater 130nm TT 25C
|
||||||
|
- `SAIFPOWER`
|
||||||
|
- Controls if power analysis is driven by switching factor or RTL modelsim simulation. When enabled requires a saif file named power.saif. The default is 0.
|
||||||
|
- Options:
|
||||||
|
- 0: switching factor power analysis
|
||||||
|
- 1: RTL simulation driven power analysis.
|
||||||
|
|
||||||
FREQ
|
## Extra Tool (PPA)
|
||||||
Frequency in MHz. Default is 500
|
|
||||||
|
|
||||||
CONFIG
|
|
||||||
The Wally configuration file. The default is rv32e.
|
|
||||||
Examples: rv32e, rv64gc, rv32gc
|
|
||||||
|
|
||||||
TECH
|
|
||||||
The target standard cell library. The default is sky130.
|
|
||||||
sky90: skywater 90nm TT 25C
|
|
||||||
sky130: skywater 130nm TT 25C
|
|
||||||
|
|
||||||
SAIFPOWER
|
|
||||||
Controls if power analysis is driven by switching factor or
|
|
||||||
RTL modelsim simulation. When enabled requires a saif file
|
|
||||||
named power.saif. The default is 0.
|
|
||||||
0: switching factor power analysis
|
|
||||||
1: RTL simulation driven power analysis.
|
|
||||||
|
|
||||||
-----
|
|
||||||
Extra Tool (PPA)
|
|
||||||
|
|
||||||
To run ppa analysis that hones into target frequency, you can type:
|
To run ppa analysis that hones into target frequency, you can type:
|
||||||
python3 ppa/ppaSynth.py from the synthDC directory. This runs a sweep
|
`python3 ppa/ppaSynth.py` from the synthDC directory. This runs a sweep
|
||||||
across all modules listed at the bottom of the ppaSynth.py file.
|
across all modules listed at the bottom of the `ppaSynth.py` file.
|
||||||
|
|
||||||
Two options for running the sweep. The first run runs all modules for
|
Two options for running the sweep. The first run runs all modules for
|
||||||
all techs around a given frequency (i.e., freqs). The second option
|
all techs around a given frequency (i.e., freqs). The second option
|
||||||
@ -44,19 +41,21 @@ will run all designs for the specific module based on bestSynths.csv
|
|||||||
values. Since the second option is 2nd, it has priority. If the
|
values. Since the second option is 2nd, it has priority. If the
|
||||||
second set of values is commented out, it will run all widths.
|
second set of values is commented out, it will run all widths.
|
||||||
|
|
||||||
WARNING: The first option may runs lots of runs that could expend all
|
**WARNING:** The first option may runs lots of runs that could expend all the licenses available for a license. Therefore, care must be taken to be sure that enough licenses are available for this first option.
|
||||||
the licenses available for a license. Therefore, care must be taken
|
|
||||||
to be sure that enough licenses are available for this first option.
|
|
||||||
|
|
||||||
##### Run specific syntheses
|
### Run specific syntheses
|
||||||
widths = [8, 16, 32, 64, 128]
|
```python
|
||||||
modules = ['mul', 'adder', 'shifter', 'flop', 'comparator', 'binencoder', 'csa', 'mux2', 'mux4', 'mux8']
|
widths = [8, 16, 32, 64, 128]
|
||||||
techs = ['sky90', 'sky130', 'tsmc28', 'tsmc28psyn']
|
modules = ['mul', 'adder', 'shifter', 'flop', 'comparator', 'binencoder', 'csa', 'mux2', 'mux4', 'mux8']
|
||||||
freqs = [5000]
|
techs = ['sky90', 'sky130', 'tsmc28', 'tsmc28psyn']
|
||||||
synthsToRun = allCombos(widths, modules, techs, freqs)
|
freqs = [5000]
|
||||||
|
synthsToRun = allCombos(widths, modules, techs, freqs)
|
||||||
|
```
|
||||||
|
|
||||||
##### Run a sweep based on best delay found in existing syntheses
|
### Run a sweep based on best delay found in existing syntheses
|
||||||
module = 'adder'
|
```python
|
||||||
width = 32
|
module = 'adder'
|
||||||
tech = 'tsmc28psyn'
|
width = 32
|
||||||
synthsToRun = freqSweep(module, width, tech)
|
tech = 'tsmc28psyn'
|
||||||
|
synthsToRun = freqSweep(module, width, tech)
|
||||||
|
```
|
||||||
|
|||||||
@ -1,35 +1,43 @@
|
|||||||
CEXT := c
|
# Disable builtin rules because they are a shorter (but incorrect) path that Make will use by default
|
||||||
CPPEXT := cpp
|
MAKEFLAGS += --no-builtin-rules
|
||||||
AEXT := s
|
SRCDIR := .
|
||||||
SEXT := S
|
SRCEXT := S
|
||||||
SRCEXT := \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\)
|
AEXT := s
|
||||||
#SRCS = $(wildcard *.S)
|
OBJEXT := o
|
||||||
#PROGS = $(patsubst %.S,%,$(SRCS))
|
EXEEXT := elf
|
||||||
SRCDIR = .
|
|
||||||
SRCEXT = S
|
|
||||||
SOURCES ?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort)
|
SOURCES ?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort)
|
||||||
OBJEXT = elf
|
ELFS := $(SOURCES:.$(SRCEXT)=.$(EXEEXT))
|
||||||
OBJECTS := $(SOURCES:.$(SEXT)=.$(OBJEXT))
|
OBJDUMPS := $(addsuffix .objdump, $(ELFS))
|
||||||
|
MEMFILES := $(addsuffix .memfile, $(ELFS))
|
||||||
|
|
||||||
all: $(OBJECTS)
|
all: $(OBJDUMPS) $(MEMFILES)
|
||||||
|
|
||||||
|
# Create dissassembly
|
||||||
%.elf.objdump: %.elf
|
%.elf.objdump: %.elf
|
||||||
|
riscv64-unknown-elf-objdump -S -D $< > $@
|
||||||
|
extractFunctionRadix.sh $@
|
||||||
|
|
||||||
# Change many things if bit width isn't 64
|
# Create memfile
|
||||||
%.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile
|
%.elf.memfile: %.elf
|
||||||
riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 -mcmodel=medany \
|
riscv64-unknown-elf-elf2hex --bit-width 64 --input $< --output $@
|
||||||
-nostartfiles -T../../examples/link/link.ld $<
|
|
||||||
riscv64-unknown-elf-objdump -S -D $@ > $@.objdump
|
# Link object file to create executable
|
||||||
riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile
|
.PRECIOUS: %.$(EXEEXT)
|
||||||
extractFunctionRadix.sh $@.objdump
|
%.$(EXEEXT): %.$(OBJEXT)
|
||||||
|
riscv64-unknown-elf-gcc -g -o $@ -mcmodel=medany -nostartfiles -T../../examples/link/link.ld $*.o
|
||||||
sim: %.elf
|
|
||||||
|
# Assemble into object files
|
||||||
|
%.$(OBJEXT): %.$(AEXT)
|
||||||
|
riscv64-unknown-elf-as -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 $<
|
||||||
|
|
||||||
|
# Preprocess assembly files
|
||||||
|
%.$(AEXT): %.$(SRCEXT) WALLY-init-lib.h
|
||||||
|
riscv64-unknown-elf-gcc -E -g -o $@ $<
|
||||||
|
|
||||||
|
sim: %.$(EXEEXT)
|
||||||
spike +signature=%.signature.output +signature-granularity=8 %.elf
|
spike +signature=%.signature.output +signature-granularity=8 %.elf
|
||||||
diff --ignore-case %.signature.output %.reference_output || exit
|
diff --ignore-case %.signature.output %.reference_output || exit
|
||||||
echo "Signature matches! Success!"
|
echo "Signature matches! Success!"
|
||||||
|
|
||||||
clean:
|
clean:
|
||||||
rm -f *.elf *.objdump *.signature.output *.addr *.lab *.memfile
|
rm -f *.elf *.objdump *.signature.output *.addr *.lab *.memfile *.o *.s
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@ -7,20 +7,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -47,21 +47,21 @@ rvtest_entry_point:
|
|||||||
csrw medeleg, zero # Don't delegate exceptions
|
csrw medeleg, zero # Don't delegate exceptions
|
||||||
# li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again
|
# li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again
|
||||||
# li t1, 0x02004000 # MTIMECMP in CLINT
|
# li t1, 0x02004000 # MTIMECMP in CLINT
|
||||||
# sd t0, 0(t1)
|
# sd t0, 0(t1)
|
||||||
li t0, 0x80
|
li t0, 0x80
|
||||||
# li t0, 0x00
|
# li t0, 0x00
|
||||||
csrw mie, t0 # Enable machine timer interrupt
|
csrw mie, t0 # Enable machine timer interrupt
|
||||||
la t0, topoftrapstack
|
la t0, topoftrapstack
|
||||||
csrw mscratch, t0 # MSCRATCH holds trap stack pointer
|
csrw mscratch, t0 # MSCRATCH holds trap stack pointer
|
||||||
csrsi mstatus, 0x8 # Turn on mstatus.MIE global interrupt enable
|
csrsi mstatus, 0x8 # Turn on mstatus.MIE global interrupt enable
|
||||||
# set up PMP so user and supervisor mode can access full address space
|
# set up PMP so user and supervisor mode can access full address space
|
||||||
csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX
|
csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX
|
||||||
li t0, 0xFFFFFFFF
|
li t0, 0xFFFFFFFF
|
||||||
csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
|
csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
|
||||||
j main # Call main function in user test program
|
j main # Call main function in user test program
|
||||||
|
|
||||||
done:
|
done:
|
||||||
li a0, 4 # argument to finish program
|
li a0, 4 # argument to finish program
|
||||||
ecall # system call to finish program
|
ecall # system call to finish program
|
||||||
j self_loop # wait forever (not taken)
|
j self_loop # wait forever (not taken)
|
||||||
|
|
||||||
@ -75,11 +75,11 @@ trap_handler:
|
|||||||
csrr t1, mtval # And the trap value
|
csrr t1, mtval # And the trap value
|
||||||
bgez t0, exception # if msb is clear, it is an exception
|
bgez t0, exception # if msb is clear, it is an exception
|
||||||
|
|
||||||
interrupt: # must be a timer interrupt
|
interrupt: # must be a timer interrupt
|
||||||
li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again
|
li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again
|
||||||
li t1, 0x02004000 # MTIMECMP in CLIN
|
li t1, 0x02004000 # MTIMECMP in CLIN
|
||||||
sd t0, 0(t1)
|
sd t0, 0(t1)
|
||||||
csrw stimecmp, t0 # sets stimecmp to big number so it doesnt interrupt
|
csrw stimecmp, t0 # sets stimecmp to big number so it doesnt interrupt
|
||||||
li t0, 32
|
li t0, 32
|
||||||
csrc sip, t0 # clears stimer interrupt
|
csrc sip, t0 # clears stimer interrupt
|
||||||
j trap_return # clean up and return
|
j trap_return # clean up and return
|
||||||
@ -105,7 +105,7 @@ changeprivilege:
|
|||||||
|
|
||||||
trap_return: # return from trap handler
|
trap_return: # return from trap handler
|
||||||
csrr t0, mepc # get address of instruction that caused exception
|
csrr t0, mepc # get address of instruction that caused exception
|
||||||
li t1, 0x20000
|
li t1, 0x20000
|
||||||
csrs mstatus, t1 # set mprv bit to fetch instruction with permission of code that trapped
|
csrs mstatus, t1 # set mprv bit to fetch instruction with permission of code that trapped
|
||||||
lh t0, 0(t0) # get instruction that caused exception
|
lh t0, 0(t0) # get instruction that caused exception
|
||||||
csrc mstatus, t1 # clear mprv bit to restore normal operation
|
csrc mstatus, t1 # clear mprv bit to restore normal operation
|
||||||
@ -145,8 +145,8 @@ setmsb:
|
|||||||
slli a0, a0, 16 # use two shifts of 16 bits each to be compatible with compiling either RV32 or 64
|
slli a0, a0, 16 # use two shifts of 16 bits each to be compatible with compiling either RV32 or 64
|
||||||
setmsbdone:
|
setmsbdone:
|
||||||
ret # return to calller
|
ret # return to calller
|
||||||
|
|
||||||
.section .tohost
|
.section .tohost
|
||||||
tohost: # write to HTIF
|
tohost: # write to HTIF
|
||||||
.dword 0
|
.dword 0
|
||||||
fromhost:
|
fromhost:
|
||||||
@ -154,7 +154,7 @@ fromhost:
|
|||||||
|
|
||||||
.EQU XLEN,64
|
.EQU XLEN,64
|
||||||
begin_signature:
|
begin_signature:
|
||||||
.fill 6*(XLEN/32),4,0xdeadbeef #
|
.fill 6*(XLEN/32),4,0xdeadbeef #
|
||||||
end_signature:
|
end_signature:
|
||||||
|
|
||||||
scratch:
|
scratch:
|
||||||
@ -165,7 +165,7 @@ scratch:
|
|||||||
.space 512
|
.space 512
|
||||||
topofstack:
|
topofstack:
|
||||||
# And another stack for the trap handler
|
# And another stack for the trap handler
|
||||||
.bss
|
.bss
|
||||||
.space 512
|
.space 512
|
||||||
topoftrapstack:
|
topoftrapstack:
|
||||||
|
|
||||||
|
|||||||
@ -7,20 +7,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -40,7 +40,7 @@ main:
|
|||||||
li t2, 2
|
li t2, 2
|
||||||
li t3, 3
|
li t3, 3
|
||||||
amoadd.d t3, t2, (t1)
|
amoadd.d t3, t2, (t1)
|
||||||
|
|
||||||
fence.I
|
fence.I
|
||||||
|
|
||||||
finished:
|
finished:
|
||||||
|
|||||||
@ -7,20 +7,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -44,7 +44,7 @@ main:
|
|||||||
li a0, 1
|
li a0, 1
|
||||||
ecall # enter supervisor mode
|
ecall # enter supervisor mode
|
||||||
|
|
||||||
li a0, 0
|
li a0, 0
|
||||||
ecall # enter user mode
|
ecall # enter user mode
|
||||||
|
|
||||||
li a0, 1
|
li a0, 1
|
||||||
|
|||||||
@ -4,23 +4,23 @@
|
|||||||
# Written: avercruysse@hmc.edu 18 April 2023
|
# Written: avercruysse@hmc.edu 18 April 2023
|
||||||
#
|
#
|
||||||
# Purpose: Test Coverage for D$
|
# Purpose: Test Coverage for D$
|
||||||
# (For each way, trigger a CacheDataMem write enable while chip enable is low)
|
# (For each way, trigger a CacheDataMem write enable while chip enable is low)
|
||||||
#
|
#
|
||||||
# A component of the CORE-V-WALLY configurable RISC-V project.
|
# A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
#
|
#
|
||||||
# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
#
|
#
|
||||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
#
|
#
|
||||||
# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
# except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
# except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
# may obtain a copy of the License at
|
# may obtain a copy of the License at
|
||||||
#
|
#
|
||||||
# https://solderpad.org/licenses/SHL-2.1/
|
# https://solderpad.org/licenses/SHL-2.1/
|
||||||
#
|
#
|
||||||
# Unless required by applicable law or agreed to in writing, any work distributed under the
|
# Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
# either express or implied. See the License for the specific language governing permissions
|
# either express or implied. See the License for the specific language governing permissions
|
||||||
# and limitations under the License.
|
# and limitations under the License.
|
||||||
################################################
|
################################################
|
||||||
|
|
||||||
@ -28,7 +28,7 @@ import os
|
|||||||
|
|
||||||
test_name = "dcache1.S"
|
test_name = "dcache1.S"
|
||||||
dcache_num_ways = 4
|
dcache_num_ways = 4
|
||||||
dcache_way_size_in_bytes = 4096
|
dcache_way_size_in_bytes = 4096
|
||||||
# warning i$ line size is not currently parameterized.
|
# warning i$ line size is not currently parameterized.
|
||||||
|
|
||||||
# arbitrary start location of where I send stores to.
|
# arbitrary start location of where I send stores to.
|
||||||
@ -48,7 +48,7 @@ def wl(line="", comment=None, fname=test_name):
|
|||||||
to_write = " " * indent + line + comment + "\n"
|
to_write = " " * indent + line + comment + "\n"
|
||||||
f.write(to_write)
|
f.write(to_write)
|
||||||
|
|
||||||
|
|
||||||
def write_repro_instrs():
|
def write_repro_instrs():
|
||||||
"""
|
"""
|
||||||
Assumes that the store location has been fetched to d$, and is in t0.
|
Assumes that the store location has been fetched to d$, and is in t0.
|
||||||
@ -72,7 +72,7 @@ if __name__ == "__main__":
|
|||||||
wl(comment="This file is generated by dcache1.py (run that script manually)")
|
wl(comment="This file is generated by dcache1.py (run that script manually)")
|
||||||
wl('#include "WALLY-init-lib.h"')
|
wl('#include "WALLY-init-lib.h"')
|
||||||
wl('main:')
|
wl('main:')
|
||||||
|
|
||||||
# excercise all 4 D$ ways. If they're not all full, it uses the first empty.
|
# excercise all 4 D$ ways. If they're not all full, it uses the first empty.
|
||||||
# So we are sure all 4 ways are exercised.
|
# So we are sure all 4 ways are exercised.
|
||||||
for i in range(dcache_num_ways):
|
for i in range(dcache_num_ways):
|
||||||
@ -82,5 +82,5 @@ if __name__ == "__main__":
|
|||||||
wl(comment=f"i$ boundary, way test #{i+1}")
|
wl(comment=f"i$ boundary, way test #{i+1}")
|
||||||
write_repro_instrs()
|
write_repro_instrs()
|
||||||
mem_addr += dcache_way_size_in_bytes # so that we excercise a new D$ way.
|
mem_addr += dcache_way_size_in_bytes # so that we excercise a new D$ way.
|
||||||
|
|
||||||
wl("j done")
|
wl("j done")
|
||||||
|
|||||||
@ -4,47 +4,47 @@
|
|||||||
// Written: avercruysse@hmc.edu 18 April 2023
|
// Written: avercruysse@hmc.edu 18 April 2023
|
||||||
//
|
//
|
||||||
// Purpose: Test Coverage for D$
|
// Purpose: Test Coverage for D$
|
||||||
// (for all 4 cache ways, trigger a FlushStage while SetDirtyWay=1)
|
// (for all 4 cache ways, trigger a FlushStage while SetDirtyWay=1)
|
||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
#include "WALLY-init-lib.h"
|
#include "WALLY-init-lib.h"
|
||||||
main:
|
main:
|
||||||
// way 0
|
// way 0
|
||||||
li t0, 0x80100770
|
li t0, 0x80100770
|
||||||
sd zero, 0(t0)
|
sd zero, 0(t0)
|
||||||
sd zero, 1(t0)
|
sd zero, 1(t0)
|
||||||
|
|
||||||
// way 1
|
// way 1
|
||||||
li t0, 0x80101770
|
li t0, 0x80101770
|
||||||
sd zero, 0(t0)
|
sd zero, 0(t0)
|
||||||
sd zero, 1(t0)
|
sd zero, 1(t0)
|
||||||
|
|
||||||
// way 2
|
// way 2
|
||||||
li t0, 0x80102770
|
li t0, 0x80102770
|
||||||
sd zero, 0(t0)
|
sd zero, 0(t0)
|
||||||
sd zero, 1(t0)
|
sd zero, 1(t0)
|
||||||
|
|
||||||
// way 3
|
// way 3
|
||||||
li t0, 0x80103770
|
li t0, 0x80103770
|
||||||
sd zero, 0(t0)
|
sd zero, 0(t0)
|
||||||
sd zero, 1(t0)
|
sd zero, 1(t0)
|
||||||
|
|
||||||
j done
|
j done
|
||||||
|
|||||||
@ -7,20 +7,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -36,22 +36,22 @@ main:
|
|||||||
csrs menvcfg, t5 # menvcfg.PBMTE = 1, CBZE, CBCFE, CBIE all 1
|
csrs menvcfg, t5 # menvcfg.PBMTE = 1, CBZE, CBCFE, CBIE all 1
|
||||||
|
|
||||||
# Page table root address at 0x80010000; SV48
|
# Page table root address at 0x80010000; SV48
|
||||||
li t5, 0x9000000000080010
|
li t5, 0x9000000000080010
|
||||||
csrw satp, t5
|
csrw satp, t5
|
||||||
|
|
||||||
# sfence.vma x0, x0
|
# sfence.vma x0, x0
|
||||||
|
|
||||||
# switch to supervisor mode
|
# switch to supervisor mode
|
||||||
li a0, 1
|
li a0, 1
|
||||||
ecall
|
ecall
|
||||||
|
|
||||||
#
|
#
|
||||||
|
|
||||||
# Tricky case to cover. I$ miss concurrent with DTLB miss. HPTW has to hit the first
|
# Tricky case to cover. I$ miss concurrent with DTLB miss. HPTW has to hit the first
|
||||||
# access in the cache and miss a later one. Trigger this by doing a load that touches
|
# access in the cache and miss a later one. Trigger this by doing a load that touches
|
||||||
# a page not in the DTLB but where the top-level PTE is already there. Has to happen
|
# a page not in the DTLB but where the top-level PTE is already there. Has to happen
|
||||||
# near the end of the 16-instruction I$ line.
|
# near the end of the 16-instruction I$ line.
|
||||||
#
|
#
|
||||||
# Condition Coverage for instance /core/ebu/ebu/ebufsmarb --
|
# Condition Coverage for instance /core/ebu/ebu/ebufsmarb --
|
||||||
#
|
#
|
||||||
# File ../src/ebu/ebufsmarb.sv
|
# File ../src/ebu/ebufsmarb.sv
|
||||||
@ -66,8 +66,8 @@ main:
|
|||||||
# LSUReq N '_1' not hit Hit '_1'
|
# LSUReq N '_1' not hit Hit '_1'
|
||||||
# IFUReq N No hits Hit '_0' and '_1'
|
# IFUReq N No hits Hit '_0' and '_1'
|
||||||
#
|
#
|
||||||
# Rows: Hits FEC Target Non-masking condition(s)
|
# Rows: Hits FEC Target Non-masking condition(s)
|
||||||
# --------- --------- -------------------- -------------------------
|
# --------- --------- -------------------- -------------------------
|
||||||
# Row 1: 2 HREADY_0 ((LSUReq ~& IFUReq) && FinalBeatD)
|
# Row 1: 2 HREADY_0 ((LSUReq ~& IFUReq) && FinalBeatD)
|
||||||
# Row 2: 14 HREADY_1 ((LSUReq ~& IFUReq) && FinalBeatD)
|
# Row 2: 14 HREADY_1 ((LSUReq ~& IFUReq) && FinalBeatD)
|
||||||
# Row 3: 1 FinalBeatD_0 ((LSUReq ~& IFUReq) && HREADY)
|
# Row 3: 1 FinalBeatD_0 ((LSUReq ~& IFUReq) && HREADY)
|
||||||
@ -78,7 +78,7 @@ main:
|
|||||||
# Row 8: ***0*** IFUReq_1 ((HREADY & FinalBeatD) && LSUReq)
|
# Row 8: ***0*** IFUReq_1 ((HREADY & FinalBeatD) && LSUReq)
|
||||||
|
|
||||||
|
|
||||||
li a0, 0x80000000
|
li a0, 0x80000000
|
||||||
li a1, 0x80A00000
|
li a1, 0x80A00000
|
||||||
j label1
|
j label1
|
||||||
|
|
||||||
@ -166,7 +166,7 @@ label1:
|
|||||||
|
|
||||||
.align 16
|
.align 16
|
||||||
# root Page table situated at 0x80010000
|
# root Page table situated at 0x80010000
|
||||||
pagetable:
|
pagetable:
|
||||||
.8byte 0x200044C1 # 0x00000000-0x80_00000000: PTE at 0x80011000 C1 dirty, accessed, valid
|
.8byte 0x200044C1 # 0x00000000-0x80_00000000: PTE at 0x80011000 C1 dirty, accessed, valid
|
||||||
.8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000
|
.8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000
|
||||||
|
|
||||||
@ -175,7 +175,7 @@ pagetable:
|
|||||||
.8byte 0x00000000000010CF # misaligned gigapage at 0x00000000
|
.8byte 0x00000000000010CF # misaligned gigapage at 0x00000000
|
||||||
.8byte 0x00000000200058C1 # PTE for pages at 0x40000000
|
.8byte 0x00000000200058C1 # PTE for pages at 0x40000000
|
||||||
.8byte 0x00000000200048C1 # gigapage at 0x80000000 pointing to 0x80120000
|
.8byte 0x00000000200048C1 # gigapage at 0x80000000 pointing to 0x80120000
|
||||||
|
|
||||||
|
|
||||||
# Next page table at 0x80012000 for gigapage at 0x80000000
|
# Next page table at 0x80012000 for gigapage at 0x80000000
|
||||||
.align 12
|
.align 12
|
||||||
@ -260,7 +260,7 @@ pagetable:
|
|||||||
.8byte 0x80000000200060CF
|
.8byte 0x80000000200060CF
|
||||||
.8byte 0x80000000200060CF
|
.8byte 0x80000000200060CF
|
||||||
.8byte 0x80000000200060CF
|
.8byte 0x80000000200060CF
|
||||||
|
|
||||||
.8byte 0x800000002000A0CF
|
.8byte 0x800000002000A0CF
|
||||||
.8byte 0x800000002000A0CF
|
.8byte 0x800000002000A0CF
|
||||||
.8byte 0x800000002000A0CF
|
.8byte 0x800000002000A0CF
|
||||||
|
|||||||
@ -6,7 +6,7 @@
|
|||||||
.global rvtest_entry_point
|
.global rvtest_entry_point
|
||||||
rvtest_entry_point:
|
rvtest_entry_point:
|
||||||
lui t0, 0x02 # turn on Floating point and XS
|
lui t0, 0x02 # turn on Floating point and XS
|
||||||
csrs mstatus, t0
|
csrs mstatus, t0
|
||||||
|
|
||||||
la a6, begin_signature
|
la a6, begin_signature
|
||||||
la a7, rvtest_data
|
la a7, rvtest_data
|
||||||
@ -53,9 +53,9 @@ write_tohost:
|
|||||||
|
|
||||||
self_loop:
|
self_loop:
|
||||||
j self_loop # wait
|
j self_loop # wait
|
||||||
|
|
||||||
.align 6
|
.align 6
|
||||||
.section .tohost
|
.section .tohost
|
||||||
tohost: # write to HTIF
|
tohost: # write to HTIF
|
||||||
.dword 0
|
.dword 0
|
||||||
fromhost:
|
fromhost:
|
||||||
@ -75,10 +75,10 @@ rvtest_data:
|
|||||||
|
|
||||||
.EQU XLEN,64
|
.EQU XLEN,64
|
||||||
begin_signature:
|
begin_signature:
|
||||||
.fill 8*(XLEN/32),4,0xdeadbeef #
|
.fill 8*(XLEN/32),4,0xdeadbeef #
|
||||||
end_signature:
|
end_signature:
|
||||||
|
|
||||||
# Initialize stack with room for 512 bytes
|
# Initialize stack with room for 512 bytes
|
||||||
.bss
|
.bss
|
||||||
.space 512
|
.space 512
|
||||||
topofstack:
|
topofstack:
|
||||||
|
|||||||
@ -7,20 +7,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -48,9 +48,9 @@ main:
|
|||||||
fcvt.h.q fs1, fs0
|
fcvt.h.q fs1, fs0
|
||||||
fcvt.s.q fs1, fs0
|
fcvt.s.q fs1, fs0
|
||||||
# round for now because these tests are excluded from Zfa until rounding is implemented
|
# round for now because these tests are excluded from Zfa until rounding is implemented
|
||||||
fround.s fs1, fs0
|
fround.s fs1, fs0
|
||||||
froundnx.s fs1, fs0
|
froundnx.s fs1, fs0
|
||||||
fround.d fs1, fs0
|
fround.d fs1, fs0
|
||||||
froundnx.d fs1, fs0
|
froundnx.d fs1, fs0
|
||||||
fround.h fs1, fs0
|
fround.h fs1, fs0
|
||||||
froundnx.h fs1, fs0
|
froundnx.h fs1, fs0
|
||||||
@ -146,7 +146,7 @@ main:
|
|||||||
sd t0, 0(t1)
|
sd t0, 0(t1)
|
||||||
csrsi mstatus, 0b1000 # enable interrupts with mstatus.MIE
|
csrsi mstatus, 0b1000 # enable interrupts with mstatus.MIE
|
||||||
li t1, 0x0200bff8 # read MTIME in CLINT
|
li t1, 0x0200bff8 # read MTIME in CLINT
|
||||||
ld t0, 0(t1)
|
ld t0, 0(t1)
|
||||||
addi t0, t0, 11
|
addi t0, t0, 11
|
||||||
li t1, 0x02004000 # MTIMECMP in CLINT
|
li t1, 0x02004000 # MTIMECMP in CLINT
|
||||||
sd t0, 0(t1) # write mtime+10 to cause interrupt soon This is very touchy timing and is sensitive to cache line fetch latency
|
sd t0, 0(t1) # write mtime+10 to cause interrupt soon This is very touchy timing and is sensitive to cache line fetch latency
|
||||||
@ -166,7 +166,7 @@ main:
|
|||||||
.word 0xc5000007 // Attempting to toggle (Op7 != 7) to 0 on line 97 in fctrl, not sure what instruction this works out to
|
.word 0xc5000007 // Attempting to toggle (Op7 != 7) to 0 on line 97 in fctrl, not sure what instruction this works out to
|
||||||
.word 0xe0101053 // toggling (Rs2D == 0) to 0 on line 139 in fctrl. Illegal Intsr (like fclass but incorrect rs2)
|
.word 0xe0101053 // toggling (Rs2D == 0) to 0 on line 139 in fctrl. Illegal Intsr (like fclass but incorrect rs2)
|
||||||
.word 0xe0100053 // toggling (Rs2D == 0) to 0 on line 141 in fctrl. Illegal Intsr (like fmv but incorrect rs2)
|
.word 0xe0100053 // toggling (Rs2D == 0) to 0 on line 141 in fctrl. Illegal Intsr (like fmv but incorrect rs2)
|
||||||
.word 0x40D00053 // toggling (Rs2D[4:2] == 0) to 0 on line 145 in fctrl.
|
.word 0x40D00053 // toggling (Rs2D[4:2] == 0) to 0 on line 145 in fctrl.
|
||||||
.word 0x40300053 // toggling SupportFmt2 to 0 on line 145 in fctrl.
|
.word 0x40300053 // toggling SupportFmt2 to 0 on line 145 in fctrl.
|
||||||
.word 0x42100053 // toggling (Rs2D[1:0] != 1) to 0 on line 147 in fctrl. Illegal Instr
|
.word 0x42100053 // toggling (Rs2D[1:0] != 1) to 0 on line 147 in fctrl. Illegal Instr
|
||||||
.word 0xf0100053 // toggling (Rs2D == 0) to 0 on line 143 in fctrl. Illegal Instr
|
.word 0xf0100053 // toggling (Rs2D == 0) to 0 on line 143 in fctrl. Illegal Instr
|
||||||
|
|||||||
@ -8,20 +8,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -41,7 +41,7 @@ main:
|
|||||||
jal ra, global_hist_2_space_test
|
jal ra, global_hist_2_space_test
|
||||||
jal ra, global_hist_1_space_test
|
jal ra, global_hist_1_space_test
|
||||||
jal ra, global_hist_0_space_test
|
jal ra, global_hist_0_space_test
|
||||||
|
|
||||||
fence.I
|
fence.I
|
||||||
|
|
||||||
finished:
|
finished:
|
||||||
@ -100,7 +100,7 @@ oneLoopTest5:
|
|||||||
# instruction
|
# instruction
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
bne t3, t4, oneLoopTest5 # this branch toggles between taken and not taken.
|
bne t3, t4, oneLoopTest5 # this branch toggles between taken and not taken.
|
||||||
|
|
||||||
ret
|
ret
|
||||||
|
|
||||||
.section .text
|
.section .text
|
||||||
@ -116,10 +116,10 @@ loop_6:
|
|||||||
# instruction
|
# instruction
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
beqz t4, zero_6 # this branch toggles between taken and not taken.
|
beqz t4, zero_6 # this branch toggles between taken and not taken.
|
||||||
li t4, 0
|
li t4, 0
|
||||||
j one_6
|
j one_6
|
||||||
@ -129,12 +129,12 @@ zero_6:
|
|||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
add t1, t1, t4
|
add t1, t1, t4
|
||||||
|
|
||||||
one_6:
|
one_6:
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
addi t2, t2, -1
|
addi t2, t2, -1
|
||||||
bnez t2, loop_6
|
bnez t2, loop_6
|
||||||
|
|
||||||
@ -153,8 +153,8 @@ loop_4:
|
|||||||
# instruction
|
# instruction
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
beqz t4, zero_4 # this branch toggles between taken and not taken.
|
beqz t4, zero_4 # this branch toggles between taken and not taken.
|
||||||
li t4, 0
|
li t4, 0
|
||||||
j one_4
|
j one_4
|
||||||
@ -162,9 +162,9 @@ zero_4:
|
|||||||
li t4, 1
|
li t4, 1
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
add t1, t1, t4
|
add t1, t1, t4
|
||||||
|
|
||||||
one_4:
|
one_4:
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
addi t2, t2, -1
|
addi t2, t2, -1
|
||||||
bnez t2, loop_4
|
bnez t2, loop_4
|
||||||
|
|
||||||
@ -183,8 +183,8 @@ loop_3:
|
|||||||
# instruction
|
# instruction
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
beqz t4, zero_3 # this branch toggles between taken and not taken.
|
beqz t4, zero_3 # this branch toggles between taken and not taken.
|
||||||
li t4, 0
|
li t4, 0
|
||||||
j one_3
|
j one_3
|
||||||
@ -192,9 +192,9 @@ zero_3:
|
|||||||
li t4, 1
|
li t4, 1
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
add t1, t1, t4
|
add t1, t1, t4
|
||||||
|
|
||||||
one_3:
|
one_3:
|
||||||
addi t3, t3, 1
|
addi t3, t3, 1
|
||||||
addi t2, t2, -1
|
addi t2, t2, -1
|
||||||
bnez t2, loop_3
|
bnez t2, loop_3
|
||||||
|
|
||||||
@ -220,7 +220,7 @@ loop_2:
|
|||||||
zero_2:
|
zero_2:
|
||||||
li t4, 1
|
li t4, 1
|
||||||
add t1, t1, t4
|
add t1, t1, t4
|
||||||
|
|
||||||
one_2:
|
one_2:
|
||||||
addi t2, t2, -1
|
addi t2, t2, -1
|
||||||
bnez t2, loop_2
|
bnez t2, loop_2
|
||||||
@ -245,13 +245,13 @@ loop_1:
|
|||||||
zero_1:
|
zero_1:
|
||||||
li t4, 1
|
li t4, 1
|
||||||
add t1, t1, t4
|
add t1, t1, t4
|
||||||
|
|
||||||
one_1:
|
one_1:
|
||||||
addi t2, t2, -1
|
addi t2, t2, -1
|
||||||
bnez t2, loop_1
|
bnez t2, loop_1
|
||||||
|
|
||||||
ret
|
ret
|
||||||
|
|
||||||
.section .text
|
.section .text
|
||||||
.globl global_hist_0_space_test
|
.globl global_hist_0_space_test
|
||||||
.type global_hist_0_space_test, @function
|
.type global_hist_0_space_test, @function
|
||||||
@ -269,10 +269,9 @@ loop_0:
|
|||||||
zero_0:
|
zero_0:
|
||||||
li t4, 1
|
li t4, 1
|
||||||
add t1, t1, t4
|
add t1, t1, t4
|
||||||
|
|
||||||
one_0:
|
one_0:
|
||||||
addi t2, t2, -1
|
addi t2, t2, -1
|
||||||
bnez t2, loop_0
|
bnez t2, loop_0
|
||||||
|
|
||||||
ret
|
ret
|
||||||
|
|
||||||
|
|||||||
@ -8,20 +8,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -39,20 +39,20 @@ main:
|
|||||||
# sfence.vma x0, x0
|
# sfence.vma x0, x0
|
||||||
|
|
||||||
# switch to supervisor mode
|
# switch to supervisor mode
|
||||||
li a0, 1
|
li a0, 1
|
||||||
ecall
|
ecall
|
||||||
li t5, 0
|
li t5, 0
|
||||||
li t2, 0x1000
|
li t2, 0x1000
|
||||||
li t0, 0x8000001000
|
li t0, 0x8000001000
|
||||||
|
|
||||||
lw t1, 0(t0) # this load is a valid virtual address, but the page table will access an invalid address so it should cause a load access fault
|
lw t1, 0(t0) # this load is a valid virtual address, but the page table will access an invalid address so it should cause a load access fault
|
||||||
li t1, 0x00008067 # this store is a valid virtual address, but the page table will access an invalid address so it should cause a store access fault
|
li t1, 0x00008067 # this store is a valid virtual address, but the page table will access an invalid address so it should cause a store access fault
|
||||||
add t0, t0, t2
|
add t0, t0, t2
|
||||||
sw t1, 0(t0)
|
sw t1, 0(t0)
|
||||||
|
|
||||||
j jumppoint
|
j jumppoint
|
||||||
|
|
||||||
jumppoint:
|
jumppoint:
|
||||||
.align 6 # aligns to cache line size
|
.align 6 # aligns to cache line size
|
||||||
sw t1, 0(t0)
|
sw t1, 0(t0)
|
||||||
sw t1, 4(t0)
|
sw t1, 4(t0)
|
||||||
@ -74,7 +74,7 @@ jumppoint:
|
|||||||
lw t3, 8(t0)
|
lw t3, 8(t0)
|
||||||
lw t3, 12(t0)
|
lw t3, 12(t0)
|
||||||
lw t3, 16(t0)
|
lw t3, 16(t0)
|
||||||
|
|
||||||
fence.I
|
fence.I
|
||||||
|
|
||||||
finished:
|
finished:
|
||||||
@ -84,15 +84,15 @@ finished:
|
|||||||
|
|
||||||
.align 16
|
.align 16
|
||||||
# Page table situated at 0x80010000
|
# Page table situated at 0x80010000
|
||||||
pagetable:
|
pagetable:
|
||||||
.8byte 0x200044C1
|
.8byte 0x200044C1
|
||||||
.8byte 0x300044C1 # point to invalid region of physical memory
|
.8byte 0x300044C1 # point to invalid region of physical memory
|
||||||
|
|
||||||
.align 12
|
.align 12
|
||||||
.8byte 0x00000040200048C1
|
.8byte 0x00000040200048C1
|
||||||
.8byte 0x00000000200048C1
|
.8byte 0x00000000200048C1
|
||||||
.8byte 0x00000000200048C1
|
.8byte 0x00000000200048C1
|
||||||
|
|
||||||
|
|
||||||
.align 12
|
.align 12
|
||||||
.8byte 0x0000000020004CC1
|
.8byte 0x0000000020004CC1
|
||||||
@ -138,7 +138,7 @@ pagetable:
|
|||||||
.8byte 0x200074CF
|
.8byte 0x200074CF
|
||||||
.8byte 0x200078CF
|
.8byte 0x200078CF
|
||||||
.8byte 0x20007CCF
|
.8byte 0x20007CCF
|
||||||
|
|
||||||
.8byte 0x200080CF
|
.8byte 0x200080CF
|
||||||
.8byte 0x200084CF
|
.8byte 0x200084CF
|
||||||
.8byte 0x200088CF
|
.8byte 0x200088CF
|
||||||
|
|||||||
@ -7,20 +7,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -53,7 +53,7 @@ main:
|
|||||||
ori x0, x0, 1
|
ori x0, x0, 1
|
||||||
ori x0, x0, 2
|
ori x0, x0, 2
|
||||||
ori x0, x0, 3
|
ori x0, x0, 3
|
||||||
|
|
||||||
|
|
||||||
# Test illegal instructions are detected
|
# Test illegal instructions are detected
|
||||||
.word 0x80000033 // illegal R-type instruction
|
.word 0x80000033 // illegal R-type instruction
|
||||||
@ -100,9 +100,8 @@ main:
|
|||||||
cbo.inval (x2)
|
cbo.inval (x2)
|
||||||
cbo.clean (x3)
|
cbo.clean (x3)
|
||||||
cbo.flush (x1)
|
cbo.flush (x1)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
j done
|
j done
|
||||||
|
|
||||||
|
|||||||
@ -7,20 +7,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -37,7 +37,7 @@ main:
|
|||||||
// binary version 0000 0000 0000 0000 0010 0000 0000 0000
|
// binary version 0000 0000 0000 0000 0010 0000 0000 0000
|
||||||
mv s0, sp
|
mv s0, sp
|
||||||
c.fld fs0, 0(s0) // Previously uncovered instructions
|
c.fld fs0, 0(s0) // Previously uncovered instructions
|
||||||
c.fsd fs0, 0(s0)
|
c.fsd fs0, 0(s0)
|
||||||
.hword 0x2002 // c.fldsp fs0, 0
|
.hword 0x2002 // c.fldsp fs0, 0
|
||||||
.hword 0xA002 // c.fsdsp fs0, 0
|
.hword 0xA002 // c.fsdsp fs0, 0
|
||||||
.hword 0x9C41 // line 134 Illegal compressed instruction
|
.hword 0x9C41 // line 134 Illegal compressed instruction
|
||||||
@ -72,9 +72,9 @@ main:
|
|||||||
.hword 0x9C71 // c.zext.w s0
|
.hword 0x9C71 // c.zext.w s0
|
||||||
# c.not s0 // exercise c.not
|
# c.not s0 // exercise c.not
|
||||||
.hword 0x9C75 // c.not s0
|
.hword 0x9C75 // c.not s0
|
||||||
|
|
||||||
.hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else
|
.hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else
|
||||||
|
|
||||||
# exercise all the cache ways
|
# exercise all the cache ways
|
||||||
j way0code
|
j way0code
|
||||||
|
|
||||||
@ -100,6 +100,6 @@ way3code:
|
|||||||
.align 12
|
.align 12
|
||||||
way00code:
|
way00code:
|
||||||
ret
|
ret
|
||||||
|
|
||||||
|
|
||||||
j done
|
j done
|
||||||
|
|||||||
@ -2,28 +2,28 @@
|
|||||||
// ifuCamlineWrite.S
|
// ifuCamlineWrite.S
|
||||||
//
|
//
|
||||||
// Written: Miles Cook <mdcook@g.hmc.edu> and Kevin Box <kbox@g.hmc.edu> 4/17
|
// Written: Miles Cook <mdcook@g.hmc.edu> and Kevin Box <kbox@g.hmc.edu> 4/17
|
||||||
//
|
|
||||||
// Acknowledgements: The pagetable and outline for this test was written by Manuel Mendoza
|
|
||||||
// and Noah Limpert.
|
|
||||||
//
|
//
|
||||||
// Purpose: Test coverage for TLBCamlines in IFU
|
// Acknowledgements: The pagetable and outline for this test was written by Manuel Mendoza
|
||||||
|
// and Noah Limpert.
|
||||||
|
//
|
||||||
|
// Purpose: Test coverage for TLBCamlines in IFU
|
||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -38,10 +38,10 @@ main:
|
|||||||
csrw satp, t5
|
csrw satp, t5
|
||||||
|
|
||||||
# switch to supervisor mode
|
# switch to supervisor mode
|
||||||
li a0, 1
|
li a0, 1
|
||||||
ecall
|
ecall
|
||||||
|
|
||||||
li t0, 0x80015000 # base addr
|
li t0, 0x80015000 # base addr
|
||||||
|
|
||||||
li t2, 0 # i = 0
|
li t2, 0 # i = 0
|
||||||
li t3, 33 # Max amount of Loops = 32
|
li t3, 33 # Max amount of Loops = 32
|
||||||
@ -49,9 +49,9 @@ main:
|
|||||||
loop: bge t2, t3, finished # exit loop if i >= loops
|
loop: bge t2, t3, finished # exit loop if i >= loops
|
||||||
li t4, 0x1000
|
li t4, 0x1000
|
||||||
li t1, 0x00008067 # load in jalr
|
li t1, 0x00008067 # load in jalr
|
||||||
sw t1, 0 (t0)
|
sw t1, 0 (t0)
|
||||||
fence.I
|
fence.I
|
||||||
jalr t0
|
jalr t0
|
||||||
add t0, t0, t4
|
add t0, t0, t4
|
||||||
addi t2, t2, 1
|
addi t2, t2, 1
|
||||||
j loop
|
j loop
|
||||||
@ -63,14 +63,14 @@ finished:
|
|||||||
|
|
||||||
.align 16
|
.align 16
|
||||||
# Page table situated at 0x80010000
|
# Page table situated at 0x80010000
|
||||||
pagetable:
|
pagetable:
|
||||||
.8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong
|
.8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong
|
||||||
|
|
||||||
.align 12
|
.align 12
|
||||||
.8byte 0x0000000000000000
|
.8byte 0x0000000000000000
|
||||||
.8byte 0x00000000200048C1
|
.8byte 0x00000000200048C1
|
||||||
.8byte 0x00000000200048C1
|
.8byte 0x00000000200048C1
|
||||||
|
|
||||||
|
|
||||||
.align 12
|
.align 12
|
||||||
.8byte 0x0000000020004CC1
|
.8byte 0x0000000020004CC1
|
||||||
@ -117,7 +117,7 @@ pagetable:
|
|||||||
.8byte 0x200074CF
|
.8byte 0x200074CF
|
||||||
.8byte 0x200078CF
|
.8byte 0x200078CF
|
||||||
.8byte 0x20007CCF
|
.8byte 0x20007CCF
|
||||||
|
|
||||||
.8byte 0x200080CF
|
.8byte 0x200080CF
|
||||||
.8byte 0x200084CF
|
.8byte 0x200084CF
|
||||||
.8byte 0x200088CF
|
.8byte 0x200088CF
|
||||||
|
|||||||
@ -7,20 +7,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -34,4 +34,4 @@ main:
|
|||||||
li a0, 0x80000001 # misaligned address
|
li a0, 0x80000001 # misaligned address
|
||||||
amoadd.w t0, a0, (a0) # amo access to misaligned address
|
amoadd.w t0, a0, (a0) # amo access to misaligned address
|
||||||
|
|
||||||
j done
|
j done
|
||||||
|
|||||||
@ -8,20 +8,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -39,17 +39,17 @@ main:
|
|||||||
# sfence.vma x0, x0
|
# sfence.vma x0, x0
|
||||||
|
|
||||||
# switch to supervisor mode
|
# switch to supervisor mode
|
||||||
li a0, 1
|
li a0, 1
|
||||||
ecall
|
ecall
|
||||||
li t5, 0
|
li t5, 0
|
||||||
li t2, 0x1000
|
li t2, 0x1000
|
||||||
li t0, 0x8000001000
|
li t0, 0x8000001000
|
||||||
|
|
||||||
lw t1, 0(t0) # valid virtual address, valid physical address, but invalid PBMT in middle of page table.
|
lw t1, 0(t0) # valid virtual address, valid physical address, but invalid PBMT in middle of page table.
|
||||||
li t1, 0x00008067
|
li t1, 0x00008067
|
||||||
add t0, t0, t2
|
add t0, t0, t2
|
||||||
sw t1, 0(t0) # valid virtual address, valid physical address, but invalid PBMT in middle of page table.
|
sw t1, 0(t0) # valid virtual address, valid physical address, but invalid PBMT in middle of page table.
|
||||||
|
|
||||||
fence.I
|
fence.I
|
||||||
|
|
||||||
finished:
|
finished:
|
||||||
@ -59,15 +59,15 @@ finished:
|
|||||||
|
|
||||||
.align 16
|
.align 16
|
||||||
# Page table situated at 0x80010000
|
# Page table situated at 0x80010000
|
||||||
pagetable:
|
pagetable:
|
||||||
.8byte 0x200044C1
|
.8byte 0x200044C1
|
||||||
.8byte 0x200044C1
|
.8byte 0x200044C1
|
||||||
|
|
||||||
.align 12
|
.align 12
|
||||||
.8byte 0x40000040200048C1
|
.8byte 0x40000040200048C1
|
||||||
.8byte 0x00000000200048C1
|
.8byte 0x00000000200048C1
|
||||||
.8byte 0x00000000200048C1
|
.8byte 0x00000000200048C1
|
||||||
|
|
||||||
|
|
||||||
.align 12
|
.align 12
|
||||||
.8byte 0x0000000020004CC1
|
.8byte 0x0000000020004CC1
|
||||||
@ -113,7 +113,7 @@ pagetable:
|
|||||||
.8byte 0x200074CF
|
.8byte 0x200074CF
|
||||||
.8byte 0x200078CF
|
.8byte 0x200078CF
|
||||||
.8byte 0x20007CCF
|
.8byte 0x20007CCF
|
||||||
|
|
||||||
.8byte 0x200080CF
|
.8byte 0x200080CF
|
||||||
.8byte 0x200084CF
|
.8byte 0x200084CF
|
||||||
.8byte 0x200088CF
|
.8byte 0x200088CF
|
||||||
|
|||||||
@ -4,10 +4,10 @@
|
|||||||
// Created 2023-04-09 23:20:54.863039
|
// Created 2023-04-09 23:20:54.863039
|
||||||
///////////////////////////////////////////
|
///////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
#include "WALLY-init-lib.h"
|
#include "WALLY-init-lib.h"
|
||||||
|
|
||||||
main:
|
main:
|
||||||
|
|
||||||
@ -107,12 +107,12 @@ li t4, 1733894653101739012
|
|||||||
csrw pmpcfg2, t4
|
csrw pmpcfg2, t4
|
||||||
|
|
||||||
|
|
||||||
// Testing
|
// Testing
|
||||||
|
|
||||||
// END Configuration and Testing Starting at Register: 0
|
// END Configuration and Testing Starting at Register: 0
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// BEGIN Configuration and Testing Starting at Register: 1
|
// BEGIN Configuration and Testing Starting at Register: 1
|
||||||
//
|
//
|
||||||
@ -209,12 +209,12 @@ li t4, 1155173425015948313
|
|||||||
csrw pmpcfg2, t4
|
csrw pmpcfg2, t4
|
||||||
|
|
||||||
|
|
||||||
// Testing
|
// Testing
|
||||||
|
|
||||||
// END Configuration and Testing Starting at Register: 1
|
// END Configuration and Testing Starting at Register: 1
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// BEGIN Configuration and Testing Starting at Register: 2
|
// BEGIN Configuration and Testing Starting at Register: 2
|
||||||
//
|
//
|
||||||
@ -311,12 +311,12 @@ li t4, 576491624729942289
|
|||||||
csrw pmpcfg2, t4
|
csrw pmpcfg2, t4
|
||||||
|
|
||||||
|
|
||||||
// Testing
|
// Testing
|
||||||
|
|
||||||
// END Configuration and Testing Starting at Register: 2
|
// END Configuration and Testing Starting at Register: 2
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// BEGIN Configuration and Testing Starting at Register: 3
|
// BEGIN Configuration and Testing Starting at Register: 3
|
||||||
//
|
//
|
||||||
@ -413,12 +413,12 @@ li t4, 7903341188813065
|
|||||||
csrw pmpcfg2, t4
|
csrw pmpcfg2, t4
|
||||||
|
|
||||||
|
|
||||||
// Testing
|
// Testing
|
||||||
|
|
||||||
// END Configuration and Testing Starting at Register: 3
|
// END Configuration and Testing Starting at Register: 3
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// BEGIN Configuration and Testing Starting at Register: 4
|
// BEGIN Configuration and Testing Starting at Register: 4
|
||||||
//
|
//
|
||||||
@ -515,12 +515,12 @@ li t4, 2023255344336144641
|
|||||||
csrw pmpcfg2, t4
|
csrw pmpcfg2, t4
|
||||||
|
|
||||||
|
|
||||||
// Testing
|
// Testing
|
||||||
|
|
||||||
// END Configuration and Testing Starting at Register: 4
|
// END Configuration and Testing Starting at Register: 4
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// BEGIN Configuration and Testing Starting at Register: 5
|
// BEGIN Configuration and Testing Starting at Register: 5
|
||||||
//
|
//
|
||||||
@ -617,12 +617,12 @@ li t4, 1444534086185583003
|
|||||||
csrw pmpcfg2, t4
|
csrw pmpcfg2, t4
|
||||||
|
|
||||||
|
|
||||||
// Testing
|
// Testing
|
||||||
|
|
||||||
// END Configuration and Testing Starting at Register: 5
|
// END Configuration and Testing Starting at Register: 5
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// BEGIN Configuration and Testing Starting at Register: 6
|
// BEGIN Configuration and Testing Starting at Register: 6
|
||||||
//
|
//
|
||||||
@ -719,12 +719,12 @@ li t4, 865844589318216595
|
|||||||
csrw pmpcfg2, t4
|
csrw pmpcfg2, t4
|
||||||
|
|
||||||
|
|
||||||
// Testing
|
// Testing
|
||||||
|
|
||||||
// END Configuration and Testing Starting at Register: 6
|
// END Configuration and Testing Starting at Register: 6
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// BEGIN Configuration and Testing Starting at Register: 7
|
// BEGIN Configuration and Testing Starting at Register: 7
|
||||||
//
|
//
|
||||||
@ -821,12 +821,12 @@ li t4, 295285980948829067
|
|||||||
csrw pmpcfg2, t4
|
csrw pmpcfg2, t4
|
||||||
|
|
||||||
|
|
||||||
// Testing
|
// Testing
|
||||||
|
|
||||||
// END Configuration and Testing Starting at Register: 7
|
// END Configuration and Testing Starting at Register: 7
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// BEGIN Configuration and Testing Starting at Register: 8
|
// BEGIN Configuration and Testing Starting at Register: 8
|
||||||
//
|
//
|
||||||
@ -923,12 +923,12 @@ li t4, 1806234828062034819
|
|||||||
csrw pmpcfg2, t4
|
csrw pmpcfg2, t4
|
||||||
|
|
||||||
|
|
||||||
// Testing
|
// Testing
|
||||||
|
|
||||||
// END Configuration and Testing Starting at Register: 8
|
// END Configuration and Testing Starting at Register: 8
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// BEGIN Configuration and Testing Starting at Register: 9
|
// BEGIN Configuration and Testing Starting at Register: 9
|
||||||
//
|
//
|
||||||
@ -1025,12 +1025,12 @@ li t4, 1227514141142123288
|
|||||||
csrw pmpcfg2, t4
|
csrw pmpcfg2, t4
|
||||||
|
|
||||||
|
|
||||||
// Testing
|
// Testing
|
||||||
|
|
||||||
// END Configuration and Testing Starting at Register: 9
|
// END Configuration and Testing Starting at Register: 9
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// BEGIN Configuration and Testing Starting at Register: 10
|
// BEGIN Configuration and Testing Starting at Register: 10
|
||||||
//
|
//
|
||||||
@ -1127,12 +1127,12 @@ li t4, 648970879321184272
|
|||||||
csrw pmpcfg2, t4
|
csrw pmpcfg2, t4
|
||||||
|
|
||||||
|
|
||||||
// Testing
|
// Testing
|
||||||
|
|
||||||
// END Configuration and Testing Starting at Register: 10
|
// END Configuration and Testing Starting at Register: 10
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// BEGIN Configuration and Testing Starting at Register: 11
|
// BEGIN Configuration and Testing Starting at Register: 11
|
||||||
//
|
//
|
||||||
@ -1229,12 +1229,12 @@ li t4, 115848442837209096
|
|||||||
csrw pmpcfg2, t4
|
csrw pmpcfg2, t4
|
||||||
|
|
||||||
|
|
||||||
// Testing
|
// Testing
|
||||||
|
|
||||||
// END Configuration and Testing Starting at Register: 11
|
// END Configuration and Testing Starting at Register: 11
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// BEGIN Configuration and Testing Starting at Register: 12
|
// BEGIN Configuration and Testing Starting at Register: 12
|
||||||
//
|
//
|
||||||
@ -1331,12 +1331,12 @@ li t4, 11210457292615976960
|
|||||||
csrw pmpcfg2, t4
|
csrw pmpcfg2, t4
|
||||||
|
|
||||||
|
|
||||||
// Testing
|
// Testing
|
||||||
|
|
||||||
// END Configuration and Testing Starting at Register: 12
|
// END Configuration and Testing Starting at Register: 12
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// BEGIN Configuration and Testing Starting at Register: 13
|
// BEGIN Configuration and Testing Starting at Register: 13
|
||||||
//
|
//
|
||||||
@ -1433,12 +1433,12 @@ li t4, 10631735484709601308
|
|||||||
csrw pmpcfg2, t4
|
csrw pmpcfg2, t4
|
||||||
|
|
||||||
|
|
||||||
// Testing
|
// Testing
|
||||||
|
|
||||||
// END Configuration and Testing Starting at Register: 13
|
// END Configuration and Testing Starting at Register: 13
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// BEGIN Configuration and Testing Starting at Register: 14
|
// BEGIN Configuration and Testing Starting at Register: 14
|
||||||
//
|
//
|
||||||
@ -1535,12 +1535,12 @@ li t4, 10052905250353847316
|
|||||||
csrw pmpcfg2, t4
|
csrw pmpcfg2, t4
|
||||||
|
|
||||||
|
|
||||||
// Testing
|
// Testing
|
||||||
|
|
||||||
// END Configuration and Testing Starting at Register: 14
|
// END Configuration and Testing Starting at Register: 14
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// BEGIN Configuration and Testing Starting at Register: 15
|
// BEGIN Configuration and Testing Starting at Register: 15
|
||||||
//
|
//
|
||||||
@ -1637,10 +1637,10 @@ li t4, 9446317844957238284
|
|||||||
csrw pmpcfg2, t4
|
csrw pmpcfg2, t4
|
||||||
|
|
||||||
|
|
||||||
// Testing
|
// Testing
|
||||||
|
|
||||||
// END Configuration and Testing Starting at Register: 15
|
// END Configuration and Testing Starting at Register: 15
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
j done
|
j done
|
||||||
|
|||||||
@ -2,8 +2,8 @@
|
|||||||
// Liam Chalk, lchalk@hmc.edu, 4/27/2023
|
// Liam Chalk, lchalk@hmc.edu, 4/27/2023
|
||||||
// Setting AdrMode to 2 or 3 for pmpadrdecs[0-4]
|
// Setting AdrMode to 2 or 3 for pmpadrdecs[0-4]
|
||||||
|
|
||||||
#include "WALLY-init-lib.h"
|
#include "WALLY-init-lib.h"
|
||||||
main:
|
main:
|
||||||
|
|
||||||
# Writing values to pmpcfg0 to change AdrMode to 2 or 3
|
# Writing values to pmpcfg0 to change AdrMode to 2 or 3
|
||||||
# pmpadrdec[0]
|
# pmpadrdec[0]
|
||||||
@ -19,4 +19,4 @@ main:
|
|||||||
li t0, 0x1000000000
|
li t0, 0x1000000000
|
||||||
csrw pmpcfg0, t0
|
csrw pmpcfg0, t0
|
||||||
|
|
||||||
j done
|
j done
|
||||||
|
|||||||
@ -2,14 +2,14 @@
|
|||||||
// David_Harris@hmc.edu 1/21/24
|
// David_Harris@hmc.edu 1/21/24
|
||||||
// Cover PMP checks of cache management instructions
|
// Cover PMP checks of cache management instructions
|
||||||
|
|
||||||
#include "WALLY-init-lib.h"
|
#include "WALLY-init-lib.h"
|
||||||
main:
|
main:
|
||||||
|
|
||||||
# set up PMP so user and supervisor mode can access partial address space
|
# set up PMP so user and supervisor mode can access partial address space
|
||||||
li t0, 0x080F;
|
li t0, 0x080F;
|
||||||
# li t0, 0x0808;
|
# li t0, 0x0808;
|
||||||
csrw pmpcfg0, t0 # configure PMP0 to TOR RWX and PMP1 to TOR no access
|
csrw pmpcfg0, t0 # configure PMP0 to TOR RWX and PMP1 to TOR no access
|
||||||
li t0, 0x2003FFFF
|
li t0, 0x2003FFFF
|
||||||
li t1, 0xFFFFFFFF
|
li t1, 0xFFFFFFFF
|
||||||
csrw pmpaddr0, t0 # configure PMP0 top of range to 0x800FFFFF to allow all 32-bit addresses
|
csrw pmpaddr0, t0 # configure PMP0 top of range to 0x800FFFFF to allow all 32-bit addresses
|
||||||
csrw pmpaddr1, t1 # configure PMP1 top of range to 0xFFFFFFFF to prohibit accesses above
|
csrw pmpaddr1, t1 # configure PMP1 top of range to 0xFFFFFFFF to prohibit accesses above
|
||||||
@ -28,4 +28,4 @@ main:
|
|||||||
cbo.zero (a0)
|
cbo.zero (a0)
|
||||||
cbo.inval (a0)
|
cbo.inval (a0)
|
||||||
|
|
||||||
j done
|
j done
|
||||||
|
|||||||
@ -1,11 +1,11 @@
|
|||||||
// pmpcfg part 1
|
// pmpcfg part 1
|
||||||
// Kevin Wan, kewan@hmc.edu, 4/18/2023
|
// Kevin Wan, kewan@hmc.edu, 4/18/2023
|
||||||
// Liam Chalk, lchalk@hmc.edu, 4/25/2023
|
// Liam Chalk, lchalk@hmc.edu, 4/25/2023
|
||||||
// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR.
|
// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR.
|
||||||
// See the next part in pmpcfg1.S
|
// See the next part in pmpcfg1.S
|
||||||
|
|
||||||
#include "WALLY-init-lib.h"
|
#include "WALLY-init-lib.h"
|
||||||
main:
|
main:
|
||||||
|
|
||||||
li t0, 0x90000000
|
li t0, 0x90000000
|
||||||
csrw pmpaddr0, t0
|
csrw pmpaddr0, t0
|
||||||
@ -103,4 +103,4 @@ main:
|
|||||||
li t0, 0x8800
|
li t0, 0x8800
|
||||||
csrw pmpcfg0, t0
|
csrw pmpcfg0, t0
|
||||||
|
|
||||||
j done
|
j done
|
||||||
|
|||||||
@ -1,12 +1,12 @@
|
|||||||
// another set of pmpcfg tests. A new file is made because pmpcfg register fields are
|
// another set of pmpcfg tests. A new file is made because pmpcfg register fields are
|
||||||
// locked forever after writing 1 to the lock bit for the first time.
|
// locked forever after writing 1 to the lock bit for the first time.
|
||||||
|
|
||||||
// Kevin Wan, kewan@hmc.edu, 4/13/2023
|
// Kevin Wan, kewan@hmc.edu, 4/13/2023
|
||||||
// This set tests locking the pmpXcfg fields in descending order again, without setting the TOR bits.
|
// This set tests locking the pmpXcfg fields in descending order again, without setting the TOR bits.
|
||||||
// for the other part of the tests, see pmpcfg.S
|
// for the other part of the tests, see pmpcfg.S
|
||||||
|
|
||||||
#include "WALLY-init-lib.h"
|
#include "WALLY-init-lib.h"
|
||||||
main:
|
main:
|
||||||
li t0, 0x800
|
li t0, 0x800
|
||||||
csrw pmpcfg0, t0
|
csrw pmpcfg0, t0
|
||||||
li t0, 0x8000000
|
li t0, 0x8000000
|
||||||
@ -45,4 +45,4 @@ main:
|
|||||||
|
|
||||||
|
|
||||||
|
|
||||||
j done
|
j done
|
||||||
|
|||||||
@ -1,12 +1,12 @@
|
|||||||
// pmpcfg part 3
|
// pmpcfg part 3
|
||||||
// Kevin Wan, kewan@hmc.edu, 4/18/2023
|
// Kevin Wan, kewan@hmc.edu, 4/18/2023
|
||||||
// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR.
|
// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR.
|
||||||
// See the next part in pmpcfg1.S
|
// See the next part in pmpcfg1.S
|
||||||
|
|
||||||
#include "WALLY-init-lib.h"
|
#include "WALLY-init-lib.h"
|
||||||
main:
|
main:
|
||||||
li t0, 0x80
|
li t0, 0x80
|
||||||
csrw pmpcfg0, t0
|
csrw pmpcfg0, t0
|
||||||
|
|
||||||
|
|
||||||
j done
|
j done
|
||||||
|
|||||||
@ -1,29 +1,29 @@
|
|||||||
// pmppriority test cases
|
// pmppriority test cases
|
||||||
// Kevin Wan kewan@hmc.edu 4/27/2023
|
// Kevin Wan kewan@hmc.edu 4/27/2023
|
||||||
// want memory ranges to match:
|
// want memory ranges to match:
|
||||||
// 1. only the most significant address and none of the lower ones,
|
// 1. only the most significant address and none of the lower ones,
|
||||||
// 2. the most significant address and ANY of the lower ones.
|
// 2. the most significant address and ANY of the lower ones.
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
#include "WALLY-init-lib.h"
|
#include "WALLY-init-lib.h"
|
||||||
main:
|
main:
|
||||||
|
|
||||||
li t1, 0x21FFFFFF // start at 0x8000000 with a range of 1000000. Address format is set to NAPOT in pmpcfg.
|
li t1, 0x21FFFFFF // start at 0x8000000 with a range of 1000000. Address format is set to NAPOT in pmpcfg.
|
||||||
csrw pmpaddr0, t1
|
csrw pmpaddr0, t1
|
||||||
csrw pmpaddr1, t1
|
csrw pmpaddr1, t1
|
||||||
csrw pmpaddr2, t1
|
csrw pmpaddr2, t1
|
||||||
csrw pmpaddr3, t1
|
csrw pmpaddr3, t1
|
||||||
csrw pmpaddr4, t1
|
csrw pmpaddr4, t1
|
||||||
csrw pmpaddr5, t1
|
csrw pmpaddr5, t1
|
||||||
csrw pmpaddr6, t1
|
csrw pmpaddr6, t1
|
||||||
csrw pmpaddr7, t1
|
csrw pmpaddr7, t1
|
||||||
|
|
||||||
csrw pmpaddr8, t1
|
csrw pmpaddr8, t1
|
||||||
csrw pmpaddr9, t1
|
csrw pmpaddr9, t1
|
||||||
csrw pmpaddr10, t1
|
csrw pmpaddr10, t1
|
||||||
csrw pmpaddr11, t1
|
csrw pmpaddr11, t1
|
||||||
csrw pmpaddr12, t1
|
csrw pmpaddr12, t1
|
||||||
csrw pmpaddr13, t1
|
csrw pmpaddr13, t1
|
||||||
csrw pmpaddr14, t1
|
csrw pmpaddr14, t1
|
||||||
csrw pmpaddr15, t1
|
csrw pmpaddr15, t1
|
||||||
@ -34,59 +34,59 @@ main:
|
|||||||
sw zero, 0(sp)
|
sw zero, 0(sp)
|
||||||
|
|
||||||
li t0, 0x1F00
|
li t0, 0x1F00
|
||||||
csrw pmpcfg0, t0
|
csrw pmpcfg0, t0
|
||||||
sw zero, 0(sp)
|
sw zero, 0(sp)
|
||||||
|
|
||||||
li t0, 0x1F1F
|
li t0, 0x1F1F
|
||||||
csrw pmpcfg0, t0
|
csrw pmpcfg0, t0
|
||||||
sw zero, 0(sp)
|
sw zero, 0(sp)
|
||||||
|
|
||||||
li t0, 0x1F0000
|
li t0, 0x1F0000
|
||||||
csrw pmpcfg0, t0
|
csrw pmpcfg0, t0
|
||||||
sw zero, 0(sp)
|
sw zero, 0(sp)
|
||||||
|
|
||||||
li t0, 0x1F1F1F
|
li t0, 0x1F1F1F
|
||||||
csrw pmpcfg0, t0
|
csrw pmpcfg0, t0
|
||||||
sw zero, 0(sp)
|
sw zero, 0(sp)
|
||||||
|
|
||||||
li t0, 0x1F000000
|
li t0, 0x1F000000
|
||||||
csrw pmpcfg0, t0
|
csrw pmpcfg0, t0
|
||||||
sw zero, 0(sp)
|
sw zero, 0(sp)
|
||||||
|
|
||||||
li t0, 0x1F1F1F1F
|
li t0, 0x1F1F1F1F
|
||||||
csrw pmpcfg0, t0
|
csrw pmpcfg0, t0
|
||||||
sw zero, 0(sp)
|
sw zero, 0(sp)
|
||||||
|
|
||||||
li t0, 0x1F00000000
|
li t0, 0x1F00000000
|
||||||
csrw pmpcfg0, t0
|
csrw pmpcfg0, t0
|
||||||
sw zero, 0(sp)
|
sw zero, 0(sp)
|
||||||
|
|
||||||
li t0, 0x1F1F1F1F1F
|
li t0, 0x1F1F1F1F1F
|
||||||
csrw pmpcfg0, t0
|
csrw pmpcfg0, t0
|
||||||
sw zero, 0(sp)
|
sw zero, 0(sp)
|
||||||
|
|
||||||
li t0, 0x1F0000000000
|
li t0, 0x1F0000000000
|
||||||
csrw pmpcfg0, t0
|
csrw pmpcfg0, t0
|
||||||
sw zero, 0(sp)
|
sw zero, 0(sp)
|
||||||
|
|
||||||
li t0, 0x1F1F1F1F1F1F
|
li t0, 0x1F1F1F1F1F1F
|
||||||
csrw pmpcfg0, t0
|
csrw pmpcfg0, t0
|
||||||
sw zero, 0(sp)
|
sw zero, 0(sp)
|
||||||
|
|
||||||
li t0, 0x1F000000000000
|
li t0, 0x1F000000000000
|
||||||
csrw pmpcfg0, t0
|
csrw pmpcfg0, t0
|
||||||
sw zero, 0(sp)
|
sw zero, 0(sp)
|
||||||
|
|
||||||
li t0, 0x1F1F1F1F1F1F1F
|
li t0, 0x1F1F1F1F1F1F1F
|
||||||
csrw pmpcfg0, t0
|
csrw pmpcfg0, t0
|
||||||
sw zero, 0(sp)
|
sw zero, 0(sp)
|
||||||
|
|
||||||
li t0, 0x1F00000000000000
|
li t0, 0x1F00000000000000
|
||||||
csrw pmpcfg0, t0
|
csrw pmpcfg0, t0
|
||||||
sw zero, 0(sp)
|
sw zero, 0(sp)
|
||||||
|
|
||||||
li t0, 0x1F1F1F1F1F1F1F1F
|
li t0, 0x1F1F1F1F1F1F1F1F
|
||||||
csrw pmpcfg0, t0
|
csrw pmpcfg0, t0
|
||||||
sw zero, 0(sp)
|
sw zero, 0(sp)
|
||||||
|
|
||||||
li t0, 0x0
|
li t0, 0x0
|
||||||
@ -156,6 +156,3 @@ main:
|
|||||||
|
|
||||||
|
|
||||||
j done
|
j done
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@ -7,20 +7,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -33,26 +33,26 @@ main:
|
|||||||
csrw sepc, t1
|
csrw sepc, t1
|
||||||
sret
|
sret
|
||||||
sretdone:
|
sretdone:
|
||||||
addi t2, x0, 42
|
addi t2, x0, 42
|
||||||
|
|
||||||
# switch to user mode
|
# switch to user mode
|
||||||
li a0, 0
|
li a0, 0
|
||||||
ecall
|
ecall
|
||||||
sret #should be treated as illegal instruction
|
sret #should be treated as illegal instruction
|
||||||
mret #mret in user mode and should be illegal
|
mret #mret in user mode and should be illegal
|
||||||
|
|
||||||
# switch to supervisor mode
|
# switch to supervisor mode
|
||||||
li a0, 1
|
li a0, 1
|
||||||
ecall
|
ecall
|
||||||
|
|
||||||
# Test read to stimecmp fails when MCOUNTEREN_TM is not set
|
# Test read to stimecmp fails when MCOUNTEREN_TM is not set
|
||||||
li t1, -3
|
li t1, -3
|
||||||
csrw stimecmp, t1
|
csrw stimecmp, t1
|
||||||
csrr t0, stimecmp
|
csrr t0, stimecmp
|
||||||
|
|
||||||
|
|
||||||
# satp write with mstatus.TVM = 1
|
# satp write with mstatus.TVM = 1
|
||||||
bseti t0, zero, 20
|
bseti t0, zero, 20
|
||||||
csrs mstatus, t0
|
csrs mstatus, t0
|
||||||
csrw satp, zero
|
csrw satp, zero
|
||||||
|
|
||||||
@ -62,7 +62,7 @@ sretdone:
|
|||||||
ecall # starts in M-mode
|
ecall # starts in M-mode
|
||||||
li t1, -3
|
li t1, -3
|
||||||
csrw stimecmp, t1 # sets stimecmp to large value to prevent it from interrupting immediately
|
csrw stimecmp, t1 # sets stimecmp to large value to prevent it from interrupting immediately
|
||||||
li t0, 2
|
li t0, 2
|
||||||
csrs mstatus, t0 # enables sie
|
csrs mstatus, t0 # enables sie
|
||||||
li t0, 32
|
li t0, 32
|
||||||
csrs sie, t0 # enables sie.stie
|
csrs sie, t0 # enables sie.stie
|
||||||
@ -111,7 +111,7 @@ sretdone:
|
|||||||
csrw fcsr, t0
|
csrw fcsr, t0
|
||||||
|
|
||||||
# switch to supervisor mode
|
# switch to supervisor mode
|
||||||
li a0, 1
|
li a0, 1
|
||||||
ecall
|
ecall
|
||||||
|
|
||||||
# Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs
|
# Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs
|
||||||
@ -125,8 +125,8 @@ sretdone:
|
|||||||
|
|
||||||
|
|
||||||
# Switch to machine mode
|
# Switch to machine mode
|
||||||
li a0, 3
|
li a0, 3
|
||||||
ecall
|
ecall
|
||||||
|
|
||||||
# Write to MCOUNTINHIBIT CSR
|
# Write to MCOUNTINHIBIT CSR
|
||||||
csrw mcountinhibit, t0
|
csrw mcountinhibit, t0
|
||||||
@ -149,7 +149,7 @@ sretdone:
|
|||||||
csrw 2828, t0
|
csrw 2828, t0
|
||||||
csrw 2829, t0
|
csrw 2829, t0
|
||||||
csrw 2830, t0
|
csrw 2830, t0
|
||||||
csrw 2831, t0
|
csrw 2831, t0
|
||||||
csrw 2832, t0
|
csrw 2832, t0
|
||||||
csrw 2833, t0
|
csrw 2833, t0
|
||||||
csrw 2834, t0
|
csrw 2834, t0
|
||||||
@ -165,7 +165,7 @@ sretdone:
|
|||||||
csrw 2844, t0
|
csrw 2844, t0
|
||||||
csrw 2845, t0
|
csrw 2845, t0
|
||||||
csrw 2846, t0
|
csrw 2846, t0
|
||||||
csrw 2847, t0
|
csrw 2847, t0
|
||||||
|
|
||||||
# Testing the HPMCOUNTERM performance counter: reading
|
# Testing the HPMCOUNTERM performance counter: reading
|
||||||
csrr t0, 2817
|
csrr t0, 2817
|
||||||
@ -181,7 +181,7 @@ sretdone:
|
|||||||
csrw 958, t0
|
csrw 958, t0
|
||||||
|
|
||||||
|
|
||||||
# Testing writes to MTVAL, MCAUSE
|
# Testing writes to MTVAL, MCAUSE
|
||||||
li t0, 0
|
li t0, 0
|
||||||
csrw mtval, t0
|
csrw mtval, t0
|
||||||
csrw mcause, t0
|
csrw mcause, t0
|
||||||
@ -195,7 +195,7 @@ sretdone:
|
|||||||
# Test writes to floating point CSRs
|
# Test writes to floating point CSRs
|
||||||
csrw frm, t0
|
csrw frm, t0
|
||||||
csrw fflags, t0
|
csrw fflags, t0
|
||||||
|
|
||||||
# CSRC MCOUNTEREN Register
|
# CSRC MCOUNTEREN Register
|
||||||
# Go to machine mode
|
# Go to machine mode
|
||||||
li a0, 3
|
li a0, 3
|
||||||
@ -228,7 +228,7 @@ sretdone:
|
|||||||
li a0, 0
|
li a0, 0
|
||||||
ecall
|
ecall
|
||||||
#set status TVM to 0 by writing to bit 20 of mstatus as 0
|
#set status TVM to 0 by writing to bit 20 of mstatus as 0
|
||||||
#bseti t0, zero, 20
|
#bseti t0, zero, 20
|
||||||
sfence.vma zero, zero
|
sfence.vma zero, zero
|
||||||
|
|
||||||
# Go to supervisor mode
|
# Go to supervisor mode
|
||||||
@ -241,7 +241,7 @@ sretdone:
|
|||||||
ecall
|
ecall
|
||||||
|
|
||||||
# Write to satp when status.TVM is 1 from machine mode
|
# Write to satp when status.TVM is 1 from machine mode
|
||||||
bseti t0, zero, 20
|
bseti t0, zero, 20
|
||||||
csrs mstatus, t0
|
csrs mstatus, t0
|
||||||
|
|
||||||
csrw satp, t0
|
csrw satp, t0
|
||||||
@ -315,15 +315,12 @@ sretdone:
|
|||||||
ecall # enter machine mode
|
ecall # enter machine mode
|
||||||
bseti t0, zero, 17
|
bseti t0, zero, 17
|
||||||
csrs mstatus, t0 # set MPRV
|
csrs mstatus, t0 # set MPRV
|
||||||
li t1, 0x00001800
|
li t1, 0x00001800
|
||||||
csrs mstatus, t1 # set MPP=3
|
csrs mstatus, t1 # set MPP=3
|
||||||
la t1, finished
|
la t1, finished
|
||||||
csrr t0, mepc
|
csrr t0, mepc
|
||||||
csrw mepc, t1 # set mepc for mret to jump to
|
csrw mepc, t1 # set mepc for mret to jump to
|
||||||
mret
|
mret
|
||||||
|
|
||||||
|
|
||||||
finished: j done
|
finished: j done
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@ -9,20 +9,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -35,19 +35,19 @@
|
|||||||
# run-elf.bash find this in project description
|
# run-elf.bash find this in project description
|
||||||
main:
|
main:
|
||||||
# Page table root address at 0x80010000
|
# Page table root address at 0x80010000
|
||||||
li t5, 0x9000000000080080 // try making asid = 0.
|
li t5, 0x9000000000080080 // try making asid = 0.
|
||||||
csrw satp, t5
|
csrw satp, t5
|
||||||
|
|
||||||
# sfence.vma x0, x0
|
# sfence.vma x0, x0
|
||||||
|
|
||||||
# switch to supervisor mode
|
# switch to supervisor mode
|
||||||
li a0, 1
|
li a0, 1
|
||||||
ecall
|
ecall
|
||||||
|
|
||||||
li t0, 0xC0000000
|
li t0, 0xC0000000
|
||||||
|
|
||||||
li t2, 0 # i = 0
|
li t2, 0 # i = 0
|
||||||
li t5, 0 # j = 0 // now use as a counter for new asid loop
|
li t5, 0 # j = 0 // now use as a counter for new asid loop
|
||||||
li t3, 32 # Max amount of Loops = 32
|
li t3, 32 # Max amount of Loops = 32
|
||||||
|
|
||||||
loop: bge t2, t3, finished # exit loop if i >= loops
|
loop: bge t2, t3, finished # exit loop if i >= loops
|
||||||
@ -56,7 +56,7 @@ loop: bge t2, t3, finished # exit loop if i >= loops
|
|||||||
sw t1, 0(t0)
|
sw t1, 0(t0)
|
||||||
fence.I
|
fence.I
|
||||||
jalr t0
|
jalr t0
|
||||||
li t5, 0x9001000000080080 // try making asid = 1
|
li t5, 0x9001000000080080 // try making asid = 1
|
||||||
csrw satp, t5
|
csrw satp, t5
|
||||||
jalr t0
|
jalr t0
|
||||||
li t5, 0x9000000000080080 // try making asid = 0
|
li t5, 0x9000000000080080 // try making asid = 0
|
||||||
@ -65,16 +65,16 @@ loop: bge t2, t3, finished # exit loop if i >= loops
|
|||||||
add t0, t0, t4
|
add t0, t0, t4
|
||||||
addi t2, t2, 1
|
addi t2, t2, 1
|
||||||
j loop
|
j loop
|
||||||
|
|
||||||
finished:
|
finished:
|
||||||
j done
|
j done
|
||||||
|
|
||||||
.data
|
.data
|
||||||
.align 19
|
.align 19
|
||||||
# level 3 Page table situated at 0x8008 0000, should point to 8008,1000
|
# level 3 Page table situated at 0x8008 0000, should point to 8008,1000
|
||||||
pagetable:
|
pagetable:
|
||||||
.8byte 0x200204C1
|
.8byte 0x200204C1
|
||||||
|
|
||||||
.align 12 // level 2 page table, contains direction to a gigapage
|
.align 12 // level 2 page table, contains direction to a gigapage
|
||||||
.8byte 0x0
|
.8byte 0x0
|
||||||
.8byte 0x0
|
.8byte 0x0
|
||||||
@ -129,5 +129,3 @@ pagetable:
|
|||||||
.8byte 0x200084CF
|
.8byte 0x200084CF
|
||||||
.8byte 0x200088CF
|
.8byte 0x200088CF
|
||||||
.8byte 0x20008CCF
|
.8byte 0x20008CCF
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@ -9,20 +9,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -34,7 +34,7 @@
|
|||||||
# run-elf.bash find this in project description
|
# run-elf.bash find this in project description
|
||||||
main:
|
main:
|
||||||
# Page table root address at 0x80010000
|
# Page table root address at 0x80010000
|
||||||
li t5, 0x9000000000080080 // try making asid = 0.
|
li t5, 0x9000000000080080 // try making asid = 0.
|
||||||
csrw satp, t5
|
csrw satp, t5
|
||||||
|
|
||||||
# switch to supervisor mode
|
# switch to supervisor mode
|
||||||
@ -82,9 +82,9 @@ nASID: #swap to different address space -> jump to each address
|
|||||||
.data
|
.data
|
||||||
.align 19
|
.align 19
|
||||||
# level 3 Page table situated at 0x8008 0000, should point to 8008,1000
|
# level 3 Page table situated at 0x8008 0000, should point to 8008,1000
|
||||||
pagetable:
|
pagetable:
|
||||||
.8byte 0x200204C1
|
.8byte 0x200204C1
|
||||||
|
|
||||||
.align 12 // level 2 page table, contains direction to a gigapageg
|
.align 12 // level 2 page table, contains direction to a gigapageg
|
||||||
.8byte 0x0
|
.8byte 0x0
|
||||||
.8byte 0x0
|
.8byte 0x0
|
||||||
@ -179,7 +179,3 @@ pagetable:
|
|||||||
.8byte 0x200084EF
|
.8byte 0x200084EF
|
||||||
.8byte 0x200088EF
|
.8byte 0x200088EF
|
||||||
.8byte 0x20008CEF
|
.8byte 0x20008CEF
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@ -8,20 +8,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -38,10 +38,10 @@ main:
|
|||||||
# sfence.vma x0, x0
|
# sfence.vma x0, x0
|
||||||
|
|
||||||
# switch to supervisor mode
|
# switch to supervisor mode
|
||||||
li a0, 1
|
li a0, 1
|
||||||
ecall
|
ecall
|
||||||
li t5, 0
|
li t5, 0
|
||||||
li t0, 0xC0200000 // go to first gigapage
|
li t0, 0xC0200000 // go to first gigapage
|
||||||
li t4, 0x40000000 // put this outside the loop.
|
li t4, 0x40000000 // put this outside the loop.
|
||||||
li t2, 0 # i = 0
|
li t2, 0 # i = 0
|
||||||
li t3, 64 # Max amount of Loops = 16
|
li t3, 64 # Max amount of Loops = 16
|
||||||
@ -63,97 +63,92 @@ finished:
|
|||||||
|
|
||||||
.align 16
|
.align 16
|
||||||
# Page table situated at 0x80010000
|
# Page table situated at 0x80010000
|
||||||
pagetable:
|
pagetable:
|
||||||
.8byte 0x200044C1
|
.8byte 0x200044C1
|
||||||
|
|
||||||
.align 12
|
.align 12
|
||||||
.8byte 0x000000CF //8000 0000
|
.8byte 0x000000CF //8000 0000
|
||||||
.8byte 0x100000CF
|
.8byte 0x100000CF
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
|
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
|
||||||
|
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
|
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
|
||||||
|
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
|
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
|
||||||
|
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
|
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
|
||||||
|
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
.8byte 0x200000CF
|
|
||||||
|
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
|
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200000CF
|
||||||
|
|
||||||
|
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
.8byte 0x200000CF
|
.8byte 0x200000CF
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@ -8,20 +8,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -38,7 +38,7 @@ main:
|
|||||||
# sfence.vma x0, x0
|
# sfence.vma x0, x0
|
||||||
|
|
||||||
# switch to supervisor mode
|
# switch to supervisor mode
|
||||||
li a0, 1
|
li a0, 1
|
||||||
ecall
|
ecall
|
||||||
|
|
||||||
li t0, 0x80015000
|
li t0, 0x80015000
|
||||||
@ -60,14 +60,14 @@ finished:
|
|||||||
|
|
||||||
.align 16
|
.align 16
|
||||||
# Page table situated at 0x80010000
|
# Page table situated at 0x80010000
|
||||||
pagetable:
|
pagetable:
|
||||||
.8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong
|
.8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong
|
||||||
|
|
||||||
.align 12
|
.align 12
|
||||||
.8byte 0x0000000000000000
|
.8byte 0x0000000000000000
|
||||||
.8byte 0x00000000200048C1
|
.8byte 0x00000000200048C1
|
||||||
.8byte 0x00000000200048C1
|
.8byte 0x00000000200048C1
|
||||||
|
|
||||||
|
|
||||||
.align 12
|
.align 12
|
||||||
.8byte 0x0000000020004CC1
|
.8byte 0x0000000020004CC1
|
||||||
@ -114,7 +114,7 @@ pagetable:
|
|||||||
.8byte 0x200074CF
|
.8byte 0x200074CF
|
||||||
.8byte 0x200078CF
|
.8byte 0x200078CF
|
||||||
.8byte 0x20007CCF
|
.8byte 0x20007CCF
|
||||||
|
|
||||||
.8byte 0x200080CF
|
.8byte 0x200080CF
|
||||||
.8byte 0x200084CF
|
.8byte 0x200084CF
|
||||||
.8byte 0x200088CF
|
.8byte 0x200088CF
|
||||||
|
|||||||
@ -8,20 +8,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -38,7 +38,7 @@ main:
|
|||||||
# sfence.vma x0, x0
|
# sfence.vma x0, x0
|
||||||
|
|
||||||
# switch to supervisor mode
|
# switch to supervisor mode
|
||||||
li a0, 1
|
li a0, 1
|
||||||
ecall
|
ecall
|
||||||
|
|
||||||
li t0, 0x1000
|
li t0, 0x1000
|
||||||
@ -57,7 +57,7 @@ loop: bge t2, t3, interim # exit loop if i >= loops
|
|||||||
interim:
|
interim:
|
||||||
li t0, 0xFFFFFFFF000
|
li t0, 0xFFFFFFFF000
|
||||||
li t2, 0 # i = 0
|
li t2, 0 # i = 0
|
||||||
|
|
||||||
|
|
||||||
loop2:bge t2, t3, finished # exit loop if i >= loops
|
loop2:bge t2, t3, finished # exit loop if i >= loops
|
||||||
lw t1, 0(t0)
|
lw t1, 0(t0)
|
||||||
@ -72,14 +72,14 @@ finished:
|
|||||||
|
|
||||||
.align 16
|
.align 16
|
||||||
# Page table situated at 0x80010000
|
# Page table situated at 0x80010000
|
||||||
pagetable:
|
pagetable:
|
||||||
.8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong
|
.8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong
|
||||||
|
|
||||||
.align 12
|
.align 12
|
||||||
.8byte 0x00000000200048C1
|
.8byte 0x00000000200048C1
|
||||||
.8byte 0x00000000200048C1
|
.8byte 0x00000000200048C1
|
||||||
.8byte 0x00000000200048C1
|
.8byte 0x00000000200048C1
|
||||||
|
|
||||||
|
|
||||||
.align 12
|
.align 12
|
||||||
.8byte 0x0000000020004CC1
|
.8byte 0x0000000020004CC1
|
||||||
@ -126,7 +126,7 @@ pagetable:
|
|||||||
.8byte 0x200074CF
|
.8byte 0x200074CF
|
||||||
.8byte 0x200078CF
|
.8byte 0x200078CF
|
||||||
.8byte 0x20007CCF
|
.8byte 0x20007CCF
|
||||||
|
|
||||||
.8byte 0x200080CF
|
.8byte 0x200080CF
|
||||||
.8byte 0x200084CF
|
.8byte 0x200084CF
|
||||||
.8byte 0x200088CF
|
.8byte 0x200088CF
|
||||||
|
|||||||
@ -8,20 +8,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -38,10 +38,10 @@ main:
|
|||||||
# sfence.vma x0, x0
|
# sfence.vma x0, x0
|
||||||
|
|
||||||
# switch to supervisor mode
|
# switch to supervisor mode
|
||||||
li a0, 1
|
li a0, 1
|
||||||
ecall
|
ecall
|
||||||
|
|
||||||
li t5, 0
|
li t5, 0
|
||||||
li t0, 0x84000000 // go to first megapage
|
li t0, 0x84000000 // go to first megapage
|
||||||
li t4, 0x200000 // put this outside the loop.
|
li t4, 0x200000 // put this outside the loop.
|
||||||
li t2, 0 # i = 0
|
li t2, 0 # i = 0
|
||||||
@ -63,19 +63,19 @@ finished:
|
|||||||
|
|
||||||
.align 16
|
.align 16
|
||||||
# Page table situated at 0x80010000
|
# Page table situated at 0x80010000
|
||||||
pagetable:
|
pagetable:
|
||||||
.8byte 0x200044C1
|
.8byte 0x200044C1
|
||||||
|
|
||||||
.align 12
|
.align 12
|
||||||
.8byte 0x00000000200048C1
|
.8byte 0x00000000200048C1
|
||||||
.8byte 0x00000000200048C1
|
.8byte 0x00000000200048C1
|
||||||
.8byte 0x00000000200048C1
|
.8byte 0x00000000200048C1
|
||||||
|
|
||||||
|
|
||||||
.align 12 // megapages starting at 8000 0000 going to 8480 0000 (32*2 MiB beyond that)
|
.align 12 // megapages starting at 8000 0000 going to 8480 0000 (32*2 MiB beyond that)
|
||||||
|
|
||||||
.8byte 0x200000CF // access 8000,0000
|
.8byte 0x200000CF // access 8000,0000
|
||||||
.8byte 0x200800CF // access 8020,0000
|
.8byte 0x200800CF // access 8020,0000
|
||||||
.8byte 0x201000CF // acesss 8040,0000
|
.8byte 0x201000CF // acesss 8040,0000
|
||||||
.8byte 0x201800CF // acesss 8060,0000
|
.8byte 0x201800CF // acesss 8060,0000
|
||||||
|
|
||||||
@ -85,37 +85,37 @@ pagetable:
|
|||||||
.8byte 0x203800CF // access 80E0,0000
|
.8byte 0x203800CF // access 80E0,0000
|
||||||
|
|
||||||
.8byte 0x204000CF // access 8100,0000
|
.8byte 0x204000CF // access 8100,0000
|
||||||
.8byte 0x204800CF
|
.8byte 0x204800CF
|
||||||
.8byte 0x205000CF
|
.8byte 0x205000CF
|
||||||
.8byte 0x205800CF
|
.8byte 0x205800CF
|
||||||
|
|
||||||
.8byte 0x206000CF // access 8180,0000
|
.8byte 0x206000CF // access 8180,0000
|
||||||
.8byte 0x206800CF
|
.8byte 0x206800CF
|
||||||
.8byte 0x207000CF
|
.8byte 0x207000CF
|
||||||
.8byte 0x207800CF
|
.8byte 0x207800CF
|
||||||
|
|
||||||
.8byte 0x208000CF // access 8200,0000
|
.8byte 0x208000CF // access 8200,0000
|
||||||
.8byte 0x208800CF
|
.8byte 0x208800CF
|
||||||
.8byte 0x209000CF
|
.8byte 0x209000CF
|
||||||
.8byte 0x209800CF
|
.8byte 0x209800CF
|
||||||
|
|
||||||
.8byte 0x20A000CF // access 8280,0000
|
.8byte 0x20A000CF // access 8280,0000
|
||||||
.8byte 0x20A800CF
|
.8byte 0x20A800CF
|
||||||
.8byte 0x20B000CF
|
.8byte 0x20B000CF
|
||||||
.8byte 0x20B800CF
|
.8byte 0x20B800CF
|
||||||
|
|
||||||
.8byte 0x20C000CF // access 8300,0000
|
.8byte 0x20C000CF // access 8300,0000
|
||||||
.8byte 0x20C800CF
|
.8byte 0x20C800CF
|
||||||
.8byte 0x20D000CF
|
.8byte 0x20D000CF
|
||||||
.8byte 0x20D800CF
|
.8byte 0x20D800CF
|
||||||
|
|
||||||
.8byte 0x20E000CF // access 8380,0000
|
.8byte 0x20E000CF // access 8380,0000
|
||||||
.8byte 0x20E800CF
|
.8byte 0x20E800CF
|
||||||
.8byte 0x20F000CF
|
.8byte 0x20F000CF
|
||||||
.8byte 0x20F800CF
|
.8byte 0x20F800CF
|
||||||
|
|
||||||
.8byte 0x200000CF // access 8000,0000 I AM REPEATING PTE TO SAVE TIME.
|
.8byte 0x200000CF // access 8000,0000 I AM REPEATING PTE TO SAVE TIME.
|
||||||
.8byte 0x200800CF // access 8020,0000
|
.8byte 0x200800CF // access 8020,0000
|
||||||
.8byte 0x201000CF // acesss 8040,0000
|
.8byte 0x201000CF // acesss 8040,0000
|
||||||
.8byte 0x201800CF // acesss 8060,0000
|
.8byte 0x201800CF // acesss 8060,0000
|
||||||
|
|
||||||
@ -125,40 +125,40 @@ pagetable:
|
|||||||
.8byte 0x203800CF // access 80E0,0000
|
.8byte 0x203800CF // access 80E0,0000
|
||||||
|
|
||||||
.8byte 0x204000CF // access 8100,0000
|
.8byte 0x204000CF // access 8100,0000
|
||||||
.8byte 0x204800CF
|
.8byte 0x204800CF
|
||||||
.8byte 0x205000CF
|
.8byte 0x205000CF
|
||||||
.8byte 0x205800CF
|
.8byte 0x205800CF
|
||||||
|
|
||||||
.8byte 0x206000CF // access 8180,0000
|
.8byte 0x206000CF // access 8180,0000
|
||||||
.8byte 0x206800CF
|
.8byte 0x206800CF
|
||||||
.8byte 0x207000CF
|
.8byte 0x207000CF
|
||||||
.8byte 0x207800CF
|
.8byte 0x207800CF
|
||||||
|
|
||||||
.8byte 0x208000CF // access 8200,0000
|
.8byte 0x208000CF // access 8200,0000
|
||||||
.8byte 0x208800CF
|
.8byte 0x208800CF
|
||||||
.8byte 0x209000CF
|
.8byte 0x209000CF
|
||||||
.8byte 0x209800CF
|
.8byte 0x209800CF
|
||||||
|
|
||||||
.8byte 0x20A000CF // access 8280,0000
|
.8byte 0x20A000CF // access 8280,0000
|
||||||
.8byte 0x20A800CF
|
.8byte 0x20A800CF
|
||||||
.8byte 0x20B000CF
|
.8byte 0x20B000CF
|
||||||
.8byte 0x20B800CF
|
.8byte 0x20B800CF
|
||||||
|
|
||||||
.8byte 0x20C000CF // access 8300,0000
|
.8byte 0x20C000CF // access 8300,0000
|
||||||
.8byte 0x20C800CF
|
.8byte 0x20C800CF
|
||||||
.8byte 0x20D000CF
|
.8byte 0x20D000CF
|
||||||
.8byte 0x20D800CF
|
.8byte 0x20D800CF
|
||||||
|
|
||||||
.8byte 0x20E000CF // access 8380,0000
|
.8byte 0x20E000CF // access 8380,0000
|
||||||
.8byte 0x20E800CF
|
.8byte 0x20E800CF
|
||||||
.8byte 0x20F000CF
|
.8byte 0x20F000CF
|
||||||
.8byte 0x20F800CF
|
.8byte 0x20F800CF
|
||||||
|
|
||||||
.8byte 0x20004CC1
|
.8byte 0x20004CC1
|
||||||
// Kilopage entry, for addresses from 8400, 0000 to 841F, FFFF
|
// Kilopage entry, for addresses from 8400, 0000 to 841F, FFFF
|
||||||
// point to ...
|
// point to ...
|
||||||
|
|
||||||
.align 12 // should start at 84000000
|
.align 12 // should start at 84000000
|
||||||
.8byte 0x210000CF
|
.8byte 0x210000CF
|
||||||
.8byte 0x210004CF
|
.8byte 0x210004CF
|
||||||
.8byte 0x210008CF
|
.8byte 0x210008CF
|
||||||
@ -198,4 +198,3 @@ pagetable:
|
|||||||
.8byte 0x210074CF
|
.8byte 0x210074CF
|
||||||
.8byte 0x210078CF
|
.8byte 0x210078CF
|
||||||
.8byte 0x21007CCF
|
.8byte 0x21007CCF
|
||||||
|
|
||||||
|
|||||||
@ -7,20 +7,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -42,11 +42,11 @@ main:
|
|||||||
# sfence.vma x0, x0
|
# sfence.vma x0, x0
|
||||||
|
|
||||||
# switch to supervisor mode
|
# switch to supervisor mode
|
||||||
li a0, 1
|
li a0, 1
|
||||||
ecall
|
ecall
|
||||||
li t5, 0
|
li t5, 0
|
||||||
li t2, 0x1000
|
li t2, 0x1000
|
||||||
li t0, 0x1000 // go to first gigapage
|
li t0, 0x1000 // go to first gigapage
|
||||||
li t4, 0x40000000 // put this outside the loop.
|
li t4, 0x40000000 // put this outside the loop.
|
||||||
|
|
||||||
lw t1, 1(t0) # load a misaligned aligned cached address
|
lw t1, 1(t0) # load a misaligned aligned cached address
|
||||||
@ -58,7 +58,7 @@ main:
|
|||||||
lw t1, 1(t0) # load a misaligned aligned uncached address should fault
|
lw t1, 1(t0) # load a misaligned aligned uncached address should fault
|
||||||
add t0, t0, t2 # go to the next page
|
add t0, t0, t2 # go to the next page
|
||||||
sw t1, 1(t0) # store to another misaligned uncached address should falt.
|
sw t1, 1(t0) # store to another misaligned uncached address should falt.
|
||||||
|
|
||||||
fence.I
|
fence.I
|
||||||
|
|
||||||
finished:
|
finished:
|
||||||
@ -68,14 +68,14 @@ finished:
|
|||||||
|
|
||||||
.align 16
|
.align 16
|
||||||
# Page table situated at 0x80010000
|
# Page table situated at 0x80010000
|
||||||
pagetable:
|
pagetable:
|
||||||
.8byte 0x200044C1
|
.8byte 0x200044C1
|
||||||
|
|
||||||
.align 12
|
.align 12
|
||||||
.8byte 0x00000000200048C1
|
.8byte 0x00000000200048C1
|
||||||
.8byte 0x00000000200048C1
|
.8byte 0x00000000200048C1
|
||||||
.8byte 0x00000000200048C1
|
.8byte 0x00000000200048C1
|
||||||
|
|
||||||
|
|
||||||
.align 12
|
.align 12
|
||||||
.8byte 0x0000000020004CC1
|
.8byte 0x0000000020004CC1
|
||||||
@ -122,7 +122,7 @@ pagetable:
|
|||||||
.8byte 0x200074CF
|
.8byte 0x200074CF
|
||||||
.8byte 0x200078CF
|
.8byte 0x200078CF
|
||||||
.8byte 0x20007CCF
|
.8byte 0x20007CCF
|
||||||
|
|
||||||
.8byte 0x200080CF
|
.8byte 0x200080CF
|
||||||
.8byte 0x200084CF
|
.8byte 0x200084CF
|
||||||
.8byte 0x200088CF
|
.8byte 0x200088CF
|
||||||
|
|||||||
@ -9,20 +9,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -36,13 +36,13 @@ main:
|
|||||||
slli t5, t5, 62
|
slli t5, t5, 62
|
||||||
csrs menvcfg, t5
|
csrs menvcfg, t5
|
||||||
# Page table root address at 0x80010000; SV48
|
# Page table root address at 0x80010000; SV48
|
||||||
li t5, 0x9000000000080010
|
li t5, 0x9000000000080010
|
||||||
csrw satp, t5
|
csrw satp, t5
|
||||||
|
|
||||||
# sfence.vma x0, x0
|
# sfence.vma x0, x0
|
||||||
|
|
||||||
# switch to supervisor mode
|
# switch to supervisor mode
|
||||||
li a0, 1
|
li a0, 1
|
||||||
ecall
|
ecall
|
||||||
|
|
||||||
li t4, 0x200000 # address step size
|
li t4, 0x200000 # address step size
|
||||||
@ -90,7 +90,7 @@ finished:
|
|||||||
jr a1
|
jr a1
|
||||||
|
|
||||||
changetoipfhandler:
|
changetoipfhandler:
|
||||||
li a0, 3
|
li a0, 3
|
||||||
ecall # switch to machine mode
|
ecall # switch to machine mode
|
||||||
la a0, ipf_handler
|
la a0, ipf_handler
|
||||||
csrw mtvec, a0 # point to new handler
|
csrw mtvec, a0 # point to new handler
|
||||||
@ -99,7 +99,7 @@ changetoipfhandler:
|
|||||||
ret
|
ret
|
||||||
|
|
||||||
changetodefaulthandler:
|
changetodefaulthandler:
|
||||||
li a0, 3
|
li a0, 3
|
||||||
ecall # switch to machine mode
|
ecall # switch to machine mode
|
||||||
la a0, trap_handler
|
la a0, trap_handler
|
||||||
csrw mtvec, a0 # point to new handler
|
csrw mtvec, a0 # point to new handler
|
||||||
@ -137,7 +137,7 @@ ipf:
|
|||||||
|
|
||||||
.align 16
|
.align 16
|
||||||
# root Page table situated at 0x80010000
|
# root Page table situated at 0x80010000
|
||||||
pagetable:
|
pagetable:
|
||||||
.8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong
|
.8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong
|
||||||
|
|
||||||
# next page table at 0x80011000
|
# next page table at 0x80011000
|
||||||
@ -146,7 +146,7 @@ pagetable:
|
|||||||
.8byte 0x00000000200058C1 # gigapage at 0x40000000 used for non-NAPOT with PPN bit 3 set
|
.8byte 0x00000000200058C1 # gigapage at 0x40000000 used for non-NAPOT with PPN bit 3 set
|
||||||
.8byte 0x00000000200048C1 # gigapage at 0x80000000 used for testing NAPOT huge pages
|
.8byte 0x00000000200048C1 # gigapage at 0x80000000 used for testing NAPOT huge pages
|
||||||
.8byte 0x00000000200050C1 # gigapage at 0xC0000000 mapped to ill-formed NAPOT with wrong PPN
|
.8byte 0x00000000200050C1 # gigapage at 0xC0000000 mapped to ill-formed NAPOT with wrong PPN
|
||||||
|
|
||||||
|
|
||||||
# Next page table at 0x80012000 for gigapage at 0x80000000
|
# Next page table at 0x80012000 for gigapage at 0x80000000
|
||||||
.align 12
|
.align 12
|
||||||
@ -231,7 +231,7 @@ pagetable:
|
|||||||
.8byte 0x80000000200060CF
|
.8byte 0x80000000200060CF
|
||||||
.8byte 0x80000000200060CF
|
.8byte 0x80000000200060CF
|
||||||
.8byte 0x80000000200060CF
|
.8byte 0x80000000200060CF
|
||||||
|
|
||||||
.8byte 0x800000002000A0CF
|
.8byte 0x800000002000A0CF
|
||||||
.8byte 0x800000002000A0CF
|
.8byte 0x800000002000A0CF
|
||||||
.8byte 0x800000002000A0CF
|
.8byte 0x800000002000A0CF
|
||||||
@ -437,4 +437,3 @@ pagetable:
|
|||||||
.8byte 0x00000000200060CF
|
.8byte 0x00000000200060CF
|
||||||
.8byte 0x000000002000A0CF
|
.8byte 0x000000002000A0CF
|
||||||
.8byte 0x000000002000E0CF
|
.8byte 0x000000002000E0CF
|
||||||
|
|
||||||
|
|||||||
@ -8,20 +8,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -38,10 +38,10 @@ main:
|
|||||||
# sfence.vma x0, x0
|
# sfence.vma x0, x0
|
||||||
|
|
||||||
# switch to supervisor mode
|
# switch to supervisor mode
|
||||||
li a0, 1
|
li a0, 1
|
||||||
ecall
|
ecall
|
||||||
li t5, 0
|
li t5, 0
|
||||||
li t0, 0x80000000 // go to first gigapage
|
li t0, 0x80000000 // go to first gigapage
|
||||||
li t4, 0x8000000000 // put this outside the loop.
|
li t4, 0x8000000000 // put this outside the loop.
|
||||||
li t2, 0 # i = 0
|
li t2, 0 # i = 0
|
||||||
li t3, 64 # run through 64 PTEs
|
li t3, 64 # run through 64 PTEs
|
||||||
@ -63,7 +63,7 @@ finished:
|
|||||||
|
|
||||||
.align 16
|
.align 16
|
||||||
# Page table situated at 0x80010000
|
# Page table situated at 0x80010000
|
||||||
pagetable:
|
pagetable:
|
||||||
.8byte 0x0CF
|
.8byte 0x0CF
|
||||||
.8byte 0x0CF
|
.8byte 0x0CF
|
||||||
.8byte 0x0CF
|
.8byte 0x0CF
|
||||||
@ -142,4 +142,4 @@ pagetable:
|
|||||||
.8byte 0x0CF
|
.8byte 0x0CF
|
||||||
.8byte 0x0CF
|
.8byte 0x0CF
|
||||||
.8byte 0x0CF
|
.8byte 0x0CF
|
||||||
.8byte 0x0CF
|
.8byte 0x0CF
|
||||||
|
|||||||
@ -7,20 +7,20 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
@ -38,21 +38,21 @@ main:
|
|||||||
# store ret instruction in case we jump to an address mapping to 80000000
|
# store ret instruction in case we jump to an address mapping to 80000000
|
||||||
li t0, 0x80000000
|
li t0, 0x80000000
|
||||||
li t5, 0x8082 # return instruction opcode
|
li t5, 0x8082 # return instruction opcode
|
||||||
sw t5, 0(t0)
|
sw t5, 0(t0)
|
||||||
fence.i
|
fence.i
|
||||||
|
|
||||||
# Test not being able to write illegal SATP mode
|
# Test not being able to write illegal SATP mode
|
||||||
li t5, 0xA000000000080010
|
li t5, 0xA000000000080010
|
||||||
csrw satp, t5
|
csrw satp, t5
|
||||||
|
|
||||||
# Page table root address at 0x80010000; SV48
|
# Page table root address at 0x80010000; SV48
|
||||||
li t5, 0x9000000000080010
|
li t5, 0x9000000000080010
|
||||||
csrw satp, t5
|
csrw satp, t5
|
||||||
|
|
||||||
# sfence.vma x0, x0
|
# sfence.vma x0, x0
|
||||||
|
|
||||||
# switch to supervisor mode
|
# switch to supervisor mode
|
||||||
li a0, 1
|
li a0, 1
|
||||||
ecall
|
ecall
|
||||||
|
|
||||||
# Instruction fetch from misaligned pages
|
# Instruction fetch from misaligned pages
|
||||||
@ -65,27 +65,27 @@ main:
|
|||||||
jalr ra, t0 # jump to misaligned megapage
|
jalr ra, t0 # jump to misaligned megapage
|
||||||
li t0, 0x7FFFFFFF80000000
|
li t0, 0x7FFFFFFF80000000
|
||||||
|
|
||||||
|
|
||||||
jalr ra, t0 # jump to page with UpperBitsUnequal
|
jalr ra, t0 # jump to page with UpperBitsUnequal
|
||||||
li t0, 0x0000000080C00000
|
li t0, 0x0000000080C00000
|
||||||
jalr ra, t0 # jump to page with bad reserved bits 60:54 in PTE
|
jalr ra, t0 # jump to page with bad reserved bits 60:54 in PTE
|
||||||
|
|
||||||
# test with ENVCFG_ADUE = 1: switch to machine mode, set ADUE, access page with A=0, clear ADUE,
|
# test with ENVCFG_ADUE = 1: switch to machine mode, set ADUE, access page with A=0, clear ADUE,
|
||||||
li a0, 3
|
li a0, 3
|
||||||
ecall # switch to machine mode
|
ecall # switch to machine mode
|
||||||
li t0, 1
|
li t0, 1
|
||||||
slli t0, t0, 61
|
slli t0, t0, 61
|
||||||
csrs menvcfg, t0 # set menvcfg.ADUE
|
csrs menvcfg, t0 # set menvcfg.ADUE
|
||||||
li a0, 1
|
li a0, 1
|
||||||
ecall # switch back to supervisor mode
|
ecall # switch back to supervisor mode
|
||||||
li t0, 0x0000000080E00000
|
li t0, 0x0000000080E00000
|
||||||
jalr ra, t0 # jump to page without accessed bit yet set
|
jalr ra, t0 # jump to page without accessed bit yet set
|
||||||
li a0, 3
|
li a0, 3
|
||||||
ecall # switch to machine mode
|
ecall # switch to machine mode
|
||||||
li t0, 1
|
li t0, 1
|
||||||
slli t0, t0, 61
|
slli t0, t0, 61
|
||||||
csrc menvcfg, t0 # clear menvcfg.ADUE
|
csrc menvcfg, t0 # clear menvcfg.ADUE
|
||||||
li a0, 1
|
li a0, 1
|
||||||
ecall # switch back to supervisor mode
|
ecall # switch back to supervisor mode
|
||||||
|
|
||||||
# exercise malformed PBMT pages
|
# exercise malformed PBMT pages
|
||||||
@ -147,9 +147,9 @@ ConcurrentICacheMissDTLBMiss:
|
|||||||
|
|
||||||
# jump to address for TLB miss to trigger HPTW to make access with DisableTranslation = 1, Translate = 0
|
# jump to address for TLB miss to trigger HPTW to make access with DisableTranslation = 1, Translate = 0
|
||||||
li t0, 0x80805000
|
li t0, 0x80805000
|
||||||
jalr ra, t0
|
jalr ra, t0
|
||||||
li t0, 0x80807000 # again, triggering setting access bit
|
li t0, 0x80807000 # again, triggering setting access bit
|
||||||
jalr ra, t0
|
jalr ra, t0
|
||||||
|
|
||||||
# atomic access to uncachable memory
|
# atomic access to uncachable memory
|
||||||
#li t0, 0x80806000
|
#li t0, 0x80806000
|
||||||
@ -168,7 +168,7 @@ ConcurrentICacheMissDTLBMiss:
|
|||||||
jalr ra, t0 # jump to page to exercise ITLB with PBMT !=0 when ENVCFG_PMTE=0
|
jalr ra, t0 # jump to page to exercise ITLB with PBMT !=0 when ENVCFG_PMTE=0
|
||||||
|
|
||||||
# Load and AMO operation on page table entry that causes access fault
|
# Load and AMO operation on page table entry that causes access fault
|
||||||
li t0, 0x81000000
|
li t0, 0x81000000
|
||||||
lw t1, 0(t0)
|
lw t1, 0(t0)
|
||||||
sfence.vma
|
sfence.vma
|
||||||
amoadd.w t0, t0, 0(t0)
|
amoadd.w t0, t0, 0(t0)
|
||||||
@ -190,7 +190,7 @@ ConcurrentICacheMissDTLBMiss:
|
|||||||
lw t1, 0(t0)
|
lw t1, 0(t0)
|
||||||
|
|
||||||
# AMO operation on page table entry that causes page fault due to malformed PBMT
|
# AMO operation on page table entry that causes page fault due to malformed PBMT
|
||||||
li t0, 0x81200000
|
li t0, 0x81200000
|
||||||
jalr t0 # Attempt to fetch instruction from address causing faulty page walk
|
jalr t0 # Attempt to fetch instruction from address causing faulty page walk
|
||||||
lw t1, 0(t0)
|
lw t1, 0(t0)
|
||||||
sfence.vma
|
sfence.vma
|
||||||
@ -198,10 +198,10 @@ ConcurrentICacheMissDTLBMiss:
|
|||||||
|
|
||||||
# point top-level page table to an illegal address and verify it faults
|
# point top-level page table to an illegal address and verify it faults
|
||||||
li t0, 0x9000000000070000 # trap handler at non-existing memory location
|
li t0, 0x9000000000070000 # trap handler at non-existing memory location
|
||||||
csrw satp, t0 # should cause trap
|
csrw satp, t0 # should cause trap
|
||||||
sfence.vma
|
sfence.vma
|
||||||
nop
|
nop
|
||||||
|
|
||||||
|
|
||||||
# change back to default trap handler after checking everything that might cause an instruction page fault
|
# change back to default trap handler after checking everything that might cause an instruction page fault
|
||||||
jal changetodefaulthandler
|
jal changetodefaulthandler
|
||||||
@ -263,7 +263,7 @@ ConcurrentICacheMissDTLBMiss:
|
|||||||
ecall
|
ecall
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
# wrap up
|
# wrap up
|
||||||
li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry
|
li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry
|
||||||
@ -274,7 +274,7 @@ backandforth:
|
|||||||
ret
|
ret
|
||||||
|
|
||||||
changetoipfhandler:
|
changetoipfhandler:
|
||||||
li a0, 3
|
li a0, 3
|
||||||
ecall # switch to machine mode
|
ecall # switch to machine mode
|
||||||
la a0, ipf_handler
|
la a0, ipf_handler
|
||||||
csrw mtvec, a0 # point to new handler
|
csrw mtvec, a0 # point to new handler
|
||||||
@ -283,7 +283,7 @@ changetoipfhandler:
|
|||||||
ret
|
ret
|
||||||
|
|
||||||
changetodefaulthandler:
|
changetodefaulthandler:
|
||||||
li a0, 3
|
li a0, 3
|
||||||
ecall # switch to machine mode
|
ecall # switch to machine mode
|
||||||
la a0, trap_handler
|
la a0, trap_handler
|
||||||
csrw mtvec, a0 # point to new handler
|
csrw mtvec, a0 # point to new handler
|
||||||
@ -301,8 +301,8 @@ ipf_handler:
|
|||||||
csrrw tp, mscratch, tp # swap MSCRATCH and tp
|
csrrw tp, mscratch, tp # swap MSCRATCH and tp
|
||||||
sd t0, 0(tp) # Save t0 and t1 on the stack
|
sd t0, 0(tp) # Save t0 and t1 on the stack
|
||||||
sd t1, -8(tp)
|
sd t1, -8(tp)
|
||||||
li t5, 0x9000000000080010
|
li t5, 0x9000000000080010
|
||||||
csrw satp, t5 # make sure we are pointing to the root page table
|
csrw satp, t5 # make sure we are pointing to the root page table
|
||||||
csrr t0, mcause # Check the cause
|
csrr t0, mcause # Check the cause
|
||||||
li t1, 8 # is it an ecall trap?
|
li t1, 8 # is it an ecall trap?
|
||||||
andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11
|
andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11
|
||||||
@ -329,7 +329,7 @@ fixsatptraphandler:
|
|||||||
|
|
||||||
.align 16
|
.align 16
|
||||||
# root Page table situated at 0x80010000
|
# root Page table situated at 0x80010000
|
||||||
pagetable:
|
pagetable:
|
||||||
.8byte 0x200044C1 # VA 0x00000000-0x7F_FFFFFFFF: PTE at 0x80011000 C1 dirty, accessed, valid
|
.8byte 0x200044C1 # VA 0x00000000-0x7F_FFFFFFFF: PTE at 0x80011000 C1 dirty, accessed, valid
|
||||||
.8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000
|
.8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000
|
||||||
.8byte 0x00000000000000CF # access fault terapage at 0x100_00000000
|
.8byte 0x00000000000000CF # access fault terapage at 0x100_00000000
|
||||||
@ -345,9 +345,9 @@ pagetable:
|
|||||||
.8byte 0x0
|
.8byte 0x0
|
||||||
.8byte 0x0
|
.8byte 0x0
|
||||||
.8byte 0x0
|
.8byte 0x0
|
||||||
SpecialPage:
|
SpecialPage:
|
||||||
.8byte 0x00000000200000CF # 0x2_0000_0000 1GiB page1
|
.8byte 0x00000000200000CF # 0x2_0000_0000 1GiB page1
|
||||||
|
|
||||||
|
|
||||||
# Next page table at 0x80012000 for gigapage at 0x80000000
|
# Next page table at 0x80012000 for gigapage at 0x80000000
|
||||||
.align 12
|
.align 12
|
||||||
@ -429,7 +429,7 @@ SpecialPage:
|
|||||||
.8byte 0x80000000200060CF
|
.8byte 0x80000000200060CF
|
||||||
.8byte 0x80000000200060CF
|
.8byte 0x80000000200060CF
|
||||||
.8byte 0x80000000200060CF
|
.8byte 0x80000000200060CF
|
||||||
|
|
||||||
.8byte 0x800000002000A0CF
|
.8byte 0x800000002000A0CF
|
||||||
.8byte 0x800000002000A0CF
|
.8byte 0x800000002000A0CF
|
||||||
.8byte 0x800000002000A0CF
|
.8byte 0x800000002000A0CF
|
||||||
@ -475,4 +475,3 @@ SpecialPage:
|
|||||||
.8byte 0x00000000200000CF # valid rwx for VA 80805000 for covering ITLB translate
|
.8byte 0x00000000200000CF # valid rwx for VA 80805000 for covering ITLB translate
|
||||||
.8byte 0x20000000200000CF # PBMT=1 for VA 80806000 for covering ITLB BadPBMT
|
.8byte 0x20000000200000CF # PBMT=1 for VA 80806000 for covering ITLB BadPBMT
|
||||||
.8byte 0x000000002000000F # valid rwx for VA 80807000 for covering UpdateDA
|
.8byte 0x000000002000000F # valid rwx for VA 80807000 for covering UpdateDA
|
||||||
|
|
||||||
|
|||||||
@ -7,27 +7,27 @@
|
|||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
// Cover IMMU vm64check block by jumping to illegal virtual addresses
|
// Cover IMMU vm64check block by jumping to illegal virtual addresses
|
||||||
// Need a nonstandard trap handler to deal with returns from theses jumps
|
// Need a nonstandard trap handler to deal with returns from theses jumps
|
||||||
// assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]);
|
// assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]);
|
||||||
// assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]);
|
// assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]);
|
||||||
// assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47;
|
// assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47;
|
||||||
|
|
||||||
.section .text.init
|
.section .text.init
|
||||||
@ -41,9 +41,9 @@ rvtest_entry_point:
|
|||||||
csrw mtvec, t0 # Initialize MTVEC to trap_handler
|
csrw mtvec, t0 # Initialize MTVEC to trap_handler
|
||||||
# set up PMP so user and supervisor mode can access full address space
|
# set up PMP so user and supervisor mode can access full address space
|
||||||
csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX
|
csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX
|
||||||
li t0, 0xFFFFFFFF
|
li t0, 0xFFFFFFFF
|
||||||
csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
|
csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
|
||||||
|
|
||||||
# SATP in non-39 mode
|
# SATP in non-39 mode
|
||||||
csrw satp, zero
|
csrw satp, zero
|
||||||
|
|
||||||
@ -118,8 +118,8 @@ self_loop:
|
|||||||
trap_handler:
|
trap_handler:
|
||||||
csrw mepc, ra # return to address in ra
|
csrw mepc, ra # return to address in ra
|
||||||
mret
|
mret
|
||||||
|
|
||||||
.section .tohost
|
.section .tohost
|
||||||
tohost: # write to HTIF
|
tohost: # write to HTIF
|
||||||
.dword 0
|
.dword 0
|
||||||
fromhost:
|
fromhost:
|
||||||
@ -146,7 +146,7 @@ topofstack:
|
|||||||
lw t1, 0(t0)
|
lw t1, 0(t0)
|
||||||
li t1, 0x0000010080000000
|
li t1, 0x0000010080000000
|
||||||
lw t1, 0(t0)
|
lw t1, 0(t0)
|
||||||
li t0, 0x8000000000000000
|
li t0, 0x8000000000000000
|
||||||
csrw satp, t0 # SV39 mode
|
csrw satp, t0 # SV39 mode
|
||||||
li t0, 0x0000000080000000
|
li t0, 0x0000000080000000
|
||||||
lw t1, 0(t0)
|
lw t1, 0(t0)
|
||||||
@ -158,7 +158,7 @@ topofstack:
|
|||||||
lw t1, 0(t0)
|
lw t1, 0(t0)
|
||||||
li t1, 0x0000010080000000
|
li t1, 0x0000010080000000
|
||||||
lw t1, 0(t0)
|
lw t1, 0(t0)
|
||||||
li t0, 0x9000000000000000
|
li t0, 0x9000000000000000
|
||||||
csrw satp, t0 # SV48 mode
|
csrw satp, t0 # SV48 mode
|
||||||
li t0, 0x0000000080000000
|
li t0, 0x0000000080000000
|
||||||
lw t1, 0(t0)
|
lw t1, 0(t0)
|
||||||
@ -170,5 +170,5 @@ topofstack:
|
|||||||
lw t1, 0(t0)
|
lw t1, 0(t0)
|
||||||
li t1, 0x0000010080000000
|
li t1, 0x0000010080000000
|
||||||
lw t1, 0(t0)
|
lw t1, 0(t0)
|
||||||
li t0, 0x0000000000000000
|
li t0, 0x0000000000000000
|
||||||
csrw satp, t0 # disable virtual memory
|
csrw satp, t0 # disable virtual memory
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
james.stine@okstate.edu 14 Jan 2022
|
james.stine@okstate.edu 14 Jan 2022\
|
||||||
jcarlin@hmc.edu Sept 2024
|
jcarlin@hmc.edu Sept 2024
|
||||||
|
|
||||||
## TestFloat for CVW
|
# TestFloat for CVW
|
||||||
|
|
||||||
The CVW floating point unit is tested using testvectors from the Berkeley TestFloat suite, written originally by John Hauser.
|
The CVW floating point unit is tested using testvectors from the Berkeley TestFloat suite, written originally by John Hauser.
|
||||||
|
|
||||||
@ -9,7 +9,7 @@ TestFloat and SoftFloat can be found as submodules in the addins directory, and
|
|||||||
- TestFloat: https://github.com/ucb-bar/berkeley-testfloat-3
|
- TestFloat: https://github.com/ucb-bar/berkeley-testfloat-3
|
||||||
- SoftFloat: https://github.com/ucb-bar/berkeley-softfloat-3
|
- SoftFloat: https://github.com/ucb-bar/berkeley-softfloat-3
|
||||||
|
|
||||||
### Compiling SoftFloat/TestFloat and Generating Testvectors
|
## Compiling SoftFloat/TestFloat and Generating Testvectors
|
||||||
|
|
||||||
The entire testvector generation process can be performed by running make in this directory.
|
The entire testvector generation process can be performed by running make in this directory.
|
||||||
|
|
||||||
@ -17,7 +17,7 @@ The entire testvector generation process can be performed by running make in thi
|
|||||||
make --jobs
|
make --jobs
|
||||||
```
|
```
|
||||||
|
|
||||||
This compiles SoftFloat for an x86_64 environment in its build/Linux-x86_64-GCC directory using the `SPECIALIZE_TYPE=RISCV` flag to get RISC-V behavior. TestFloat is then compiled in its build/Linux-x86_64-GCC directory using this SoftFloat library.
|
This compiles SoftFloat for an x86_64 environment in its `build/Linux-x86_64-GCC` directory using the `SPECIALIZE_TYPE=RISCV` flag to get RISC-V behavior. TestFloat is then compiled in its `build/Linux-x86_64-GCC` directory using this SoftFloat library.
|
||||||
|
|
||||||
The Makefile in the vectors subdirectory of this directory is then called to generate testvectors for each rounding mode and operation. It also puts an underscore between each vector instead of a space to allow SystemVerilog `$readmemh` to read correctly.
|
The Makefile in the vectors subdirectory of this directory is then called to generate testvectors for each rounding mode and operation. It also puts an underscore between each vector instead of a space to allow SystemVerilog `$readmemh` to read correctly.
|
||||||
|
|
||||||
@ -25,7 +25,7 @@ Testvectors for the combined integer floating-point divider are also generated.
|
|||||||
|
|
||||||
Although not needed, a `case.sh` script is included to change the case of the hex output. This is for those that do not like to see hexadecimal capitalized :P.
|
Although not needed, a `case.sh` script is included to change the case of the hex output. This is for those that do not like to see hexadecimal capitalized :P.
|
||||||
|
|
||||||
### Running TestFloat Vectors on Wally
|
## Running TestFloat Vectors on Wally
|
||||||
|
|
||||||
TestFloat is run using the standard Wally simulation commands.
|
TestFloat is run using the standard Wally simulation commands.
|
||||||
|
|
||||||
@ -40,15 +40,15 @@ wsim <config> <test> --tb testbench_fp
|
|||||||
```
|
```
|
||||||
The choices for `<test>` are as follows:
|
The choices for `<test>` are as follows:
|
||||||
|
|
||||||
>cvtint - test integer conversion unit (fcvtint)
|
cvtint - test integer conversion unit (fcvtint)
|
||||||
cvtfp - test floating-point conversion unit (fcvtfp)
|
cvtfp - test floating-point conversion unit (fcvtfp)
|
||||||
cmp - test comparison unit's LT, LE, EQ opperations (fcmp)
|
cmp - test comparison unit's LT, LE, EQ opperations (fcmp)
|
||||||
add - test addition
|
add - test addition
|
||||||
fma - test fma
|
fma - test fma
|
||||||
mul - test mult with fma
|
mul - test mult with fma
|
||||||
sub - test subtraction
|
sub - test subtraction
|
||||||
div - test division
|
div - test division
|
||||||
sqrt - test square root
|
sqrt - test square root
|
||||||
|
|
||||||
Any config that includes floating point support can be used. Each test will test all its vectors for all precisions supported by the given config.
|
Any config that includes floating point support can be used. Each test will test all its vectors for all precisions supported by the given config.
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user